octeontx2/nic/cn10k.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Marvell RVU Ethernet driver
0003  *
0004  * Copyright (C) 2021 Marvell.
0005  *
0006  */
0007
0008 #ifndef CN10K_H
0009 #define CN10K_H
0010
0011 #include "otx2_common.h"
0012
0013 static inline int mtu_to_dwrr_weight(struct otx2_nic *pfvf, int mtu)
0014 {
0015     u32 weight;
0016
0017     /* On OTx2, since AF returns DWRR_MTU as '1', this logic
0018      * will work on those silicons as well.
0019      */
0020     weight = mtu / pfvf->hw.dwrr_mtu;
0021     if (mtu % pfvf->hw.dwrr_mtu)
0022         weight += 1;
0023
0024     return weight;
0025 }
0026
0027 void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
0028 void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq, int size, int qidx);
0029 int cn10k_sq_aq_init(void *dev, u16 qidx, u16 sqb_aura);
0030 int cn10k_lmtst_init(struct otx2_nic *pfvf);
0031 int cn10k_free_all_ipolicers(struct otx2_nic *pfvf);
0032 int cn10k_alloc_matchall_ipolicer(struct otx2_nic *pfvf);
0033 int cn10k_free_matchall_ipolicer(struct otx2_nic *pfvf);
0034 int cn10k_set_matchall_ipolicer_rate(struct otx2_nic *pfvf,
0035                      u32 burst, u64 rate);
0036 int cn10k_map_unmap_rq_policer(struct otx2_nic *pfvf, int rq_idx,
0037                    u16 policer, bool map);
0038 int cn10k_alloc_leaf_profile(struct otx2_nic *pfvf, u16 *leaf);
0039 int cn10k_set_ipolicer_rate(struct otx2_nic *pfvf, u16 profile,
0040                 u32 burst, u64 rate, bool pps);
0041 int cn10k_free_leaf_profile(struct otx2_nic *pfvf, u16 leaf);
0042 #endif /* CN10K_H */