octeontx2/af/rvu_sdp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Marvell RVU Admin Function driver
0003  *
0004  * Copyright (C) 2021 Marvell.
0005  *
0006  */
0007
0008 #include <linux/pci.h>
0009 #include "rvu.h"
0010
0011 /* SDP PF device id */
0012 #define PCI_DEVID_OTX2_SDP_PF   0xA0F6
0013
0014 /* Maximum SDP blocks in a chip */
0015 #define MAX_SDP     2
0016
0017 /* SDP PF number */
0018 static int sdp_pf_num[MAX_SDP] = {-1, -1};
0019
0020 bool is_sdp_pfvf(u16 pcifunc)
0021 {
0022     u16 pf = rvu_get_pf(pcifunc);
0023     u32 found = 0, i = 0;
0024
0025     while (i < MAX_SDP) {
0026         if (pf == sdp_pf_num[i])
0027             found = 1;
0028         i++;
0029     }
0030
0031     if (!found)
0032         return false;
0033
0034     return true;
0035 }
0036
0037 bool is_sdp_pf(u16 pcifunc)
0038 {
0039     return (is_sdp_pfvf(pcifunc) &&
0040         !(pcifunc & RVU_PFVF_FUNC_MASK));
0041 }
0042
0043 bool is_sdp_vf(u16 pcifunc)
0044 {
0045     return (is_sdp_pfvf(pcifunc) &&
0046         !!(pcifunc & RVU_PFVF_FUNC_MASK));
0047 }
0048
0049 int rvu_sdp_init(struct rvu *rvu)
0050 {
0051     struct pci_dev *pdev = NULL;
0052     struct rvu_pfvf *pfvf;
0053     u32 i = 0;
0054
0055     while ((i < MAX_SDP) && (pdev = pci_get_device(PCI_VENDOR_ID_CAVIUM,
0056                                PCI_DEVID_OTX2_SDP_PF,
0057                                pdev)) != NULL) {
0058         /* The RVU PF number is one less than bus number */
0059         sdp_pf_num[i] = pdev->bus->number - 1;
0060         pfvf = &rvu->pf[sdp_pf_num[i]];
0061
0062         pfvf->sdp_info = devm_kzalloc(rvu->dev,
0063                           sizeof(struct sdp_node_info),
0064                           GFP_KERNEL);
0065         if (!pfvf->sdp_info)
0066             return -ENOMEM;
0067
0068         dev_info(rvu->dev, "SDP PF number:%d\n", sdp_pf_num[i]);
0069
0070         put_device(&pdev->dev);
0071         i++;
0072     }
0073
0074     return 0;
0075 }
0076
0077 int
0078 rvu_mbox_handler_set_sdp_chan_info(struct rvu *rvu,
0079                    struct sdp_chan_info_msg *req,
0080                    struct msg_rsp *rsp)
0081 {
0082     struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
0083
0084     memcpy(pfvf->sdp_info, &req->info, sizeof(struct sdp_node_info));
0085     dev_info(rvu->dev, "AF: SDP%d max_vfs %d num_pf_rings %d pf_srn %d\n",
0086          req->info.node_id, req->info.max_vfs, req->info.num_pf_rings,
0087          req->info.pf_srn);
0088     return 0;
0089 }
0090
0091 int
0092 rvu_mbox_handler_get_sdp_chan_info(struct rvu *rvu, struct msg_req *req,
0093                    struct sdp_get_chan_info_msg *rsp)
0094 {
0095     struct rvu_hwinfo *hw = rvu->hw;
0096     int blkaddr;
0097
0098     if (!hw->cap.programmable_chans) {
0099         rsp->chan_base = NIX_CHAN_SDP_CH_START;
0100         rsp->num_chan = NIX_CHAN_SDP_NUM_CHANS;
0101     } else {
0102         blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0);
0103         rsp->chan_base = hw->sdp_chan_base;
0104         rsp->num_chan = rvu_read64(rvu, blkaddr, NIX_AF_CONST1) & 0xFFFUL;
0105     }
0106
0107     return 0;
0108 }