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0008 #ifndef RVU_REG_H
0009 #define RVU_REG_H
0010
0011
0012 #define RVU_AF_MSIXTR_BASE (0x10)
0013 #define RVU_AF_ECO (0x20)
0014 #define RVU_AF_BLK_RST (0x30)
0015 #define RVU_AF_PF_BAR4_ADDR (0x40)
0016 #define RVU_AF_RAS (0x100)
0017 #define RVU_AF_RAS_W1S (0x108)
0018 #define RVU_AF_RAS_ENA_W1S (0x110)
0019 #define RVU_AF_RAS_ENA_W1C (0x118)
0020 #define RVU_AF_GEN_INT (0x120)
0021 #define RVU_AF_GEN_INT_W1S (0x128)
0022 #define RVU_AF_GEN_INT_ENA_W1S (0x130)
0023 #define RVU_AF_GEN_INT_ENA_W1C (0x138)
0024 #define RVU_AF_AFPF_MBOX0 (0x02000)
0025 #define RVU_AF_AFPF_MBOX1 (0x02008)
0026 #define RVU_AF_AFPFX_MBOXX(a, b) (0x2000 | (a) << 4 | (b) << 3)
0027 #define RVU_AF_PFME_STATUS (0x2800)
0028 #define RVU_AF_PFTRPEND (0x2810)
0029 #define RVU_AF_PFTRPEND_W1S (0x2820)
0030 #define RVU_AF_PF_RST (0x2840)
0031 #define RVU_AF_HWVF_RST (0x2850)
0032 #define RVU_AF_PFAF_MBOX_INT (0x2880)
0033 #define RVU_AF_PFAF_MBOX_INT_W1S (0x2888)
0034 #define RVU_AF_PFAF_MBOX_INT_ENA_W1S (0x2890)
0035 #define RVU_AF_PFAF_MBOX_INT_ENA_W1C (0x2898)
0036 #define RVU_AF_PFFLR_INT (0x28a0)
0037 #define RVU_AF_PFFLR_INT_W1S (0x28a8)
0038 #define RVU_AF_PFFLR_INT_ENA_W1S (0x28b0)
0039 #define RVU_AF_PFFLR_INT_ENA_W1C (0x28b8)
0040 #define RVU_AF_PFME_INT (0x28c0)
0041 #define RVU_AF_PFME_INT_W1S (0x28c8)
0042 #define RVU_AF_PFME_INT_ENA_W1S (0x28d0)
0043 #define RVU_AF_PFME_INT_ENA_W1C (0x28d8)
0044 #define RVU_AF_PFX_BAR4_ADDR(a) (0x5000 | (a) << 4)
0045 #define RVU_AF_PFX_BAR4_CFG (0x5200 | (a) << 4)
0046 #define RVU_AF_PFX_VF_BAR4_ADDR (0x5400 | (a) << 4)
0047 #define RVU_AF_PFX_VF_BAR4_CFG (0x5600 | (a) << 4)
0048 #define RVU_AF_PFX_LMTLINE_ADDR (0x5800 | (a) << 4)
0049 #define RVU_AF_SMMU_ADDR_REQ (0x6000)
0050 #define RVU_AF_SMMU_TXN_REQ (0x6008)
0051 #define RVU_AF_SMMU_ADDR_RSP_STS (0x6010)
0052 #define RVU_AF_SMMU_ADDR_TLN (0x6018)
0053 #define RVU_AF_SMMU_TLN_FLIT0 (0x6020)
0054
0055
0056 #define RVU_PRIV_CONST (0x8000000)
0057 #define RVU_PRIV_GEN_CFG (0x8000010)
0058 #define RVU_PRIV_CLK_CFG (0x8000020)
0059 #define RVU_PRIV_ACTIVE_PC (0x8000030)
0060 #define RVU_PRIV_PFX_CFG(a) (0x8000100 | (a) << 16)
0061 #define RVU_PRIV_PFX_MSIX_CFG(a) (0x8000110 | (a) << 16)
0062 #define RVU_PRIV_PFX_ID_CFG(a) (0x8000120 | (a) << 16)
0063 #define RVU_PRIV_PFX_INT_CFG(a) (0x8000200 | (a) << 16)
0064 #define RVU_PRIV_PFX_NIXX_CFG(a) (0x8000300 | (a) << 3)
0065 #define RVU_PRIV_PFX_NPA_CFG (0x8000310)
0066 #define RVU_PRIV_PFX_SSO_CFG (0x8000320)
0067 #define RVU_PRIV_PFX_SSOW_CFG (0x8000330)
0068 #define RVU_PRIV_PFX_TIM_CFG (0x8000340)
0069 #define RVU_PRIV_PFX_CPTX_CFG(a) (0x8000350 | (a) << 3)
0070 #define RVU_PRIV_BLOCK_TYPEX_REV(a) (0x8000400 | (a) << 3)
0071 #define RVU_PRIV_HWVFX_INT_CFG(a) (0x8001280 | (a) << 16)
0072 #define RVU_PRIV_HWVFX_NIXX_CFG(a) (0x8001300 | (a) << 3)
0073 #define RVU_PRIV_HWVFX_NPA_CFG (0x8001310)
0074 #define RVU_PRIV_HWVFX_SSO_CFG (0x8001320)
0075 #define RVU_PRIV_HWVFX_SSOW_CFG (0x8001330)
0076 #define RVU_PRIV_HWVFX_TIM_CFG (0x8001340)
0077 #define RVU_PRIV_HWVFX_CPTX_CFG(a) (0x8001350 | (a) << 3)
0078
0079
0080 #define RVU_PF_VFX_PFVF_MBOX0 (0x00000)
0081 #define RVU_PF_VFX_PFVF_MBOX1 (0x00008)
0082 #define RVU_PF_VFX_PFVF_MBOXX(a, b) (0x0 | (a) << 12 | (b) << 3)
0083 #define RVU_PF_VF_BAR4_ADDR (0x10)
0084 #define RVU_PF_BLOCK_ADDRX_DISC(a) (0x200 | (a) << 3)
0085 #define RVU_PF_VFME_STATUSX(a) (0x800 | (a) << 3)
0086 #define RVU_PF_VFTRPENDX(a) (0x820 | (a) << 3)
0087 #define RVU_PF_VFTRPEND_W1SX(a) (0x840 | (a) << 3)
0088 #define RVU_PF_VFPF_MBOX_INTX(a) (0x880 | (a) << 3)
0089 #define RVU_PF_VFPF_MBOX_INT_W1SX(a) (0x8A0 | (a) << 3)
0090 #define RVU_PF_VFPF_MBOX_INT_ENA_W1SX(a) (0x8C0 | (a) << 3)
0091 #define RVU_PF_VFPF_MBOX_INT_ENA_W1CX(a) (0x8E0 | (a) << 3)
0092 #define RVU_PF_VFFLR_INTX(a) (0x900 | (a) << 3)
0093 #define RVU_PF_VFFLR_INT_W1SX(a) (0x920 | (a) << 3)
0094 #define RVU_PF_VFFLR_INT_ENA_W1SX(a) (0x940 | (a) << 3)
0095 #define RVU_PF_VFFLR_INT_ENA_W1CX(a) (0x960 | (a) << 3)
0096 #define RVU_PF_VFME_INTX(a) (0x980 | (a) << 3)
0097 #define RVU_PF_VFME_INT_W1SX(a) (0x9A0 | (a) << 3)
0098 #define RVU_PF_VFME_INT_ENA_W1SX(a) (0x9C0 | (a) << 3)
0099 #define RVU_PF_VFME_INT_ENA_W1CX(a) (0x9E0 | (a) << 3)
0100 #define RVU_PF_PFAF_MBOX0 (0xC00)
0101 #define RVU_PF_PFAF_MBOX1 (0xC08)
0102 #define RVU_PF_PFAF_MBOXX(a) (0xC00 | (a) << 3)
0103 #define RVU_PF_INT (0xc20)
0104 #define RVU_PF_INT_W1S (0xc28)
0105 #define RVU_PF_INT_ENA_W1S (0xc30)
0106 #define RVU_PF_INT_ENA_W1C (0xc38)
0107 #define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4)
0108 #define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4)
0109 #define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3)
0110 #define RVU_PF_VF_MBOX_ADDR (0xC40)
0111 #define RVU_PF_LMTLINE_ADDR (0xC48)
0112
0113
0114 #define RVU_VF_VFPF_MBOX0 (0x00000)
0115 #define RVU_VF_VFPF_MBOX1 (0x00008)
0116
0117
0118 #define NPA_AF_BLK_RST (0x0000)
0119 #define NPA_AF_CONST (0x0010)
0120 #define NPA_AF_CONST1 (0x0018)
0121 #define NPA_AF_LF_RST (0x0020)
0122 #define NPA_AF_GEN_CFG (0x0030)
0123 #define NPA_AF_NDC_CFG (0x0040)
0124 #define NPA_AF_INP_CTL (0x00D0)
0125 #define NPA_AF_ACTIVE_CYCLES_PC (0x00F0)
0126 #define NPA_AF_AVG_DELAY (0x0100)
0127 #define NPA_AF_GEN_INT (0x0140)
0128 #define NPA_AF_GEN_INT_W1S (0x0148)
0129 #define NPA_AF_GEN_INT_ENA_W1S (0x0150)
0130 #define NPA_AF_GEN_INT_ENA_W1C (0x0158)
0131 #define NPA_AF_RVU_INT (0x0160)
0132 #define NPA_AF_RVU_INT_W1S (0x0168)
0133 #define NPA_AF_RVU_INT_ENA_W1S (0x0170)
0134 #define NPA_AF_RVU_INT_ENA_W1C (0x0178)
0135 #define NPA_AF_ERR_INT (0x0180)
0136 #define NPA_AF_ERR_INT_W1S (0x0188)
0137 #define NPA_AF_ERR_INT_ENA_W1S (0x0190)
0138 #define NPA_AF_ERR_INT_ENA_W1C (0x0198)
0139 #define NPA_AF_RAS (0x01A0)
0140 #define NPA_AF_RAS_W1S (0x01A8)
0141 #define NPA_AF_RAS_ENA_W1S (0x01B0)
0142 #define NPA_AF_RAS_ENA_W1C (0x01B8)
0143 #define NPA_AF_BP_TEST (0x0200)
0144 #define NPA_AF_ECO (0x0300)
0145 #define NPA_AF_AQ_CFG (0x0600)
0146 #define NPA_AF_AQ_BASE (0x0610)
0147 #define NPA_AF_AQ_STATUS (0x0620)
0148 #define NPA_AF_AQ_DOOR (0x0630)
0149 #define NPA_AF_AQ_DONE_WAIT (0x0640)
0150 #define NPA_AF_AQ_DONE (0x0650)
0151 #define NPA_AF_AQ_DONE_ACK (0x0660)
0152 #define NPA_AF_AQ_DONE_INT (0x0680)
0153 #define NPA_AF_AQ_DONE_INT_W1S (0x0688)
0154 #define NPA_AF_AQ_DONE_ENA_W1S (0x0690)
0155 #define NPA_AF_AQ_DONE_ENA_W1C (0x0698)
0156 #define NPA_AF_BATCH_CTL (0x06a0)
0157 #define NPA_AF_LFX_AURAS_CFG(a) (0x4000 | (a) << 18)
0158 #define NPA_AF_LFX_LOC_AURAS_BASE(a) (0x4010 | (a) << 18)
0159 #define NPA_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 18)
0160 #define NPA_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 18)
0161 #define NPA_PRIV_AF_INT_CFG (0x10000)
0162 #define NPA_PRIV_LFX_CFG (0x10010)
0163 #define NPA_PRIV_LFX_INT_CFG (0x10020)
0164 #define NPA_AF_RVU_LF_CFG_DEBUG (0x10030)
0165
0166
0167 #define NIX_AF_CFG (0x0000)
0168 #define NIX_AF_STATUS (0x0010)
0169 #define NIX_AF_NDC_CFG (0x0018)
0170 #define NIX_AF_CONST (0x0020)
0171 #define NIX_AF_CONST1 (0x0028)
0172 #define NIX_AF_CONST2 (0x0030)
0173 #define NIX_AF_CONST3 (0x0038)
0174 #define NIX_AF_SQ_CONST (0x0040)
0175 #define NIX_AF_CQ_CONST (0x0048)
0176 #define NIX_AF_RQ_CONST (0x0050)
0177 #define NIX_AF_PL_CONST (0x0058)
0178 #define NIX_AF_PSE_CONST (0x0060)
0179 #define NIX_AF_TL1_CONST (0x0070)
0180 #define NIX_AF_TL2_CONST (0x0078)
0181 #define NIX_AF_TL3_CONST (0x0080)
0182 #define NIX_AF_TL4_CONST (0x0088)
0183 #define NIX_AF_MDQ_CONST (0x0090)
0184 #define NIX_AF_MC_MIRROR_CONST (0x0098)
0185 #define NIX_AF_LSO_CFG (0x00A8)
0186 #define NIX_AF_BLK_RST (0x00B0)
0187 #define NIX_AF_TX_TSTMP_CFG (0x00C0)
0188 #define NIX_AF_PL_TS (0x00C8)
0189 #define NIX_AF_RX_CFG (0x00D0)
0190 #define NIX_AF_AVG_DELAY (0x00E0)
0191 #define NIX_AF_CINT_DELAY (0x00F0)
0192 #define NIX_AF_RX_MCAST_BASE (0x0100)
0193 #define NIX_AF_RX_MCAST_CFG (0x0110)
0194 #define NIX_AF_RX_MCAST_BUF_BASE (0x0120)
0195 #define NIX_AF_RX_MCAST_BUF_CFG (0x0130)
0196 #define NIX_AF_RX_MIRROR_BUF_BASE (0x0140)
0197 #define NIX_AF_RX_MIRROR_BUF_CFG (0x0148)
0198 #define NIX_AF_LF_RST (0x0150)
0199 #define NIX_AF_GEN_INT (0x0160)
0200 #define NIX_AF_GEN_INT_W1S (0x0168)
0201 #define NIX_AF_GEN_INT_ENA_W1S (0x0170)
0202 #define NIX_AF_GEN_INT_ENA_W1C (0x0178)
0203 #define NIX_AF_ERR_INT (0x0180)
0204 #define NIX_AF_ERR_INT_W1S (0x0188)
0205 #define NIX_AF_ERR_INT_ENA_W1S (0x0190)
0206 #define NIX_AF_ERR_INT_ENA_W1C (0x0198)
0207 #define NIX_AF_RAS (0x01A0)
0208 #define NIX_AF_RAS_W1S (0x01A8)
0209 #define NIX_AF_RAS_ENA_W1S (0x01B0)
0210 #define NIX_AF_RAS_ENA_W1C (0x01B8)
0211 #define NIX_AF_RVU_INT (0x01C0)
0212 #define NIX_AF_RVU_INT_W1S (0x01C8)
0213 #define NIX_AF_RVU_INT_ENA_W1S (0x01D0)
0214 #define NIX_AF_RVU_INT_ENA_W1C (0x01D8)
0215 #define NIX_AF_TCP_TIMER (0x01E0)
0216 #define NIX_AF_RX_DEF_ET(a) (0x01F0ull | (uint64_t)(a) << 3)
0217 #define NIX_AF_RX_DEF_OL2 (0x0200)
0218 #define NIX_AF_RX_DEF_OIP4 (0x0210)
0219 #define NIX_AF_RX_DEF_IIP4 (0x0220)
0220 #define NIX_AF_RX_DEF_VLAN0_PCP_DEI (0x0228)
0221 #define NIX_AF_RX_DEF_OIP6 (0x0230)
0222 #define NIX_AF_RX_DEF_VLAN1_PCP_DEI (0x0238)
0223 #define NIX_AF_RX_DEF_IIP6 (0x0240)
0224 #define NIX_AF_RX_DEF_OTCP (0x0250)
0225 #define NIX_AF_RX_DEF_ITCP (0x0260)
0226 #define NIX_AF_RX_DEF_OUDP (0x0270)
0227 #define NIX_AF_RX_DEF_IUDP (0x0280)
0228 #define NIX_AF_RX_DEF_OSCTP (0x0290)
0229 #define NIX_AF_RX_DEF_CST_APAD0 (0x0298)
0230 #define NIX_AF_RX_DEF_ISCTP (0x02A0)
0231 #define NIX_AF_RX_DEF_IPSECX (0x02B0)
0232 #define NIX_AF_RX_DEF_CST_APAD1 (0x02A8)
0233 #define NIX_AF_RX_DEF_IIP4_DSCP (0x02E0)
0234 #define NIX_AF_RX_DEF_OIP4_DSCP (0x02E8)
0235 #define NIX_AF_RX_DEF_IIP6_DSCP (0x02F0)
0236 #define NIX_AF_RX_DEF_OIP6_DSCP (0x02F8)
0237 #define NIX_AF_RX_IPSEC_GEN_CFG (0x0300)
0238 #define NIX_AF_RX_CPTX_INST_ADDR (0x0310)
0239 #define NIX_AF_RX_CPTX_INST_QSEL(a) (0x0320ull | (uint64_t)(a) << 3)
0240 #define NIX_AF_RX_CPTX_CREDIT(a) (0x0360ull | (uint64_t)(a) << 3)
0241 #define NIX_AF_NDC_TX_SYNC (0x03F0)
0242 #define NIX_AF_AQ_CFG (0x0400)
0243 #define NIX_AF_AQ_BASE (0x0410)
0244 #define NIX_AF_AQ_STATUS (0x0420)
0245 #define NIX_AF_AQ_DOOR (0x0430)
0246 #define NIX_AF_AQ_DONE_WAIT (0x0440)
0247 #define NIX_AF_AQ_DONE (0x0450)
0248 #define NIX_AF_AQ_DONE_ACK (0x0460)
0249 #define NIX_AF_AQ_DONE_TIMER (0x0470)
0250 #define NIX_AF_AQ_DONE_INT (0x0480)
0251 #define NIX_AF_AQ_DONE_INT_W1S (0x0488)
0252 #define NIX_AF_AQ_DONE_ENA_W1S (0x0490)
0253 #define NIX_AF_AQ_DONE_ENA_W1C (0x0498)
0254 #define NIX_AF_RX_LINKX_SLX_SPKT_CNT (0x0500)
0255 #define NIX_AF_RX_LINKX_SLX_SXQE_CNT (0x0510)
0256 #define NIX_AF_RX_MCAST_JOBSX_SW_CNT (0x0520)
0257 #define NIX_AF_RX_MIRROR_JOBSX_SW_CNT (0x0530)
0258 #define NIX_AF_RX_LINKX_CFG(a) (0x0540 | (a) << 16)
0259 #define NIX_AF_RX_SW_SYNC (0x0550)
0260 #define NIX_AF_RX_SW_SYNC_DONE (0x0560)
0261 #define NIX_AF_SEB_ECO (0x0600)
0262 #define NIX_AF_SEB_TEST_BP (0x0610)
0263 #define NIX_AF_NORM_TX_FIFO_STATUS (0x0620)
0264 #define NIX_AF_EXPR_TX_FIFO_STATUS (0x0630)
0265 #define NIX_AF_SDP_TX_FIFO_STATUS (0x0640)
0266 #define NIX_AF_TX_NPC_CAPTURE_CONFIG (0x0660)
0267 #define NIX_AF_TX_NPC_CAPTURE_INFO (0x0670)
0268 #define NIX_AF_SEB_CFG (0x05F0)
0269
0270 #define NIX_AF_DEBUG_NPC_RESP_DATAX(a) (0x680 | (a) << 3)
0271 #define NIX_AF_SMQX_CFG(a) (0x700 | (a) << 16)
0272 #define NIX_AF_SQM_DBG_CTL_STATUS (0x750)
0273 #define NIX_AF_DWRR_SDP_MTU (0x790)
0274 #define NIX_AF_DWRR_RPM_MTU (0x7A0)
0275 #define NIX_AF_PSE_CHANNEL_LEVEL (0x800)
0276 #define NIX_AF_PSE_SHAPER_CFG (0x810)
0277 #define NIX_AF_TX_EXPR_CREDIT (0x830)
0278 #define NIX_AF_MARK_FORMATX_CTL(a) (0x900 | (a) << 18)
0279 #define NIX_AF_TX_LINKX_NORM_CREDIT(a) (0xA00 | (a) << 16)
0280 #define NIX_AF_TX_LINKX_EXPR_CREDIT(a) (0xA10 | (a) << 16)
0281 #define NIX_AF_TX_LINKX_SW_XOFF(a) (0xA20 | (a) << 16)
0282 #define NIX_AF_TX_LINKX_HW_XOFF(a) (0xA30 | (a) << 16)
0283 #define NIX_AF_SDP_LINK_CREDIT (0xa40)
0284 #define NIX_AF_SDP_SW_XOFFX(a) (0xA60 | (a) << 3)
0285 #define NIX_AF_SDP_HW_XOFFX(a) (0xAC0 | (a) << 3)
0286 #define NIX_AF_TL4X_BP_STATUS(a) (0xB00 | (a) << 16)
0287 #define NIX_AF_TL4X_SDP_LINK_CFG(a) (0xB10 | (a) << 16)
0288 #define NIX_AF_TL1X_SCHEDULE(a) (0xC00 | (a) << 16)
0289 #define NIX_AF_TL1X_SHAPE(a) (0xC10 | (a) << 16)
0290 #define NIX_AF_TL1X_CIR(a) (0xC20 | (a) << 16)
0291 #define NIX_AF_TL1X_SHAPE_STATE(a) (0xC50 | (a) << 16)
0292 #define NIX_AF_TL1X_SW_XOFF(a) (0xC70 | (a) << 16)
0293 #define NIX_AF_TL1X_TOPOLOGY(a) (0xC80 | (a) << 16)
0294 #define NIX_AF_TL1X_GREEN(a) (0xC90 | (a) << 16)
0295 #define NIX_AF_TL1X_YELLOW(a) (0xCA0 | (a) << 16)
0296 #define NIX_AF_TL1X_RED(a) (0xCB0 | (a) << 16)
0297 #define NIX_AF_TL1X_MD_DEBUG0(a) (0xCC0 | (a) << 16)
0298 #define NIX_AF_TL1X_MD_DEBUG1(a) (0xCC8 | (a) << 16)
0299 #define NIX_AF_TL1X_MD_DEBUG2(a) (0xCD0 | (a) << 16)
0300 #define NIX_AF_TL1X_MD_DEBUG3(a) (0xCD8 | (a) << 16)
0301 #define NIX_AF_TL1A_DEBUG (0xce0)
0302 #define NIX_AF_TL1B_DEBUG (0xcf0)
0303 #define NIX_AF_TL1_DEBUG_GREEN (0xd00)
0304 #define NIX_AF_TL1_DEBUG_NODE (0xd10)
0305 #define NIX_AF_TL1X_DROPPED_PACKETS(a) (0xD20 | (a) << 16)
0306 #define NIX_AF_TL1X_DROPPED_BYTES(a) (0xD30 | (a) << 16)
0307 #define NIX_AF_TL1X_RED_PACKETS(a) (0xD40 | (a) << 16)
0308 #define NIX_AF_TL1X_RED_BYTES(a) (0xD50 | (a) << 16)
0309 #define NIX_AF_TL1X_YELLOW_PACKETS(a) (0xD60 | (a) << 16)
0310 #define NIX_AF_TL1X_YELLOW_BYTES(a) (0xD70 | (a) << 16)
0311 #define NIX_AF_TL1X_GREEN_PACKETS(a) (0xD80 | (a) << 16)
0312 #define NIX_AF_TL1X_GREEN_BYTES(a) (0xD90 | (a) << 16)
0313 #define NIX_AF_TL2X_SCHEDULE(a) (0xE00 | (a) << 16)
0314 #define NIX_AF_TL2X_SHAPE(a) (0xE10 | (a) << 16)
0315 #define NIX_AF_TL2X_CIR(a) (0xE20 | (a) << 16)
0316 #define NIX_AF_TL2X_PIR(a) (0xE30 | (a) << 16)
0317 #define NIX_AF_TL2X_SCHED_STATE(a) (0xE40 | (a) << 16)
0318 #define NIX_AF_TL2X_SHAPE_STATE(a) (0xE50 | (a) << 16)
0319 #define NIX_AF_TL2X_POINTERS(a) (0xE60 | (a) << 16)
0320 #define NIX_AF_TL2X_SW_XOFF(a) (0xE70 | (a) << 16)
0321 #define NIX_AF_TL2X_TOPOLOGY(a) (0xE80 | (a) << 16)
0322 #define NIX_AF_TL2X_PARENT(a) (0xE88 | (a) << 16)
0323 #define NIX_AF_TL2X_GREEN(a) (0xE90 | (a) << 16)
0324 #define NIX_AF_TL2X_YELLOW(a) (0xEA0 | (a) << 16)
0325 #define NIX_AF_TL2X_RED(a) (0xEB0 | (a) << 16)
0326 #define NIX_AF_TL2X_MD_DEBUG0(a) (0xEC0 | (a) << 16)
0327 #define NIX_AF_TL2X_MD_DEBUG1(a) (0xEC8 | (a) << 16)
0328 #define NIX_AF_TL2X_MD_DEBUG2(a) (0xED0 | (a) << 16)
0329 #define NIX_AF_TL2X_MD_DEBUG3(a) (0xED8 | (a) << 16)
0330 #define NIX_AF_TL2A_DEBUG (0xee0)
0331 #define NIX_AF_TL2B_DEBUG (0xef0)
0332 #define NIX_AF_TL3X_SCHEDULE(a) (0x1000 | (a) << 16)
0333 #define NIX_AF_TL3X_SHAPE(a) (0x1010 | (a) << 16)
0334 #define NIX_AF_TL3X_CIR(a) (0x1020 | (a) << 16)
0335 #define NIX_AF_TL3X_PIR(a) (0x1030 | (a) << 16)
0336 #define NIX_AF_TL3X_SCHED_STATE(a) (0x1040 | (a) << 16)
0337 #define NIX_AF_TL3X_SHAPE_STATE(a) (0x1050 | (a) << 16)
0338 #define NIX_AF_TL3X_POINTERS(a) (0x1060 | (a) << 16)
0339 #define NIX_AF_TL3X_SW_XOFF(a) (0x1070 | (a) << 16)
0340 #define NIX_AF_TL3X_TOPOLOGY(a) (0x1080 | (a) << 16)
0341 #define NIX_AF_TL3X_PARENT(a) (0x1088 | (a) << 16)
0342 #define NIX_AF_TL3X_GREEN(a) (0x1090 | (a) << 16)
0343 #define NIX_AF_TL3X_YELLOW(a) (0x10A0 | (a) << 16)
0344 #define NIX_AF_TL3X_RED(a) (0x10B0 | (a) << 16)
0345 #define NIX_AF_TL3X_MD_DEBUG0(a) (0x10C0 | (a) << 16)
0346 #define NIX_AF_TL3X_MD_DEBUG1(a) (0x10C8 | (a) << 16)
0347 #define NIX_AF_TL3X_MD_DEBUG2(a) (0x10D0 | (a) << 16)
0348 #define NIX_AF_TL3X_MD_DEBUG3(a) (0x10D8 | (a) << 16)
0349 #define NIX_AF_TL3A_DEBUG (0x10e0)
0350 #define NIX_AF_TL3B_DEBUG (0x10f0)
0351 #define NIX_AF_TL4X_SCHEDULE(a) (0x1200 | (a) << 16)
0352 #define NIX_AF_TL4X_SHAPE(a) (0x1210 | (a) << 16)
0353 #define NIX_AF_TL4X_CIR(a) (0x1220 | (a) << 16)
0354 #define NIX_AF_TL4X_PIR(a) (0x1230 | (a) << 16)
0355 #define NIX_AF_TL4X_SCHED_STATE(a) (0x1240 | (a) << 16)
0356 #define NIX_AF_TL4X_SHAPE_STATE(a) (0x1250 | (a) << 16)
0357 #define NIX_AF_TL4X_POINTERS(a) (0x1260 | (a) << 16)
0358 #define NIX_AF_TL4X_SW_XOFF(a) (0x1270 | (a) << 16)
0359 #define NIX_AF_TL4X_TOPOLOGY(a) (0x1280 | (a) << 16)
0360 #define NIX_AF_TL4X_PARENT(a) (0x1288 | (a) << 16)
0361 #define NIX_AF_TL4X_GREEN(a) (0x1290 | (a) << 16)
0362 #define NIX_AF_TL4X_YELLOW(a) (0x12A0 | (a) << 16)
0363 #define NIX_AF_TL4X_RED(a) (0x12B0 | (a) << 16)
0364 #define NIX_AF_TL4X_MD_DEBUG0(a) (0x12C0 | (a) << 16)
0365 #define NIX_AF_TL4X_MD_DEBUG1(a) (0x12C8 | (a) << 16)
0366 #define NIX_AF_TL4X_MD_DEBUG2(a) (0x12D0 | (a) << 16)
0367 #define NIX_AF_TL4X_MD_DEBUG3(a) (0x12D8 | (a) << 16)
0368 #define NIX_AF_TL4A_DEBUG (0x12e0)
0369 #define NIX_AF_TL4B_DEBUG (0x12f0)
0370 #define NIX_AF_MDQX_SCHEDULE(a) (0x1400 | (a) << 16)
0371 #define NIX_AF_MDQX_SHAPE(a) (0x1410 | (a) << 16)
0372 #define NIX_AF_MDQX_CIR(a) (0x1420 | (a) << 16)
0373 #define NIX_AF_MDQX_PIR(a) (0x1430 | (a) << 16)
0374 #define NIX_AF_MDQX_SCHED_STATE(a) (0x1440 | (a) << 16)
0375 #define NIX_AF_MDQX_SHAPE_STATE(a) (0x1450 | (a) << 16)
0376 #define NIX_AF_MDQX_POINTERS(a) (0x1460 | (a) << 16)
0377 #define NIX_AF_MDQX_SW_XOFF(a) (0x1470 | (a) << 16)
0378 #define NIX_AF_MDQX_PARENT(a) (0x1480 | (a) << 16)
0379 #define NIX_AF_MDQX_MD_DEBUG(a) (0x14C0 | (a) << 16)
0380 #define NIX_AF_MDQX_PTR_FIFO(a) (0x14D0 | (a) << 16)
0381 #define NIX_AF_MDQA_DEBUG (0x14e0)
0382 #define NIX_AF_MDQB_DEBUG (0x14f0)
0383 #define NIX_AF_TL3_TL2X_CFG(a) (0x1600 | (a) << 18)
0384 #define NIX_AF_TL3_TL2X_BP_STATUS(a) (0x1610 | (a) << 16)
0385 #define NIX_AF_TL3_TL2X_LINKX_CFG(a, b) (0x1700 | (a) << 16 | (b) << 3)
0386 #define NIX_AF_RX_FLOW_KEY_ALGX_FIELDX(a, b) (0x1800 | (a) << 18 | (b) << 3)
0387 #define NIX_AF_TX_MCASTX(a) (0x1900 | (a) << 15)
0388 #define NIX_AF_TX_VTAG_DEFX_CTL(a) (0x1A00 | (a) << 16)
0389 #define NIX_AF_TX_VTAG_DEFX_DATA(a) (0x1A10 | (a) << 16)
0390 #define NIX_AF_RX_BPIDX_STATUS(a) (0x1A20 | (a) << 17)
0391 #define NIX_AF_RX_CHANX_CFG(a) (0x1A30 | (a) << 15)
0392 #define NIX_AF_CINT_TIMERX(a) (0x1A40 | (a) << 18)
0393 #define NIX_AF_LSO_FORMATX_FIELDX(a, b) (0x1B00 | (a) << 16 | (b) << 3)
0394 #define NIX_AF_LFX_CFG(a) (0x4000 | (a) << 17)
0395 #define NIX_AF_LFX_SQS_CFG(a) (0x4020 | (a) << 17)
0396 #define NIX_AF_LFX_TX_CFG2(a) (0x4028 | (a) << 17)
0397 #define NIX_AF_LFX_SQS_BASE(a) (0x4030 | (a) << 17)
0398 #define NIX_AF_LFX_RQS_CFG(a) (0x4040 | (a) << 17)
0399 #define NIX_AF_LFX_RQS_BASE(a) (0x4050 | (a) << 17)
0400 #define NIX_AF_LFX_CQS_CFG(a) (0x4060 | (a) << 17)
0401 #define NIX_AF_LFX_CQS_BASE(a) (0x4070 | (a) << 17)
0402 #define NIX_AF_LFX_TX_CFG(a) (0x4080 | (a) << 17)
0403 #define NIX_AF_LFX_TX_PARSE_CFG(a) (0x4090 | (a) << 17)
0404 #define NIX_AF_LFX_RX_CFG(a) (0x40A0 | (a) << 17)
0405 #define NIX_AF_LFX_RSS_CFG(a) (0x40C0 | (a) << 17)
0406 #define NIX_AF_LFX_RSS_BASE(a) (0x40D0 | (a) << 17)
0407 #define NIX_AF_LFX_QINTS_CFG(a) (0x4100 | (a) << 17)
0408 #define NIX_AF_LFX_QINTS_BASE(a) (0x4110 | (a) << 17)
0409 #define NIX_AF_LFX_CINTS_CFG(a) (0x4120 | (a) << 17)
0410 #define NIX_AF_LFX_CINTS_BASE(a) (0x4130 | (a) << 17)
0411 #define NIX_AF_LFX_RX_IPSEC_CFG0(a) (0x4140 | (a) << 17)
0412 #define NIX_AF_LFX_RX_IPSEC_CFG1(a) (0x4148 | (a) << 17)
0413 #define NIX_AF_LFX_RX_IPSEC_DYNO_CFG(a) (0x4150 | (a) << 17)
0414 #define NIX_AF_LFX_RX_IPSEC_DYNO_BASE(a) (0x4158 | (a) << 17)
0415 #define NIX_AF_LFX_RX_IPSEC_SA_BASE(a) (0x4170 | (a) << 17)
0416 #define NIX_AF_LFX_TX_STATUS(a) (0x4180 | (a) << 17)
0417 #define NIX_AF_LFX_RX_VTAG_TYPEX(a, b) (0x4200 | (a) << 17 | (b) << 3)
0418 #define NIX_AF_LFX_LOCKX(a, b) (0x4300 | (a) << 17 | (b) << 3)
0419 #define NIX_AF_LFX_TX_STATX(a, b) (0x4400 | (a) << 17 | (b) << 3)
0420 #define NIX_AF_LFX_RX_STATX(a, b) (0x4500 | (a) << 17 | (b) << 3)
0421 #define NIX_AF_LFX_RSS_GRPX(a, b) (0x4600 | (a) << 17 | (b) << 3)
0422 #define NIX_AF_RX_NPC_MC_RCV (0x4700)
0423 #define NIX_AF_RX_NPC_MC_DROP (0x4710)
0424 #define NIX_AF_RX_NPC_MIRROR_RCV (0x4720)
0425 #define NIX_AF_RX_NPC_MIRROR_DROP (0x4730)
0426 #define NIX_AF_RX_ACTIVE_CYCLES_PCX(a) (0x4800 | (a) << 16)
0427 #define NIX_AF_LINKX_CFG(a) (0x4010 | (a) << 17)
0428
0429 #define NIX_PRIV_AF_INT_CFG (0x8000000)
0430 #define NIX_PRIV_LFX_CFG (0x8000010)
0431 #define NIX_PRIV_LFX_INT_CFG (0x8000020)
0432 #define NIX_AF_RVU_LF_CFG_DEBUG (0x8000030)
0433
0434 #define NIX_AF_LINKX_BASE_MASK GENMASK_ULL(11, 0)
0435 #define NIX_AF_LINKX_RANGE_MASK GENMASK_ULL(19, 16)
0436
0437
0438 #define SSO_AF_CONST (0x1000)
0439 #define SSO_AF_CONST1 (0x1008)
0440 #define SSO_AF_BLK_RST (0x10f8)
0441 #define SSO_AF_LF_HWGRP_RST (0x10e0)
0442 #define SSO_AF_RVU_LF_CFG_DEBUG (0x3800)
0443 #define SSO_PRIV_LFX_HWGRP_CFG (0x10000)
0444 #define SSO_PRIV_LFX_HWGRP_INT_CFG (0x20000)
0445
0446
0447 #define SSOW_AF_RVU_LF_HWS_CFG_DEBUG (0x0010)
0448 #define SSOW_AF_LF_HWS_RST (0x0030)
0449 #define SSOW_PRIV_LFX_HWS_CFG (0x1000)
0450 #define SSOW_PRIV_LFX_HWS_INT_CFG (0x2000)
0451
0452
0453 #define TIM_AF_CONST (0x90)
0454 #define TIM_PRIV_LFX_CFG (0x20000)
0455 #define TIM_PRIV_LFX_INT_CFG (0x24000)
0456 #define TIM_AF_RVU_LF_CFG_DEBUG (0x30000)
0457 #define TIM_AF_BLK_RST (0x10)
0458 #define TIM_AF_LF_RST (0x20)
0459
0460
0461 #define CPT_AF_CONSTANTS0 (0x0000)
0462 #define CPT_AF_CONSTANTS1 (0x1000)
0463 #define CPT_AF_DIAG (0x3000)
0464 #define CPT_AF_ECO (0x4000)
0465 #define CPT_AF_FLTX_INT(a) (0xa000ull | (u64)(a) << 3)
0466 #define CPT_AF_FLTX_INT_W1S(a) (0xb000ull | (u64)(a) << 3)
0467 #define CPT_AF_FLTX_INT_ENA_W1C(a) (0xc000ull | (u64)(a) << 3)
0468 #define CPT_AF_FLTX_INT_ENA_W1S(a) (0xd000ull | (u64)(a) << 3)
0469 #define CPT_AF_PSNX_EXE(a) (0xe000ull | (u64)(a) << 3)
0470 #define CPT_AF_PSNX_EXE_W1S(a) (0xf000ull | (u64)(a) << 3)
0471 #define CPT_AF_PSNX_LF(a) (0x10000ull | (u64)(a) << 3)
0472 #define CPT_AF_PSNX_LF_W1S(a) (0x11000ull | (u64)(a) << 3)
0473 #define CPT_AF_EXEX_CTL2(a) (0x12000ull | (u64)(a) << 3)
0474 #define CPT_AF_EXEX_STS(a) (0x13000ull | (u64)(a) << 3)
0475 #define CPT_AF_EXE_ERR_INFO (0x14000)
0476 #define CPT_AF_EXEX_ACTIVE(a) (0x16000ull | (u64)(a) << 3)
0477 #define CPT_AF_INST_REQ_PC (0x17000)
0478 #define CPT_AF_INST_LATENCY_PC (0x18000)
0479 #define CPT_AF_RD_REQ_PC (0x19000)
0480 #define CPT_AF_RD_LATENCY_PC (0x1a000)
0481 #define CPT_AF_RD_UC_PC (0x1b000)
0482 #define CPT_AF_ACTIVE_CYCLES_PC (0x1c000)
0483 #define CPT_AF_EXE_DBG_CTL (0x1d000)
0484 #define CPT_AF_EXE_DBG_DATA (0x1e000)
0485 #define CPT_AF_EXE_REQ_TIMER (0x1f000)
0486 #define CPT_AF_EXEX_CTL(a) (0x20000ull | (u64)(a) << 3)
0487 #define CPT_AF_EXE_PERF_CTL (0x21000)
0488 #define CPT_AF_EXE_DBG_CNTX(a) (0x22000ull | (u64)(a) << 3)
0489 #define CPT_AF_EXE_PERF_EVENT_CNT (0x23000)
0490 #define CPT_AF_EXE_EPCI_INBX_CNT(a) (0x24000ull | (u64)(a) << 3)
0491 #define CPT_AF_EXE_EPCI_OUTBX_CNT(a) (0x25000ull | (u64)(a) << 3)
0492 #define CPT_AF_EXEX_UCODE_BASE(a) (0x26000ull | (u64)(a) << 3)
0493 #define CPT_AF_LFX_CTL(a) (0x27000ull | (u64)(a) << 3)
0494 #define CPT_AF_LFX_CTL2(a) (0x29000ull | (u64)(a) << 3)
0495 #define CPT_AF_CPTCLK_CNT (0x2a000)
0496 #define CPT_AF_PF_FUNC (0x2b000)
0497 #define CPT_AF_LFX_PTR_CTL(a) (0x2c000ull | (u64)(a) << 3)
0498 #define CPT_AF_GRPX_THR(a) (0x2d000ull | (u64)(a) << 3)
0499 #define CPT_AF_CTL (0x2e000ull)
0500 #define CPT_AF_XEX_THR(a) (0x2f000ull | (u64)(a) << 3)
0501 #define CPT_PRIV_LFX_CFG (0x41000)
0502 #define CPT_PRIV_AF_INT_CFG (0x42000)
0503 #define CPT_PRIV_LFX_INT_CFG (0x43000)
0504 #define CPT_AF_LF_RST (0x44000)
0505 #define CPT_AF_RVU_LF_CFG_DEBUG (0x45000)
0506 #define CPT_AF_BLK_RST (0x46000)
0507 #define CPT_AF_RVU_INT (0x47000)
0508 #define CPT_AF_RVU_INT_W1S (0x47008)
0509 #define CPT_AF_RVU_INT_ENA_W1S (0x47010)
0510 #define CPT_AF_RVU_INT_ENA_W1C (0x47018)
0511 #define CPT_AF_RAS_INT (0x47020)
0512 #define CPT_AF_RAS_INT_W1S (0x47028)
0513 #define CPT_AF_RAS_INT_ENA_W1S (0x47030)
0514 #define CPT_AF_RAS_INT_ENA_W1C (0x47038)
0515 #define CPT_AF_CTX_FLUSH_TIMER (0x48000ull)
0516 #define CPT_AF_CTX_ERR (0x48008ull)
0517 #define CPT_AF_CTX_ENC_ID (0x48010ull)
0518 #define CPT_AF_CTX_MIS_PC (0x49400ull)
0519 #define CPT_AF_CTX_HIT_PC (0x49408ull)
0520 #define CPT_AF_CTX_AOP_PC (0x49410ull)
0521 #define CPT_AF_CTX_AOP_LATENCY_PC (0x49418ull)
0522 #define CPT_AF_CTX_IFETCH_PC (0x49420ull)
0523 #define CPT_AF_CTX_IFETCH_LATENCY_PC (0x49428ull)
0524 #define CPT_AF_CTX_FFETCH_PC (0x49430ull)
0525 #define CPT_AF_CTX_FFETCH_LATENCY_PC (0x49438ull)
0526 #define CPT_AF_CTX_WBACK_PC (0x49440ull)
0527 #define CPT_AF_CTX_WBACK_LATENCY_PC (0x49448ull)
0528 #define CPT_AF_CTX_PSH_PC (0x49450ull)
0529 #define CPT_AF_CTX_PSH_LATENCY_PC (0x49458ull)
0530 #define CPT_AF_CTX_CAM_DATA(a) (0x49800ull | (u64)(a) << 3)
0531 #define CPT_AF_RXC_TIME (0x50010ull)
0532 #define CPT_AF_RXC_TIME_CFG (0x50018ull)
0533 #define CPT_AF_RXC_DFRG (0x50020ull)
0534 #define CPT_AF_RXC_ACTIVE_STS (0x50028ull)
0535 #define CPT_AF_RXC_ZOMBIE_STS (0x50030ull)
0536 #define CPT_AF_X2PX_LINK_CFG(a) (0x51000ull | (u64)(a) << 3)
0537
0538 #define AF_BAR2_ALIASX(a, b) (0x9100000ull | (a) << 12 | (b))
0539 #define CPT_AF_BAR2_SEL 0x9000000
0540 #define CPT_AF_BAR2_ALIASX(a, b) AF_BAR2_ALIASX(a, b)
0541
0542 #define CPT_AF_LF_CTL2_SHIFT 3
0543 #define CPT_AF_LF_SSO_PF_FUNC_SHIFT 32
0544
0545 #define CPT_LF_CTL 0x10
0546 #define CPT_LF_INPROG 0x40
0547 #define CPT_LF_Q_GRP_PTR 0x120
0548 #define CPT_LF_CTX_FLUSH 0x510
0549
0550 #define NPC_AF_BLK_RST (0x00040)
0551
0552
0553 #define NPC_AF_CFG (0x00000)
0554 #define NPC_AF_ACTIVE_PC (0x00010)
0555 #define NPC_AF_CONST (0x00020)
0556 #define NPC_AF_CONST1 (0x00030)
0557 #define NPC_AF_BLK_RST (0x00040)
0558 #define NPC_AF_MCAM_SCRUB_CTL (0x000a0)
0559 #define NPC_AF_KCAM_SCRUB_CTL (0x000b0)
0560 #define NPC_AF_CONST2 (0x00100)
0561 #define NPC_AF_CONST3 (0x00110)
0562 #define NPC_AF_KPUX_CFG(a) (0x00500 | (a) << 3)
0563 #define NPC_AF_PCK_CFG (0x00600)
0564 #define NPC_AF_PCK_DEF_OL2 (0x00610)
0565 #define NPC_AF_PCK_DEF_OIP4 (0x00620)
0566 #define NPC_AF_PCK_DEF_OIP6 (0x00630)
0567 #define NPC_AF_PCK_DEF_IIP4 (0x00640)
0568 #define NPC_AF_INTFX_HASHX_RESULT_CTRL(a, b) (0x006c0 | (a) << 4 | (b) << 3)
0569 #define NPC_AF_INTFX_HASHX_MASKX(a, b, c) (0x00700 | (a) << 5 | (b) << 4 | (c) << 3)
0570 #define NPC_AF_KEX_LDATAX_FLAGS_CFG(a) (0x00800 | (a) << 3)
0571 #define NPC_AF_INTFX_HASHX_CFG(a, b) (0x00b00 | (a) << 6 | (b) << 4)
0572 #define NPC_AF_INTFX_SECRET_KEY0(a) (0x00e00 | (a) << 3)
0573 #define NPC_AF_INTFX_SECRET_KEY1(a) (0x00e20 | (a) << 3)
0574 #define NPC_AF_INTFX_SECRET_KEY2(a) (0x00e40 | (a) << 3)
0575 #define NPC_AF_INTFX_KEX_CFG(a) (0x01010 | (a) << 8)
0576 #define NPC_AF_PKINDX_ACTION0(a) (0x80000ull | (a) << 6)
0577 #define NPC_AF_PKINDX_ACTION1(a) (0x80008ull | (a) << 6)
0578 #define NPC_AF_PKINDX_CPI_DEFX(a, b) (0x80020ull | (a) << 6 | (b) << 3)
0579 #define NPC_AF_KPUX_ENTRYX_CAMX(a, b, c) \
0580 (0x100000 | (a) << 14 | (b) << 6 | (c) << 3)
0581 #define NPC_AF_KPUX_ENTRYX_ACTION0(a, b) \
0582 (0x100020 | (a) << 14 | (b) << 6)
0583 #define NPC_AF_KPUX_ENTRYX_ACTION1(a, b) \
0584 (0x100028 | (a) << 14 | (b) << 6)
0585 #define NPC_AF_KPUX_ENTRY_DISX(a, b) (0x180000 | (a) << 6 | (b) << 3)
0586 #define NPC_AF_CPIX_CFG(a) (0x200000 | (a) << 3)
0587 #define NPC_AF_INTFX_LIDX_LTX_LDX_CFG(a, b, c, d) \
0588 (0x900000 | (a) << 16 | (b) << 12 | (c) << 5 | (d) << 3)
0589 #define NPC_AF_INTFX_LDATAX_FLAGSX_CFG(a, b, c) \
0590 (0x980000 | (a) << 16 | (b) << 12 | (c) << 3)
0591 #define NPC_AF_INTFX_MISS_STAT_ACT(a) (0x1880040 + (a) * 0x8)
0592 #define NPC_AF_INTFX_MISS_ACT(a) (0x1a00000 | (a) << 4)
0593 #define NPC_AF_INTFX_MISS_TAG_ACT(a) (0x1b00008 | (a) << 4)
0594 #define NPC_AF_MCAM_BANKX_HITX(a, b) (0x1c80000 | (a) << 8 | (b) << 4)
0595 #define NPC_AF_LKUP_CTL (0x2000000)
0596 #define NPC_AF_LKUP_DATAX(a) (0x2000200 | (a) << 4)
0597 #define NPC_AF_LKUP_RESULTX(a) (0x2000400 | (a) << 4)
0598 #define NPC_AF_INTFX_STAT(a) (0x2000800 | (a) << 4)
0599 #define NPC_AF_DBG_CTL (0x3000000)
0600 #define NPC_AF_DBG_STATUS (0x3000010)
0601 #define NPC_AF_KPUX_DBG(a) (0x3000020 | (a) << 8)
0602 #define NPC_AF_IKPU_ERR_CTL (0x3000080)
0603 #define NPC_AF_KPUX_ERR_CTL(a) (0x30000a0 | (a) << 8)
0604 #define NPC_AF_MCAM_DBG (0x3001000)
0605 #define NPC_AF_DBG_DATAX(a) (0x3001400 | (a) << 4)
0606 #define NPC_AF_DBG_RESULTX(a) (0x3001800 | (a) << 4)
0607
0608 #define NPC_AF_EXACT_MEM_ENTRY(a, b) (0x300000 | (a) << 15 | (b) << 3)
0609 #define NPC_AF_EXACT_CAM_ENTRY(a) (0xC00 | (a) << 3)
0610 #define NPC_AF_INTFX_EXACT_MASK(a) (0x660 | (a) << 3)
0611 #define NPC_AF_INTFX_EXACT_RESULT_CTL(a)(0x680 | (a) << 3)
0612 #define NPC_AF_INTFX_EXACT_CFG(a) (0xA00 | (a) << 3)
0613 #define NPC_AF_INTFX_EXACT_SECRET0(a) (0xE00 | (a) << 3)
0614 #define NPC_AF_INTFX_EXACT_SECRET1(a) (0xE20 | (a) << 3)
0615 #define NPC_AF_INTFX_EXACT_SECRET2(a) (0xE40 | (a) << 3)
0616
0617 #define NPC_AF_MCAMEX_BANKX_CAMX_INTF(a, b, c) ({ \
0618 u64 offset; \
0619 \
0620 offset = (0x1000000ull | (a) << 10 | (b) << 6 | (c) << 3); \
0621 if (rvu->hw->npc_ext_set) \
0622 offset = (0x8000000ull | (a) << 8 | (b) << 22 | (c) << 3); \
0623 offset; })
0624
0625 #define NPC_AF_MCAMEX_BANKX_CAMX_W0(a, b, c) ({ \
0626 u64 offset; \
0627 \
0628 offset = (0x1000010ull | (a) << 10 | (b) << 6 | (c) << 3); \
0629 if (rvu->hw->npc_ext_set) \
0630 offset = (0x8000010ull | (a) << 8 | (b) << 22 | (c) << 3); \
0631 offset; })
0632
0633 #define NPC_AF_MCAMEX_BANKX_CAMX_W1(a, b, c) ({ \
0634 u64 offset; \
0635 \
0636 offset = (0x1000020ull | (a) << 10 | (b) << 6 | (c) << 3); \
0637 if (rvu->hw->npc_ext_set) \
0638 offset = (0x8000020ull | (a) << 8 | (b) << 22 | (c) << 3); \
0639 offset; })
0640
0641 #define NPC_AF_MCAMEX_BANKX_CFG(a, b) ({ \
0642 u64 offset; \
0643 \
0644 offset = (0x1800000ull | (a) << 8 | (b) << 4); \
0645 if (rvu->hw->npc_ext_set) \
0646 offset = (0x8000038ull | (a) << 8 | (b) << 22); \
0647 offset; })
0648
0649 #define NPC_AF_MCAMEX_BANKX_ACTION(a, b) ({ \
0650 u64 offset; \
0651 \
0652 offset = (0x1900000ull | (a) << 8 | (b) << 4); \
0653 if (rvu->hw->npc_ext_set) \
0654 offset = (0x8000040ull | (a) << 8 | (b) << 22); \
0655 offset; }) \
0656
0657 #define NPC_AF_MCAMEX_BANKX_TAG_ACT(a, b) ({ \
0658 u64 offset; \
0659 \
0660 offset = (0x1900008ull | (a) << 8 | (b) << 4); \
0661 if (rvu->hw->npc_ext_set) \
0662 offset = (0x8000048ull | (a) << 8 | (b) << 22); \
0663 offset; }) \
0664
0665 #define NPC_AF_MCAMEX_BANKX_STAT_ACT(a, b) ({ \
0666 u64 offset; \
0667 \
0668 offset = (0x1880000ull | (a) << 8 | (b) << 4); \
0669 if (rvu->hw->npc_ext_set) \
0670 offset = (0x8000050ull | (a) << 8 | (b) << 22); \
0671 offset; }) \
0672
0673 #define NPC_AF_MATCH_STATX(a) ({ \
0674 u64 offset; \
0675 \
0676 offset = (0x1880008ull | (a) << 8); \
0677 if (rvu->hw->npc_ext_set) \
0678 offset = (0x8000078ull | (a) << 8); \
0679 offset; }) \
0680
0681
0682 #define NDC_AF_CONST (0x00000)
0683 #define NDC_AF_CLK_EN (0x00020)
0684 #define NDC_AF_CTL (0x00030)
0685 #define NDC_AF_BANK_CTL (0x00040)
0686 #define NDC_AF_BANK_CTL_DONE (0x00048)
0687 #define NDC_AF_INTR (0x00058)
0688 #define NDC_AF_INTR_W1S (0x00060)
0689 #define NDC_AF_INTR_ENA_W1S (0x00068)
0690 #define NDC_AF_INTR_ENA_W1C (0x00070)
0691 #define NDC_AF_ACTIVE_PC (0x00078)
0692 #define NDC_AF_BP_TEST_ENABLE (0x001F8)
0693 #define NDC_AF_BP_TEST(a) (0x00200 | (a) << 3)
0694 #define NDC_AF_BLK_RST (0x002F0)
0695 #define NDC_PRIV_AF_INT_CFG (0x002F8)
0696 #define NDC_AF_HASHX(a) (0x00300 | (a) << 3)
0697 #define NDC_AF_PORTX_RTX_RWX_REQ_PC(a, b, c) \
0698 (0x00C00 | (a) << 5 | (b) << 4 | (c) << 3)
0699 #define NDC_AF_PORTX_RTX_RWX_OSTDN_PC(a, b, c) \
0700 (0x00D00 | (a) << 5 | (b) << 4 | (c) << 3)
0701 #define NDC_AF_PORTX_RTX_RWX_LAT_PC(a, b, c) \
0702 (0x00E00 | (a) << 5 | (b) << 4 | (c) << 3)
0703 #define NDC_AF_PORTX_RTX_CANT_ALLOC_PC(a, b) \
0704 (0x00F00 | (a) << 5 | (b) << 4)
0705 #define NDC_AF_BANKX_HIT_PC(a) (0x01000 | (a) << 3)
0706 #define NDC_AF_BANKX_MISS_PC(a) (0x01100 | (a) << 3)
0707
0708
0709 #define LBK_CONST (0x10ull)
0710 #define LBK_LINK_CFG_P2X (0x400ull)
0711 #define LBK_LINK_CFG_X2P (0x408ull)
0712 #define LBK_CONST_CHANS GENMASK_ULL(47, 32)
0713 #define LBK_CONST_DST GENMASK_ULL(31, 28)
0714 #define LBK_CONST_SRC GENMASK_ULL(27, 24)
0715 #define LBK_CONST_BUF_SIZE GENMASK_ULL(23, 0)
0716 #define LBK_LINK_CFG_RANGE_MASK GENMASK_ULL(19, 16)
0717 #define LBK_LINK_CFG_ID_MASK GENMASK_ULL(11, 6)
0718 #define LBK_LINK_CFG_BASE_MASK GENMASK_ULL(5, 0)
0719
0720
0721 #define APR_AF_LMT_CFG (0x000ull)
0722 #define APR_AF_LMT_MAP_BASE (0x008ull)
0723 #define APR_AF_LMT_CTL (0x010ull)
0724 #define APR_LMT_MAP_ENT_DIS_SCH_CMP_SHIFT 23
0725 #define APR_LMT_MAP_ENT_SCH_ENA_SHIFT 22
0726 #define APR_LMT_MAP_ENT_DIS_LINE_PREF_SHIFT 21
0727
0728 #endif
