octeontx2/af/rvu_reg.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Marvell RVU Admin Function driver
0003  *
0004  * Copyright (C) 2018 Marvell.
0005  *
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/pci.h>
0010
0011 #include "rvu_struct.h"
0012 #include "common.h"
0013 #include "mbox.h"
0014 #include "rvu.h"
0015
0016 struct reg_range {
0017     u64  start;
0018     u64  end;
0019 };
0020
0021 struct hw_reg_map {
0022     u8  regblk;
0023     u8  num_ranges;
0024     u64 mask;
0025 #define  MAX_REG_RANGES 8
0026     struct reg_range range[MAX_REG_RANGES];
0027 };
0028
0029 static struct hw_reg_map txsch_reg_map[NIX_TXSCH_LVL_CNT] = {
0030     {NIX_TXSCH_LVL_SMQ, 2, 0xFFFF, {{0x0700, 0x0708}, {0x1400, 0x14C8} } },
0031     {NIX_TXSCH_LVL_TL4, 3, 0xFFFF, {{0x0B00, 0x0B08}, {0x0B10, 0x0B18},
0032                   {0x1200, 0x12E0} } },
0033     {NIX_TXSCH_LVL_TL3, 4, 0xFFFF, {{0x1000, 0x10E0}, {0x1600, 0x1608},
0034                   {0x1610, 0x1618}, {0x1700, 0x17B0} } },
0035     {NIX_TXSCH_LVL_TL2, 2, 0xFFFF, {{0x0E00, 0x0EE0}, {0x1700, 0x17B0} } },
0036     {NIX_TXSCH_LVL_TL1, 1, 0xFFFF, {{0x0C00, 0x0D98} } },
0037 };
0038
0039 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg)
0040 {
0041     int idx;
0042     struct hw_reg_map *map;
0043
0044     /* Only 64bit offsets */
0045     if (reg & 0x07)
0046         return false;
0047
0048     if (regmap == TXSCHQ_HWREGMAP) {
0049         if (regblk >= NIX_TXSCH_LVL_CNT)
0050             return false;
0051         map = &txsch_reg_map[regblk];
0052     } else {
0053         return false;
0054     }
0055
0056     /* Should never happen */
0057     if (map->regblk != regblk)
0058         return false;
0059
0060     reg &= map->mask;
0061
0062     for (idx = 0; idx < map->num_ranges; idx++) {
0063         if (reg >= map->range[idx].start &&
0064             reg < map->range[idx].end)
0065             return true;
0066     }
0067     return false;
0068 }