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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /* Marvell RVU Admin Function driver
0003  *
0004  * Copyright (C) 2020 Marvell.
0005  *
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/pci.h>
0010 #include "rvu_struct.h"
0011 #include "rvu_reg.h"
0012 #include "mbox.h"
0013 #include "rvu.h"
0014 
0015 /* CPT PF device id */
0016 #define PCI_DEVID_OTX2_CPT_PF   0xA0FD
0017 #define PCI_DEVID_OTX2_CPT10K_PF 0xA0F2
0018 
0019 /* Length of initial context fetch in 128 byte words */
0020 #define CPT_CTX_ILEN    2ULL
0021 
0022 #define cpt_get_eng_sts(e_min, e_max, rsp, etype)                   \
0023 ({                                                                  \
0024     u64 free_sts = 0, busy_sts = 0;                             \
0025     typeof(rsp) _rsp = rsp;                                     \
0026     u32 e, i;                                                   \
0027                                     \
0028     for (e = (e_min), i = 0; e < (e_max); e++, i++) {           \
0029         reg = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(e)); \
0030         if (reg & 0x1)                                      \
0031             busy_sts |= 1ULL << i;                      \
0032                                     \
0033         if (reg & 0x2)                                      \
0034             free_sts |= 1ULL << i;                      \
0035     }                                                           \
0036     (_rsp)->busy_sts_##etype = busy_sts;                        \
0037     (_rsp)->free_sts_##etype = free_sts;                        \
0038 })
0039 
0040 static irqreturn_t rvu_cpt_af_flt_intr_handler(int irq, void *ptr)
0041 {
0042     struct rvu_block *block = ptr;
0043     struct rvu *rvu = block->rvu;
0044     int blkaddr = block->addr;
0045     u64 reg0, reg1, reg2;
0046 
0047     reg0 = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(0));
0048     reg1 = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(1));
0049     if (!is_rvu_otx2(rvu)) {
0050         reg2 = rvu_read64(rvu, blkaddr, CPT_AF_FLTX_INT(2));
0051         dev_err_ratelimited(rvu->dev,
0052                     "Received CPTAF FLT irq : 0x%llx, 0x%llx, 0x%llx",
0053                      reg0, reg1, reg2);
0054     } else {
0055         dev_err_ratelimited(rvu->dev,
0056                     "Received CPTAF FLT irq : 0x%llx, 0x%llx",
0057                      reg0, reg1);
0058     }
0059 
0060     rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT(0), reg0);
0061     rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT(1), reg1);
0062     if (!is_rvu_otx2(rvu))
0063         rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT(2), reg2);
0064 
0065     return IRQ_HANDLED;
0066 }
0067 
0068 static irqreturn_t rvu_cpt_af_rvu_intr_handler(int irq, void *ptr)
0069 {
0070     struct rvu_block *block = ptr;
0071     struct rvu *rvu = block->rvu;
0072     int blkaddr = block->addr;
0073     u64 reg;
0074 
0075     reg = rvu_read64(rvu, blkaddr, CPT_AF_RVU_INT);
0076     dev_err_ratelimited(rvu->dev, "Received CPTAF RVU irq : 0x%llx", reg);
0077 
0078     rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT, reg);
0079     return IRQ_HANDLED;
0080 }
0081 
0082 static irqreturn_t rvu_cpt_af_ras_intr_handler(int irq, void *ptr)
0083 {
0084     struct rvu_block *block = ptr;
0085     struct rvu *rvu = block->rvu;
0086     int blkaddr = block->addr;
0087     u64 reg;
0088 
0089     reg = rvu_read64(rvu, blkaddr, CPT_AF_RAS_INT);
0090     dev_err_ratelimited(rvu->dev, "Received CPTAF RAS irq : 0x%llx", reg);
0091 
0092     rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT, reg);
0093     return IRQ_HANDLED;
0094 }
0095 
0096 static int rvu_cpt_do_register_interrupt(struct rvu_block *block, int irq_offs,
0097                      irq_handler_t handler,
0098                      const char *name)
0099 {
0100     struct rvu *rvu = block->rvu;
0101     int ret;
0102 
0103     ret = request_irq(pci_irq_vector(rvu->pdev, irq_offs), handler, 0,
0104               name, block);
0105     if (ret) {
0106         dev_err(rvu->dev, "RVUAF: %s irq registration failed", name);
0107         return ret;
0108     }
0109 
0110     WARN_ON(rvu->irq_allocated[irq_offs]);
0111     rvu->irq_allocated[irq_offs] = true;
0112     return 0;
0113 }
0114 
0115 static void cpt_10k_unregister_interrupts(struct rvu_block *block, int off)
0116 {
0117     struct rvu *rvu = block->rvu;
0118     int blkaddr = block->addr;
0119     int i;
0120 
0121     /* Disable all CPT AF interrupts */
0122     for (i = 0; i < CPT_10K_AF_INT_VEC_RVU; i++)
0123         rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(i), 0x1);
0124     rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1);
0125     rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1);
0126 
0127     for (i = 0; i < CPT_10K_AF_INT_VEC_CNT; i++)
0128         if (rvu->irq_allocated[off + i]) {
0129             free_irq(pci_irq_vector(rvu->pdev, off + i), block);
0130             rvu->irq_allocated[off + i] = false;
0131         }
0132 }
0133 
0134 static void cpt_unregister_interrupts(struct rvu *rvu, int blkaddr)
0135 {
0136     struct rvu_hwinfo *hw = rvu->hw;
0137     struct rvu_block *block;
0138     int i, offs;
0139 
0140     if (!is_block_implemented(rvu->hw, blkaddr))
0141         return;
0142     offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF;
0143     if (!offs) {
0144         dev_warn(rvu->dev,
0145              "Failed to get CPT_AF_INT vector offsets\n");
0146         return;
0147     }
0148     block = &hw->block[blkaddr];
0149     if (!is_rvu_otx2(rvu))
0150         return cpt_10k_unregister_interrupts(block, offs);
0151 
0152     /* Disable all CPT AF interrupts */
0153     for (i = 0; i < CPT_AF_INT_VEC_RVU; i++)
0154         rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1C(i), 0x1);
0155     rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1C, 0x1);
0156     rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1C, 0x1);
0157 
0158     for (i = 0; i < CPT_AF_INT_VEC_CNT; i++)
0159         if (rvu->irq_allocated[offs + i]) {
0160             free_irq(pci_irq_vector(rvu->pdev, offs + i), block);
0161             rvu->irq_allocated[offs + i] = false;
0162         }
0163 }
0164 
0165 void rvu_cpt_unregister_interrupts(struct rvu *rvu)
0166 {
0167     cpt_unregister_interrupts(rvu, BLKADDR_CPT0);
0168     cpt_unregister_interrupts(rvu, BLKADDR_CPT1);
0169 }
0170 
0171 static int cpt_10k_register_interrupts(struct rvu_block *block, int off)
0172 {
0173     struct rvu *rvu = block->rvu;
0174     int blkaddr = block->addr;
0175     int i, ret;
0176 
0177     for (i = CPT_10K_AF_INT_VEC_FLT0; i < CPT_10K_AF_INT_VEC_RVU; i++) {
0178         sprintf(&rvu->irq_name[(off + i) * NAME_SIZE], "CPTAF FLT%d", i);
0179         ret = rvu_cpt_do_register_interrupt(block, off + i,
0180                             rvu_cpt_af_flt_intr_handler,
0181                             &rvu->irq_name[(off + i) * NAME_SIZE]);
0182         if (ret)
0183             goto err;
0184         rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), 0x1);
0185     }
0186 
0187     ret = rvu_cpt_do_register_interrupt(block, off + CPT_10K_AF_INT_VEC_RVU,
0188                         rvu_cpt_af_rvu_intr_handler,
0189                         "CPTAF RVU");
0190     if (ret)
0191         goto err;
0192     rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1);
0193 
0194     ret = rvu_cpt_do_register_interrupt(block, off + CPT_10K_AF_INT_VEC_RAS,
0195                         rvu_cpt_af_ras_intr_handler,
0196                         "CPTAF RAS");
0197     if (ret)
0198         goto err;
0199     rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1S, 0x1);
0200 
0201     return 0;
0202 err:
0203     rvu_cpt_unregister_interrupts(rvu);
0204     return ret;
0205 }
0206 
0207 static int cpt_register_interrupts(struct rvu *rvu, int blkaddr)
0208 {
0209     struct rvu_hwinfo *hw = rvu->hw;
0210     struct rvu_block *block;
0211     int i, offs, ret = 0;
0212     char irq_name[16];
0213 
0214     if (!is_block_implemented(rvu->hw, blkaddr))
0215         return 0;
0216 
0217     block = &hw->block[blkaddr];
0218     offs = rvu_read64(rvu, blkaddr, CPT_PRIV_AF_INT_CFG) & 0x7FF;
0219     if (!offs) {
0220         dev_warn(rvu->dev,
0221              "Failed to get CPT_AF_INT vector offsets\n");
0222         return 0;
0223     }
0224 
0225     if (!is_rvu_otx2(rvu))
0226         return cpt_10k_register_interrupts(block, offs);
0227 
0228     for (i = CPT_AF_INT_VEC_FLT0; i < CPT_AF_INT_VEC_RVU; i++) {
0229         snprintf(irq_name, sizeof(irq_name), "CPTAF FLT%d", i);
0230         ret = rvu_cpt_do_register_interrupt(block, offs + i,
0231                             rvu_cpt_af_flt_intr_handler,
0232                             irq_name);
0233         if (ret)
0234             goto err;
0235         rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT_ENA_W1S(i), 0x1);
0236     }
0237 
0238     ret = rvu_cpt_do_register_interrupt(block, offs + CPT_AF_INT_VEC_RVU,
0239                         rvu_cpt_af_rvu_intr_handler,
0240                         "CPTAF RVU");
0241     if (ret)
0242         goto err;
0243     rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT_ENA_W1S, 0x1);
0244 
0245     ret = rvu_cpt_do_register_interrupt(block, offs + CPT_AF_INT_VEC_RAS,
0246                         rvu_cpt_af_ras_intr_handler,
0247                         "CPTAF RAS");
0248     if (ret)
0249         goto err;
0250     rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT_ENA_W1S, 0x1);
0251 
0252     return 0;
0253 err:
0254     rvu_cpt_unregister_interrupts(rvu);
0255     return ret;
0256 }
0257 
0258 int rvu_cpt_register_interrupts(struct rvu *rvu)
0259 {
0260     int ret;
0261 
0262     ret = cpt_register_interrupts(rvu, BLKADDR_CPT0);
0263     if (ret)
0264         return ret;
0265 
0266     return cpt_register_interrupts(rvu, BLKADDR_CPT1);
0267 }
0268 
0269 static int get_cpt_pf_num(struct rvu *rvu)
0270 {
0271     int i, domain_nr, cpt_pf_num = -1;
0272     struct pci_dev *pdev;
0273 
0274     domain_nr = pci_domain_nr(rvu->pdev->bus);
0275     for (i = 0; i < rvu->hw->total_pfs; i++) {
0276         pdev = pci_get_domain_bus_and_slot(domain_nr, i + 1, 0);
0277         if (!pdev)
0278             continue;
0279 
0280         if (pdev->device == PCI_DEVID_OTX2_CPT_PF ||
0281             pdev->device == PCI_DEVID_OTX2_CPT10K_PF) {
0282             cpt_pf_num = i;
0283             put_device(&pdev->dev);
0284             break;
0285         }
0286         put_device(&pdev->dev);
0287     }
0288     return cpt_pf_num;
0289 }
0290 
0291 static bool is_cpt_pf(struct rvu *rvu, u16 pcifunc)
0292 {
0293     int cpt_pf_num = get_cpt_pf_num(rvu);
0294 
0295     if (rvu_get_pf(pcifunc) != cpt_pf_num)
0296         return false;
0297     if (pcifunc & RVU_PFVF_FUNC_MASK)
0298         return false;
0299 
0300     return true;
0301 }
0302 
0303 static bool is_cpt_vf(struct rvu *rvu, u16 pcifunc)
0304 {
0305     int cpt_pf_num = get_cpt_pf_num(rvu);
0306 
0307     if (rvu_get_pf(pcifunc) != cpt_pf_num)
0308         return false;
0309     if (!(pcifunc & RVU_PFVF_FUNC_MASK))
0310         return false;
0311 
0312     return true;
0313 }
0314 
0315 static int validate_and_get_cpt_blkaddr(int req_blkaddr)
0316 {
0317     int blkaddr;
0318 
0319     blkaddr = req_blkaddr ? req_blkaddr : BLKADDR_CPT0;
0320     if (blkaddr != BLKADDR_CPT0 && blkaddr != BLKADDR_CPT1)
0321         return -EINVAL;
0322 
0323     return blkaddr;
0324 }
0325 
0326 int rvu_mbox_handler_cpt_lf_alloc(struct rvu *rvu,
0327                   struct cpt_lf_alloc_req_msg *req,
0328                   struct msg_rsp *rsp)
0329 {
0330     u16 pcifunc = req->hdr.pcifunc;
0331     struct rvu_block *block;
0332     int cptlf, blkaddr;
0333     int num_lfs, slot;
0334     u64 val;
0335 
0336     blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
0337     if (blkaddr < 0)
0338         return blkaddr;
0339 
0340     if (req->eng_grpmsk == 0x0)
0341         return CPT_AF_ERR_GRP_INVALID;
0342 
0343     block = &rvu->hw->block[blkaddr];
0344     num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
0345                     block->addr);
0346     if (!num_lfs)
0347         return CPT_AF_ERR_LF_INVALID;
0348 
0349     /* Check if requested 'CPTLF <=> NIXLF' mapping is valid */
0350     if (req->nix_pf_func) {
0351         /* If default, use 'this' CPTLF's PFFUNC */
0352         if (req->nix_pf_func == RVU_DEFAULT_PF_FUNC)
0353             req->nix_pf_func = pcifunc;
0354         if (!is_pffunc_map_valid(rvu, req->nix_pf_func, BLKTYPE_NIX))
0355             return CPT_AF_ERR_NIX_PF_FUNC_INVALID;
0356     }
0357 
0358     /* Check if requested 'CPTLF <=> SSOLF' mapping is valid */
0359     if (req->sso_pf_func) {
0360         /* If default, use 'this' CPTLF's PFFUNC */
0361         if (req->sso_pf_func == RVU_DEFAULT_PF_FUNC)
0362             req->sso_pf_func = pcifunc;
0363         if (!is_pffunc_map_valid(rvu, req->sso_pf_func, BLKTYPE_SSO))
0364             return CPT_AF_ERR_SSO_PF_FUNC_INVALID;
0365     }
0366 
0367     for (slot = 0; slot < num_lfs; slot++) {
0368         cptlf = rvu_get_lf(rvu, block, pcifunc, slot);
0369         if (cptlf < 0)
0370             return CPT_AF_ERR_LF_INVALID;
0371 
0372         /* Set CPT LF group and priority */
0373         val = (u64)req->eng_grpmsk << 48 | 1;
0374         if (!is_rvu_otx2(rvu))
0375             val |= (CPT_CTX_ILEN << 17);
0376 
0377         rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
0378 
0379         /* Set CPT LF NIX_PF_FUNC and SSO_PF_FUNC. EXE_LDWB is set
0380          * on reset.
0381          */
0382         val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
0383         val &= ~(GENMASK_ULL(63, 48) | GENMASK_ULL(47, 32));
0384         val |= ((u64)req->nix_pf_func << 48 |
0385             (u64)req->sso_pf_func << 32);
0386         rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val);
0387     }
0388 
0389     return 0;
0390 }
0391 
0392 static int cpt_lf_free(struct rvu *rvu, struct msg_req *req, int blkaddr)
0393 {
0394     u16 pcifunc = req->hdr.pcifunc;
0395     int num_lfs, cptlf, slot, err;
0396     struct rvu_block *block;
0397 
0398     block = &rvu->hw->block[blkaddr];
0399     num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
0400                     block->addr);
0401     if (!num_lfs)
0402         return 0;
0403 
0404     for (slot = 0; slot < num_lfs; slot++) {
0405         cptlf = rvu_get_lf(rvu, block, pcifunc, slot);
0406         if (cptlf < 0)
0407             return CPT_AF_ERR_LF_INVALID;
0408 
0409         /* Perform teardown */
0410         rvu_cpt_lf_teardown(rvu, pcifunc, blkaddr, cptlf, slot);
0411 
0412         /* Reset LF */
0413         err = rvu_lf_reset(rvu, block, cptlf);
0414         if (err) {
0415             dev_err(rvu->dev, "Failed to reset blkaddr %d LF%d\n",
0416                 block->addr, cptlf);
0417         }
0418     }
0419 
0420     return 0;
0421 }
0422 
0423 int rvu_mbox_handler_cpt_lf_free(struct rvu *rvu, struct msg_req *req,
0424                  struct msg_rsp *rsp)
0425 {
0426     int ret;
0427 
0428     ret = cpt_lf_free(rvu, req, BLKADDR_CPT0);
0429     if (ret)
0430         return ret;
0431 
0432     if (is_block_implemented(rvu->hw, BLKADDR_CPT1))
0433         ret = cpt_lf_free(rvu, req, BLKADDR_CPT1);
0434 
0435     return ret;
0436 }
0437 
0438 static int cpt_inline_ipsec_cfg_inbound(struct rvu *rvu, int blkaddr, u8 cptlf,
0439                     struct cpt_inline_ipsec_cfg_msg *req)
0440 {
0441     u16 sso_pf_func = req->sso_pf_func;
0442     u8 nix_sel;
0443     u64 val;
0444 
0445     val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf));
0446     if (req->enable && (val & BIT_ULL(16))) {
0447         /* IPSec inline outbound path is already enabled for a given
0448          * CPT LF, HRM states that inline inbound & outbound paths
0449          * must not be enabled at the same time for a given CPT LF
0450          */
0451         return CPT_AF_ERR_INLINE_IPSEC_INB_ENA;
0452     }
0453     /* Check if requested 'CPTLF <=> SSOLF' mapping is valid */
0454     if (sso_pf_func && !is_pffunc_map_valid(rvu, sso_pf_func, BLKTYPE_SSO))
0455         return CPT_AF_ERR_SSO_PF_FUNC_INVALID;
0456 
0457     nix_sel = (blkaddr == BLKADDR_CPT1) ? 1 : 0;
0458     /* Enable CPT LF for IPsec inline inbound operations */
0459     if (req->enable)
0460         val |= BIT_ULL(9);
0461     else
0462         val &= ~BIT_ULL(9);
0463 
0464     val |= (u64)nix_sel << 8;
0465     rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
0466 
0467     if (sso_pf_func) {
0468         /* Set SSO_PF_FUNC */
0469         val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
0470         val |= (u64)sso_pf_func << 32;
0471         val |= (u64)req->nix_pf_func << 48;
0472         rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val);
0473     }
0474     if (req->sso_pf_func_ovrd)
0475         /* Set SSO_PF_FUNC_OVRD for inline IPSec */
0476         rvu_write64(rvu, blkaddr, CPT_AF_ECO, 0x1);
0477 
0478     /* Configure the X2P Link register with the cpt base channel number and
0479      * range of channels it should propagate to X2P
0480      */
0481     if (!is_rvu_otx2(rvu)) {
0482         val = (ilog2(NIX_CHAN_CPT_X2P_MASK + 1) << 16);
0483         val |= (u64)rvu->hw->cpt_chan_base;
0484 
0485         rvu_write64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0), val);
0486         rvu_write64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1), val);
0487     }
0488 
0489     return 0;
0490 }
0491 
0492 static int cpt_inline_ipsec_cfg_outbound(struct rvu *rvu, int blkaddr, u8 cptlf,
0493                      struct cpt_inline_ipsec_cfg_msg *req)
0494 {
0495     u16 nix_pf_func = req->nix_pf_func;
0496     int nix_blkaddr;
0497     u8 nix_sel;
0498     u64 val;
0499 
0500     val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf));
0501     if (req->enable && (val & BIT_ULL(9))) {
0502         /* IPSec inline inbound path is already enabled for a given
0503          * CPT LF, HRM states that inline inbound & outbound paths
0504          * must not be enabled at the same time for a given CPT LF
0505          */
0506         return CPT_AF_ERR_INLINE_IPSEC_OUT_ENA;
0507     }
0508 
0509     /* Check if requested 'CPTLF <=> NIXLF' mapping is valid */
0510     if (nix_pf_func && !is_pffunc_map_valid(rvu, nix_pf_func, BLKTYPE_NIX))
0511         return CPT_AF_ERR_NIX_PF_FUNC_INVALID;
0512 
0513     /* Enable CPT LF for IPsec inline outbound operations */
0514     if (req->enable)
0515         val |= BIT_ULL(16);
0516     else
0517         val &= ~BIT_ULL(16);
0518     rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
0519 
0520     if (nix_pf_func) {
0521         /* Set NIX_PF_FUNC */
0522         val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf));
0523         val |= (u64)nix_pf_func << 48;
0524         rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL2(cptlf), val);
0525 
0526         nix_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, nix_pf_func);
0527         nix_sel = (nix_blkaddr == BLKADDR_NIX0) ? 0 : 1;
0528 
0529         val = rvu_read64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf));
0530         val |= (u64)nix_sel << 8;
0531         rvu_write64(rvu, blkaddr, CPT_AF_LFX_CTL(cptlf), val);
0532     }
0533 
0534     return 0;
0535 }
0536 
0537 int rvu_mbox_handler_cpt_inline_ipsec_cfg(struct rvu *rvu,
0538                       struct cpt_inline_ipsec_cfg_msg *req,
0539                       struct msg_rsp *rsp)
0540 {
0541     u16 pcifunc = req->hdr.pcifunc;
0542     struct rvu_block *block;
0543     int cptlf, blkaddr, ret;
0544     u16 actual_slot;
0545 
0546     blkaddr = rvu_get_blkaddr_from_slot(rvu, BLKTYPE_CPT, pcifunc,
0547                         req->slot, &actual_slot);
0548     if (blkaddr < 0)
0549         return CPT_AF_ERR_LF_INVALID;
0550 
0551     block = &rvu->hw->block[blkaddr];
0552 
0553     cptlf = rvu_get_lf(rvu, block, pcifunc, actual_slot);
0554     if (cptlf < 0)
0555         return CPT_AF_ERR_LF_INVALID;
0556 
0557     switch (req->dir) {
0558     case CPT_INLINE_INBOUND:
0559         ret = cpt_inline_ipsec_cfg_inbound(rvu, blkaddr, cptlf, req);
0560         break;
0561 
0562     case CPT_INLINE_OUTBOUND:
0563         ret = cpt_inline_ipsec_cfg_outbound(rvu, blkaddr, cptlf, req);
0564         break;
0565 
0566     default:
0567         return CPT_AF_ERR_PARAM;
0568     }
0569 
0570     return ret;
0571 }
0572 
0573 static bool is_valid_offset(struct rvu *rvu, struct cpt_rd_wr_reg_msg *req)
0574 {
0575     u64 offset = req->reg_offset;
0576     int blkaddr, num_lfs, lf;
0577     struct rvu_block *block;
0578     struct rvu_pfvf *pfvf;
0579 
0580     blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
0581     if (blkaddr < 0)
0582         return false;
0583 
0584     /* Registers that can be accessed from PF/VF */
0585     if ((offset & 0xFF000) ==  CPT_AF_LFX_CTL(0) ||
0586         (offset & 0xFF000) ==  CPT_AF_LFX_CTL2(0)) {
0587         if (offset & 7)
0588             return false;
0589 
0590         lf = (offset & 0xFFF) >> 3;
0591         block = &rvu->hw->block[blkaddr];
0592         pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc);
0593         num_lfs = rvu_get_rsrc_mapcount(pfvf, block->addr);
0594         if (lf >= num_lfs)
0595             /* Slot is not valid for that PF/VF */
0596             return false;
0597 
0598         /* Translate local LF used by VFs to global CPT LF */
0599         lf = rvu_get_lf(rvu, &rvu->hw->block[blkaddr],
0600                 req->hdr.pcifunc, lf);
0601         if (lf < 0)
0602             return false;
0603 
0604         return true;
0605     } else if (!(req->hdr.pcifunc & RVU_PFVF_FUNC_MASK)) {
0606         /* Registers that can be accessed from PF */
0607         switch (offset) {
0608         case CPT_AF_DIAG:
0609         case CPT_AF_CTL:
0610         case CPT_AF_PF_FUNC:
0611         case CPT_AF_BLK_RST:
0612         case CPT_AF_CONSTANTS1:
0613         case CPT_AF_CTX_FLUSH_TIMER:
0614             return true;
0615         }
0616 
0617         switch (offset & 0xFF000) {
0618         case CPT_AF_EXEX_STS(0):
0619         case CPT_AF_EXEX_CTL(0):
0620         case CPT_AF_EXEX_CTL2(0):
0621         case CPT_AF_EXEX_UCODE_BASE(0):
0622             if (offset & 7)
0623                 return false;
0624             break;
0625         default:
0626             return false;
0627         }
0628         return true;
0629     }
0630     return false;
0631 }
0632 
0633 int rvu_mbox_handler_cpt_rd_wr_register(struct rvu *rvu,
0634                     struct cpt_rd_wr_reg_msg *req,
0635                     struct cpt_rd_wr_reg_msg *rsp)
0636 {
0637     int blkaddr;
0638 
0639     blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
0640     if (blkaddr < 0)
0641         return blkaddr;
0642 
0643     /* This message is accepted only if sent from CPT PF/VF */
0644     if (!is_cpt_pf(rvu, req->hdr.pcifunc) &&
0645         !is_cpt_vf(rvu, req->hdr.pcifunc))
0646         return CPT_AF_ERR_ACCESS_DENIED;
0647 
0648     rsp->reg_offset = req->reg_offset;
0649     rsp->ret_val = req->ret_val;
0650     rsp->is_write = req->is_write;
0651 
0652     if (!is_valid_offset(rvu, req))
0653         return CPT_AF_ERR_ACCESS_DENIED;
0654 
0655     if (req->is_write)
0656         rvu_write64(rvu, blkaddr, req->reg_offset, req->val);
0657     else
0658         rsp->val = rvu_read64(rvu, blkaddr, req->reg_offset);
0659 
0660     return 0;
0661 }
0662 
0663 static void get_ctx_pc(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr)
0664 {
0665     if (is_rvu_otx2(rvu))
0666         return;
0667 
0668     rsp->ctx_mis_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_MIS_PC);
0669     rsp->ctx_hit_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_HIT_PC);
0670     rsp->ctx_aop_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_AOP_PC);
0671     rsp->ctx_aop_lat_pc = rvu_read64(rvu, blkaddr,
0672                      CPT_AF_CTX_AOP_LATENCY_PC);
0673     rsp->ctx_ifetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_IFETCH_PC);
0674     rsp->ctx_ifetch_lat_pc = rvu_read64(rvu, blkaddr,
0675                         CPT_AF_CTX_IFETCH_LATENCY_PC);
0676     rsp->ctx_ffetch_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC);
0677     rsp->ctx_ffetch_lat_pc = rvu_read64(rvu, blkaddr,
0678                         CPT_AF_CTX_FFETCH_LATENCY_PC);
0679     rsp->ctx_wback_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC);
0680     rsp->ctx_wback_lat_pc = rvu_read64(rvu, blkaddr,
0681                        CPT_AF_CTX_FFETCH_LATENCY_PC);
0682     rsp->ctx_psh_pc = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FFETCH_PC);
0683     rsp->ctx_psh_lat_pc = rvu_read64(rvu, blkaddr,
0684                      CPT_AF_CTX_FFETCH_LATENCY_PC);
0685     rsp->ctx_err = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ERR);
0686     rsp->ctx_enc_id = rvu_read64(rvu, blkaddr, CPT_AF_CTX_ENC_ID);
0687     rsp->ctx_flush_timer = rvu_read64(rvu, blkaddr, CPT_AF_CTX_FLUSH_TIMER);
0688 
0689     rsp->rxc_time = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME);
0690     rsp->rxc_time_cfg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG);
0691     rsp->rxc_active_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ACTIVE_STS);
0692     rsp->rxc_zombie_sts = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ZOMBIE_STS);
0693     rsp->rxc_dfrg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_DFRG);
0694     rsp->x2p_link_cfg0 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(0));
0695     rsp->x2p_link_cfg1 = rvu_read64(rvu, blkaddr, CPT_AF_X2PX_LINK_CFG(1));
0696 }
0697 
0698 static void get_eng_sts(struct rvu *rvu, struct cpt_sts_rsp *rsp, int blkaddr)
0699 {
0700     u16 max_ses, max_ies, max_aes;
0701     u32 e_min = 0, e_max = 0;
0702     u64 reg;
0703 
0704     reg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS1);
0705     max_ses = reg & 0xffff;
0706     max_ies = (reg >> 16) & 0xffff;
0707     max_aes = (reg >> 32) & 0xffff;
0708 
0709     /* Get AE status */
0710     e_min = max_ses + max_ies;
0711     e_max = max_ses + max_ies + max_aes;
0712     cpt_get_eng_sts(e_min, e_max, rsp, ae);
0713     /* Get SE status */
0714     e_min = 0;
0715     e_max = max_ses;
0716     cpt_get_eng_sts(e_min, e_max, rsp, se);
0717     /* Get IE status */
0718     e_min = max_ses;
0719     e_max = max_ses + max_ies;
0720     cpt_get_eng_sts(e_min, e_max, rsp, ie);
0721 }
0722 
0723 int rvu_mbox_handler_cpt_sts(struct rvu *rvu, struct cpt_sts_req *req,
0724                  struct cpt_sts_rsp *rsp)
0725 {
0726     int blkaddr;
0727 
0728     blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
0729     if (blkaddr < 0)
0730         return blkaddr;
0731 
0732     /* This message is accepted only if sent from CPT PF/VF */
0733     if (!is_cpt_pf(rvu, req->hdr.pcifunc) &&
0734         !is_cpt_vf(rvu, req->hdr.pcifunc))
0735         return CPT_AF_ERR_ACCESS_DENIED;
0736 
0737     get_ctx_pc(rvu, rsp, blkaddr);
0738 
0739     /* Get CPT engines status */
0740     get_eng_sts(rvu, rsp, blkaddr);
0741 
0742     /* Read CPT instruction PC registers */
0743     rsp->inst_req_pc = rvu_read64(rvu, blkaddr, CPT_AF_INST_REQ_PC);
0744     rsp->inst_lat_pc = rvu_read64(rvu, blkaddr, CPT_AF_INST_LATENCY_PC);
0745     rsp->rd_req_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_REQ_PC);
0746     rsp->rd_lat_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_LATENCY_PC);
0747     rsp->rd_uc_pc = rvu_read64(rvu, blkaddr, CPT_AF_RD_UC_PC);
0748     rsp->active_cycles_pc = rvu_read64(rvu, blkaddr,
0749                        CPT_AF_ACTIVE_CYCLES_PC);
0750     rsp->exe_err_info = rvu_read64(rvu, blkaddr, CPT_AF_EXE_ERR_INFO);
0751     rsp->cptclk_cnt = rvu_read64(rvu, blkaddr, CPT_AF_CPTCLK_CNT);
0752     rsp->diag = rvu_read64(rvu, blkaddr, CPT_AF_DIAG);
0753 
0754     return 0;
0755 }
0756 
0757 #define RXC_ZOMBIE_THRES  GENMASK_ULL(59, 48)
0758 #define RXC_ZOMBIE_LIMIT  GENMASK_ULL(43, 32)
0759 #define RXC_ACTIVE_THRES  GENMASK_ULL(27, 16)
0760 #define RXC_ACTIVE_LIMIT  GENMASK_ULL(11, 0)
0761 #define RXC_ACTIVE_COUNT  GENMASK_ULL(60, 48)
0762 #define RXC_ZOMBIE_COUNT  GENMASK_ULL(60, 48)
0763 
0764 static void cpt_rxc_time_cfg(struct rvu *rvu, struct cpt_rxc_time_cfg_req *req,
0765                  int blkaddr)
0766 {
0767     u64 dfrg_reg;
0768 
0769     dfrg_reg = FIELD_PREP(RXC_ZOMBIE_THRES, req->zombie_thres);
0770     dfrg_reg |= FIELD_PREP(RXC_ZOMBIE_LIMIT, req->zombie_limit);
0771     dfrg_reg |= FIELD_PREP(RXC_ACTIVE_THRES, req->active_thres);
0772     dfrg_reg |= FIELD_PREP(RXC_ACTIVE_LIMIT, req->active_limit);
0773 
0774     rvu_write64(rvu, blkaddr, CPT_AF_RXC_TIME_CFG, req->step);
0775     rvu_write64(rvu, blkaddr, CPT_AF_RXC_DFRG, dfrg_reg);
0776 }
0777 
0778 int rvu_mbox_handler_cpt_rxc_time_cfg(struct rvu *rvu,
0779                       struct cpt_rxc_time_cfg_req *req,
0780                       struct msg_rsp *rsp)
0781 {
0782     int blkaddr;
0783 
0784     blkaddr = validate_and_get_cpt_blkaddr(req->blkaddr);
0785     if (blkaddr < 0)
0786         return blkaddr;
0787 
0788     /* This message is accepted only if sent from CPT PF/VF */
0789     if (!is_cpt_pf(rvu, req->hdr.pcifunc) &&
0790         !is_cpt_vf(rvu, req->hdr.pcifunc))
0791         return CPT_AF_ERR_ACCESS_DENIED;
0792 
0793     cpt_rxc_time_cfg(rvu, req, blkaddr);
0794 
0795     return 0;
0796 }
0797 
0798 int rvu_mbox_handler_cpt_ctx_cache_sync(struct rvu *rvu, struct msg_req *req,
0799                     struct msg_rsp *rsp)
0800 {
0801     return rvu_cpt_ctx_flush(rvu, req->hdr.pcifunc);
0802 }
0803 
0804 static void cpt_rxc_teardown(struct rvu *rvu, int blkaddr)
0805 {
0806     struct cpt_rxc_time_cfg_req req;
0807     int timeout = 2000;
0808     u64 reg;
0809 
0810     if (is_rvu_otx2(rvu))
0811         return;
0812 
0813     /* Set time limit to minimum values, so that rxc entries will be
0814      * flushed out quickly.
0815      */
0816     req.step = 1;
0817     req.zombie_thres = 1;
0818     req.zombie_limit = 1;
0819     req.active_thres = 1;
0820     req.active_limit = 1;
0821 
0822     cpt_rxc_time_cfg(rvu, &req, blkaddr);
0823 
0824     do {
0825         reg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ACTIVE_STS);
0826         udelay(1);
0827         if (FIELD_GET(RXC_ACTIVE_COUNT, reg))
0828             timeout--;
0829         else
0830             break;
0831     } while (timeout);
0832 
0833     if (timeout == 0)
0834         dev_warn(rvu->dev, "Poll for RXC active count hits hard loop counter\n");
0835 
0836     timeout = 2000;
0837     do {
0838         reg = rvu_read64(rvu, blkaddr, CPT_AF_RXC_ZOMBIE_STS);
0839         udelay(1);
0840         if (FIELD_GET(RXC_ZOMBIE_COUNT, reg))
0841             timeout--;
0842         else
0843             break;
0844     } while (timeout);
0845 
0846     if (timeout == 0)
0847         dev_warn(rvu->dev, "Poll for RXC zombie count hits hard loop counter\n");
0848 }
0849 
0850 #define INPROG_INFLIGHT(reg)    ((reg) & 0x1FF)
0851 #define INPROG_GRB_PARTIAL(reg) ((reg) & BIT_ULL(31))
0852 #define INPROG_GRB(reg)         (((reg) >> 32) & 0xFF)
0853 #define INPROG_GWB(reg)         (((reg) >> 40) & 0xFF)
0854 
0855 static void cpt_lf_disable_iqueue(struct rvu *rvu, int blkaddr, int slot)
0856 {
0857     int i = 0, hard_lp_ctr = 100000;
0858     u64 inprog, grp_ptr;
0859     u16 nq_ptr, dq_ptr;
0860 
0861     /* Disable instructions enqueuing */
0862     rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTL), 0x0);
0863 
0864     /* Disable executions in the LF's queue */
0865     inprog = rvu_read64(rvu, blkaddr,
0866                 CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG));
0867     inprog &= ~BIT_ULL(16);
0868     rvu_write64(rvu, blkaddr,
0869             CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), inprog);
0870 
0871     /* Wait for CPT queue to become execution-quiescent */
0872     do {
0873         inprog = rvu_read64(rvu, blkaddr,
0874                     CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG));
0875         if (INPROG_GRB_PARTIAL(inprog)) {
0876             i = 0;
0877             hard_lp_ctr--;
0878         } else {
0879             i++;
0880         }
0881 
0882         grp_ptr = rvu_read64(rvu, blkaddr,
0883                      CPT_AF_BAR2_ALIASX(slot,
0884                             CPT_LF_Q_GRP_PTR));
0885         nq_ptr = (grp_ptr >> 32) & 0x7FFF;
0886         dq_ptr = grp_ptr & 0x7FFF;
0887 
0888     } while (hard_lp_ctr && (i < 10) && (nq_ptr != dq_ptr));
0889 
0890     if (hard_lp_ctr == 0)
0891         dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n");
0892 
0893     i = 0;
0894     hard_lp_ctr = 100000;
0895     do {
0896         inprog = rvu_read64(rvu, blkaddr,
0897                     CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG));
0898 
0899         if ((INPROG_INFLIGHT(inprog) == 0) &&
0900             (INPROG_GWB(inprog) < 40) &&
0901             ((INPROG_GRB(inprog) == 0) ||
0902              (INPROG_GRB((inprog)) == 40))) {
0903             i++;
0904         } else {
0905             i = 0;
0906             hard_lp_ctr--;
0907         }
0908     } while (hard_lp_ctr && (i < 10));
0909 
0910     if (hard_lp_ctr == 0)
0911         dev_warn(rvu->dev, "CPT FLR hits hard loop counter\n");
0912 }
0913 
0914 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf, int slot)
0915 {
0916     u64 reg;
0917 
0918     if (is_cpt_pf(rvu, pcifunc) || is_cpt_vf(rvu, pcifunc))
0919         cpt_rxc_teardown(rvu, blkaddr);
0920 
0921     /* Enable BAR2 ALIAS for this pcifunc. */
0922     reg = BIT_ULL(16) | pcifunc;
0923     rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg);
0924 
0925     cpt_lf_disable_iqueue(rvu, blkaddr, slot);
0926 
0927     /* Set group drop to help clear out hardware */
0928     reg = rvu_read64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG));
0929     reg |= BIT_ULL(17);
0930     rvu_write64(rvu, blkaddr, CPT_AF_BAR2_ALIASX(slot, CPT_LF_INPROG), reg);
0931 
0932     rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0);
0933 
0934     return 0;
0935 }
0936 
0937 #define CPT_RES_LEN    16
0938 #define CPT_SE_IE_EGRP 1ULL
0939 
0940 static int cpt_inline_inb_lf_cmd_send(struct rvu *rvu, int blkaddr,
0941                       int nix_blkaddr)
0942 {
0943     int cpt_pf_num = get_cpt_pf_num(rvu);
0944     struct cpt_inst_lmtst_req *req;
0945     dma_addr_t res_daddr;
0946     int timeout = 3000;
0947     u8 cpt_idx;
0948     u64 *inst;
0949     u16 *res;
0950     int rc;
0951 
0952     res = kzalloc(CPT_RES_LEN, GFP_KERNEL);
0953     if (!res)
0954         return -ENOMEM;
0955 
0956     res_daddr = dma_map_single(rvu->dev, res, CPT_RES_LEN,
0957                    DMA_BIDIRECTIONAL);
0958     if (dma_mapping_error(rvu->dev, res_daddr)) {
0959         dev_err(rvu->dev, "DMA mapping failed for CPT result\n");
0960         rc = -EFAULT;
0961         goto res_free;
0962     }
0963     *res = 0xFFFF;
0964 
0965     /* Send mbox message to CPT PF */
0966     req = (struct cpt_inst_lmtst_req *)
0967            otx2_mbox_alloc_msg_rsp(&rvu->afpf_wq_info.mbox_up,
0968                        cpt_pf_num, sizeof(*req),
0969                        sizeof(struct msg_rsp));
0970     if (!req) {
0971         rc = -ENOMEM;
0972         goto res_daddr_unmap;
0973     }
0974     req->hdr.sig = OTX2_MBOX_REQ_SIG;
0975     req->hdr.id = MBOX_MSG_CPT_INST_LMTST;
0976 
0977     inst = req->inst;
0978     /* Prepare CPT_INST_S */
0979     inst[0] = 0;
0980     inst[1] = res_daddr;
0981     /* AF PF FUNC */
0982     inst[2] = 0;
0983     /* Set QORD */
0984     inst[3] = 1;
0985     inst[4] = 0;
0986     inst[5] = 0;
0987     inst[6] = 0;
0988     /* Set EGRP */
0989     inst[7] = CPT_SE_IE_EGRP << 61;
0990 
0991     /* Subtract 1 from the NIX-CPT credit count to preserve
0992      * credit counts.
0993      */
0994     cpt_idx = (blkaddr == BLKADDR_CPT0) ? 0 : 1;
0995     rvu_write64(rvu, nix_blkaddr, NIX_AF_RX_CPTX_CREDIT(cpt_idx),
0996             BIT_ULL(22) - 1);
0997 
0998     otx2_mbox_msg_send(&rvu->afpf_wq_info.mbox_up, cpt_pf_num);
0999     rc = otx2_mbox_wait_for_rsp(&rvu->afpf_wq_info.mbox_up, cpt_pf_num);
1000     if (rc)
1001         dev_warn(rvu->dev, "notification to pf %d failed\n",
1002              cpt_pf_num);
1003     /* Wait for CPT instruction to be completed */
1004     do {
1005         mdelay(1);
1006         if (*res == 0xFFFF)
1007             timeout--;
1008         else
1009             break;
1010     } while (timeout);
1011 
1012     if (timeout == 0)
1013         dev_warn(rvu->dev, "Poll for result hits hard loop counter\n");
1014 
1015 res_daddr_unmap:
1016     dma_unmap_single(rvu->dev, res_daddr, CPT_RES_LEN, DMA_BIDIRECTIONAL);
1017 res_free:
1018     kfree(res);
1019 
1020     return 0;
1021 }
1022 
1023 #define CTX_CAM_PF_FUNC   GENMASK_ULL(61, 46)
1024 #define CTX_CAM_CPTR      GENMASK_ULL(45, 0)
1025 
1026 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc)
1027 {
1028     int nix_blkaddr, blkaddr;
1029     u16 max_ctx_entries, i;
1030     int slot = 0, num_lfs;
1031     u64 reg, cam_data;
1032     int rc;
1033 
1034     nix_blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc);
1035     if (nix_blkaddr < 0)
1036         return -EINVAL;
1037 
1038     if (is_rvu_otx2(rvu))
1039         return 0;
1040 
1041     blkaddr = (nix_blkaddr == BLKADDR_NIX1) ? BLKADDR_CPT1 : BLKADDR_CPT0;
1042 
1043     /* Submit CPT_INST_S to track when all packets have been
1044      * flushed through for the NIX PF FUNC in inline inbound case.
1045      */
1046     rc = cpt_inline_inb_lf_cmd_send(rvu, blkaddr, nix_blkaddr);
1047     if (rc)
1048         return rc;
1049 
1050     /* Wait for rxc entries to be flushed out */
1051     cpt_rxc_teardown(rvu, blkaddr);
1052 
1053     reg = rvu_read64(rvu, blkaddr, CPT_AF_CONSTANTS0);
1054     max_ctx_entries = (reg >> 48) & 0xFFF;
1055 
1056     mutex_lock(&rvu->rsrc_lock);
1057 
1058     num_lfs = rvu_get_rsrc_mapcount(rvu_get_pfvf(rvu, pcifunc),
1059                     blkaddr);
1060     if (num_lfs == 0) {
1061         dev_warn(rvu->dev, "CPT LF is not configured\n");
1062         goto unlock;
1063     }
1064 
1065     /* Enable BAR2 ALIAS for this pcifunc. */
1066     reg = BIT_ULL(16) | pcifunc;
1067     rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, reg);
1068 
1069     for (i = 0; i < max_ctx_entries; i++) {
1070         cam_data = rvu_read64(rvu, blkaddr, CPT_AF_CTX_CAM_DATA(i));
1071 
1072         if ((FIELD_GET(CTX_CAM_PF_FUNC, cam_data) == pcifunc) &&
1073             FIELD_GET(CTX_CAM_CPTR, cam_data)) {
1074             reg = BIT_ULL(46) | FIELD_GET(CTX_CAM_CPTR, cam_data);
1075             rvu_write64(rvu, blkaddr,
1076                     CPT_AF_BAR2_ALIASX(slot, CPT_LF_CTX_FLUSH),
1077                     reg);
1078         }
1079     }
1080     rvu_write64(rvu, blkaddr, CPT_AF_BAR2_SEL, 0);
1081 
1082 unlock:
1083     mutex_unlock(&rvu->rsrc_lock);
1084 
1085     return 0;
1086 }
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