Back to home page

OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Marvell RVU Admin Function driver
0003  *
0004  * Copyright (C) 2018 Marvell.
0005  *
0006  */
0007 
0008 #ifndef RVU_H
0009 #define RVU_H
0010 
0011 #include <linux/pci.h>
0012 #include <net/devlink.h>
0013 
0014 #include "rvu_struct.h"
0015 #include "rvu_devlink.h"
0016 #include "common.h"
0017 #include "mbox.h"
0018 #include "npc.h"
0019 #include "rvu_reg.h"
0020 
0021 /* PCI device IDs */
0022 #define PCI_DEVID_OCTEONTX2_RVU_AF      0xA065
0023 #define PCI_DEVID_OCTEONTX2_LBK         0xA061
0024 
0025 /* Subsystem Device ID */
0026 #define PCI_SUBSYS_DEVID_96XX                  0xB200
0027 #define PCI_SUBSYS_DEVID_CN10K_A           0xB900
0028 
0029 /* PCI BAR nos */
0030 #define PCI_AF_REG_BAR_NUM          0
0031 #define PCI_PF_REG_BAR_NUM          2
0032 #define PCI_MBOX_BAR_NUM            4
0033 
0034 #define NAME_SIZE               32
0035 #define MAX_NIX_BLKS                2
0036 #define MAX_CPT_BLKS                2
0037 
0038 /* PF_FUNC */
0039 #define RVU_PFVF_PF_SHIFT   10
0040 #define RVU_PFVF_PF_MASK    0x3F
0041 #define RVU_PFVF_FUNC_SHIFT 0
0042 #define RVU_PFVF_FUNC_MASK  0x3FF
0043 
0044 #ifdef CONFIG_DEBUG_FS
0045 struct dump_ctx {
0046     int lf;
0047     int id;
0048     bool    all;
0049 };
0050 
0051 struct cpt_ctx {
0052     int blkaddr;
0053     struct rvu *rvu;
0054 };
0055 
0056 struct rvu_debugfs {
0057     struct dentry *root;
0058     struct dentry *cgx_root;
0059     struct dentry *cgx;
0060     struct dentry *lmac;
0061     struct dentry *npa;
0062     struct dentry *nix;
0063     struct dentry *npc;
0064     struct dentry *cpt;
0065     struct dump_ctx npa_aura_ctx;
0066     struct dump_ctx npa_pool_ctx;
0067     struct dump_ctx nix_cq_ctx;
0068     struct dump_ctx nix_rq_ctx;
0069     struct dump_ctx nix_sq_ctx;
0070     struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
0071     int npa_qsize_id;
0072     int nix_qsize_id;
0073 };
0074 #endif
0075 
0076 struct rvu_work {
0077     struct  work_struct work;
0078     struct  rvu *rvu;
0079     int num_msgs;
0080     int up_num_msgs;
0081 };
0082 
0083 struct rsrc_bmap {
0084     unsigned long *bmap;    /* Pointer to resource bitmap */
0085     u16  max;       /* Max resource id or count */
0086 };
0087 
0088 struct rvu_block {
0089     struct rsrc_bmap    lf;
0090     struct admin_queue  *aq; /* NIX/NPA AQ */
0091     u16  *fn_map; /* LF to pcifunc mapping */
0092     bool multislot;
0093     bool implemented;
0094     u8   addr;  /* RVU_BLOCK_ADDR_E */
0095     u8   type;  /* RVU_BLOCK_TYPE_E */
0096     u8   lfshift;
0097     u64  lookup_reg;
0098     u64  pf_lfcnt_reg;
0099     u64  vf_lfcnt_reg;
0100     u64  lfcfg_reg;
0101     u64  msixcfg_reg;
0102     u64  lfreset_reg;
0103     unsigned char name[NAME_SIZE];
0104     struct rvu *rvu;
0105 };
0106 
0107 struct nix_mcast {
0108     struct qmem *mce_ctx;
0109     struct qmem *mcast_buf;
0110     int     replay_pkind;
0111     int     next_free_mce;
0112     struct mutex    mce_lock; /* Serialize MCE updates */
0113 };
0114 
0115 struct nix_mce_list {
0116     struct hlist_head   head;
0117     int         count;
0118     int         max;
0119 };
0120 
0121 /* layer metadata to uniquely identify a packet header field */
0122 struct npc_layer_mdata {
0123     u8 lid;
0124     u8 ltype;
0125     u8 hdr;
0126     u8 key;
0127     u8 len;
0128 };
0129 
0130 /* Structure to represent a field present in the
0131  * generated key. A key field may present anywhere and can
0132  * be of any size in the generated key. Once this structure
0133  * is populated for fields of interest then field's presence
0134  * and location (if present) can be known.
0135  */
0136 struct npc_key_field {
0137     /* Masks where all set bits indicate position
0138      * of a field in the key
0139      */
0140     u64 kw_mask[NPC_MAX_KWS_IN_KEY];
0141     /* Number of words in the key a field spans. If a field is
0142      * of 16 bytes and key offset is 4 then the field will use
0143      * 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
0144      * nr_kws will be 3(KW0, KW1 and KW2).
0145      */
0146     int nr_kws;
0147     /* used by packet header fields */
0148     struct npc_layer_mdata layer_mdata;
0149 };
0150 
0151 struct npc_mcam {
0152     struct rsrc_bmap counters;
0153     struct mutex    lock;   /* MCAM entries and counters update lock */
0154     unsigned long   *bmap;      /* bitmap, 0 => bmap_entries */
0155     unsigned long   *bmap_reverse;  /* Reverse bitmap, bmap_entries => 0 */
0156     u16 bmap_entries;   /* Number of unreserved MCAM entries */
0157     u16 bmap_fcnt;  /* MCAM entries free count */
0158     u16 *entry2pfvf_map;
0159     u16 *entry2cntr_map;
0160     u16 *cntr2pfvf_map;
0161     u16 *cntr_refcnt;
0162     u16 *entry2target_pffunc;
0163     u8  keysize;    /* MCAM keysize 112/224/448 bits */
0164     u8  banks;      /* Number of MCAM banks */
0165     u8  banks_per_entry;/* Number of keywords in key */
0166     u16 banksize;   /* Number of MCAM entries in each bank */
0167     u16 total_entries;  /* Total number of MCAM entries */
0168     u16 nixlf_offset;   /* Offset of nixlf rsvd uncast entries */
0169     u16 pf_offset;  /* Offset of PF's rsvd bcast, promisc entries */
0170     u16 lprio_count;
0171     u16 lprio_start;
0172     u16 hprio_count;
0173     u16 hprio_end;
0174     u16     rx_miss_act_cntr; /* Counter for RX MISS action */
0175     /* fields present in the generated key */
0176     struct npc_key_field    tx_key_fields[NPC_KEY_FIELDS_MAX];
0177     struct npc_key_field    rx_key_fields[NPC_KEY_FIELDS_MAX];
0178     u64 tx_features;
0179     u64 rx_features;
0180     struct list_head mcam_rules;
0181 };
0182 
0183 /* Structure for per RVU func info ie PF/VF */
0184 struct rvu_pfvf {
0185     bool        npalf; /* Only one NPALF per RVU_FUNC */
0186     bool        nixlf; /* Only one NIXLF per RVU_FUNC */
0187     u16     sso;
0188     u16     ssow;
0189     u16     cptlfs;
0190     u16     timlfs;
0191     u16     cpt1_lfs;
0192     u8      cgx_lmac;
0193 
0194     /* Block LF's MSIX vector info */
0195     struct rsrc_bmap msix;      /* Bitmap for MSIX vector alloc */
0196 #define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
0197     u16      *msix_lfmap; /* Vector to block LF mapping */
0198 
0199     /* NPA contexts */
0200     struct qmem *aura_ctx;
0201     struct qmem *pool_ctx;
0202     struct qmem *npa_qints_ctx;
0203     unsigned long   *aura_bmap;
0204     unsigned long   *pool_bmap;
0205 
0206     /* NIX contexts */
0207     struct qmem *rq_ctx;
0208     struct qmem *sq_ctx;
0209     struct qmem *cq_ctx;
0210     struct qmem *rss_ctx;
0211     struct qmem *cq_ints_ctx;
0212     struct qmem *nix_qints_ctx;
0213     unsigned long   *sq_bmap;
0214     unsigned long   *rq_bmap;
0215     unsigned long   *cq_bmap;
0216 
0217     u16     rx_chan_base;
0218     u16     tx_chan_base;
0219     u8              rx_chan_cnt; /* total number of RX channels */
0220     u8              tx_chan_cnt; /* total number of TX channels */
0221     u16     maxlen;
0222     u16     minlen;
0223 
0224     bool        hw_rx_tstamp_en; /* Is rx_tstamp enabled */
0225     u8      mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
0226     u8      default_mac[ETH_ALEN]; /* MAC address from FWdata */
0227 
0228     /* Broadcast/Multicast/Promisc pkt replication info */
0229     u16         bcast_mce_idx;
0230     u16         mcast_mce_idx;
0231     u16         promisc_mce_idx;
0232     struct nix_mce_list bcast_mce_list;
0233     struct nix_mce_list mcast_mce_list;
0234     struct nix_mce_list promisc_mce_list;
0235     bool            use_mce_list;
0236 
0237     struct rvu_npc_mcam_rule *def_ucast_rule;
0238 
0239     bool    cgx_in_use; /* this PF/VF using CGX? */
0240     int cgx_users;  /* number of cgx users - used only by PFs */
0241 
0242     int     intf_mode;
0243     u8  nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
0244     u8  nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
0245     u8  nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
0246     u8  lbkid;       /* NIX0/1 lbk link ID */
0247     u64     lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
0248     u64     lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
0249     unsigned long flags;
0250     struct  sdp_node_info *sdp_info;
0251 };
0252 
0253 enum rvu_pfvf_flags {
0254     NIXLF_INITIALIZED = 0,
0255     PF_SET_VF_MAC,
0256     PF_SET_VF_CFG,
0257     PF_SET_VF_TRUSTED,
0258 };
0259 
0260 #define RVU_CLEAR_VF_PERM  ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
0261 
0262 struct nix_txsch {
0263     struct rsrc_bmap schq;
0264     u8   lvl;
0265 #define NIX_TXSCHQ_FREE           BIT_ULL(1)
0266 #define NIX_TXSCHQ_CFG_DONE       BIT_ULL(0)
0267 #define TXSCH_MAP_FUNC(__pfvf_map)    ((__pfvf_map) & 0xFFFF)
0268 #define TXSCH_MAP_FLAGS(__pfvf_map)   ((__pfvf_map) >> 16)
0269 #define TXSCH_MAP(__func, __flags)    (((__func) & 0xFFFF) | ((__flags) << 16))
0270 #define TXSCH_SET_FLAG(__pfvf_map, flag)    ((__pfvf_map) | ((flag) << 16))
0271     u32  *pfvf_map;
0272 };
0273 
0274 struct nix_mark_format {
0275     u8 total;
0276     u8 in_use;
0277     u32 *cfg;
0278 };
0279 
0280 struct npc_pkind {
0281     struct rsrc_bmap rsrc;
0282     u32 *pfchan_map;
0283 };
0284 
0285 struct nix_flowkey {
0286 #define NIX_FLOW_KEY_ALG_MAX 32
0287     u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
0288     int in_use;
0289 };
0290 
0291 struct nix_lso {
0292     u8 total;
0293     u8 in_use;
0294 };
0295 
0296 struct nix_txvlan {
0297 #define NIX_TX_VTAG_DEF_MAX 0x400
0298     struct rsrc_bmap rsrc;
0299     u16 *entry2pfvf_map;
0300     struct mutex rsrc_lock; /* Serialize resource alloc/free */
0301 };
0302 
0303 struct nix_ipolicer {
0304     struct rsrc_bmap band_prof;
0305     u16 *pfvf_map;
0306     u16 *match_id;
0307     u16 *ref_count;
0308 };
0309 
0310 struct nix_hw {
0311     int blkaddr;
0312     struct rvu *rvu;
0313     struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
0314     struct nix_mcast mcast;
0315     struct nix_flowkey flowkey;
0316     struct nix_mark_format mark_format;
0317     struct nix_lso lso;
0318     struct nix_txvlan txvlan;
0319     struct nix_ipolicer *ipolicer;
0320     u64    *tx_credits;
0321 };
0322 
0323 /* RVU block's capabilities or functionality,
0324  * which vary by silicon version/skew.
0325  */
0326 struct hw_cap {
0327     /* Transmit side supported functionality */
0328     u8  nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
0329     u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
0330     u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
0331     u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
0332     bool    nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
0333     bool    nix_shaping;         /* Is shaping and coloring supported */
0334     bool    nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
0335     bool    nix_tx_link_bp;      /* Can link backpressure TL queues ? */
0336     bool    nix_rx_multicast;    /* Rx packet replication support */
0337     bool    nix_common_dwrr_mtu;     /* Common DWRR MTU for quantum config */
0338     bool    per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
0339     bool    programmable_chans; /* Channels programmable ? */
0340     bool    ipolicer;
0341     bool    npc_hash_extract; /* Hash extract enabled ? */
0342     bool    npc_exact_match_enabled; /* Exact match supported ? */
0343 };
0344 
0345 struct rvu_hwinfo {
0346     u8  total_pfs;   /* MAX RVU PFs HW supports */
0347     u16 total_vfs;   /* Max RVU VFs HW supports */
0348     u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
0349     u8  cgx;
0350     u8  lmac_per_cgx;
0351     u16 cgx_chan_base;  /* CGX base channel number */
0352     u16 lbk_chan_base;  /* LBK base channel number */
0353     u16 sdp_chan_base;  /* SDP base channel number */
0354     u16 cpt_chan_base;  /* CPT base channel number */
0355     u8  cgx_links;
0356     u8  lbk_links;
0357     u8  sdp_links;
0358     u8  cpt_links;  /* Number of CPT links */
0359     u8  npc_kpus;          /* No of parser units */
0360     u8  npc_pkinds;        /* No of port kinds */
0361     u8  npc_intfs;         /* No of interfaces */
0362     u8  npc_kpu_entries;   /* No of KPU entries */
0363     u16 npc_counters;      /* No of match stats counters */
0364     u32 lbk_bufsize;       /* FIFO size supported by LBK */
0365     bool    npc_ext_set;       /* Extended register set */
0366     u64     npc_stat_ena;      /* Match stats enable bit */
0367 
0368     struct hw_cap    cap;
0369     struct rvu_block block[BLK_COUNT]; /* Block info */
0370     struct nix_hw    *nix;
0371     struct rvu   *rvu;
0372     struct npc_pkind pkind;
0373     struct npc_mcam  mcam;
0374     struct npc_exact_table *table;
0375 };
0376 
0377 struct mbox_wq_info {
0378     struct otx2_mbox mbox;
0379     struct rvu_work *mbox_wrk;
0380 
0381     struct otx2_mbox mbox_up;
0382     struct rvu_work *mbox_wrk_up;
0383 
0384     struct workqueue_struct *mbox_wq;
0385 };
0386 
0387 struct rvu_fwdata {
0388 #define RVU_FWDATA_HEADER_MAGIC 0xCFDA  /* Custom Firmware Data*/
0389 #define RVU_FWDATA_VERSION  0x0001
0390     u32 header_magic;
0391     u32 version;        /* version id */
0392 
0393     /* MAC address */
0394 #define PF_MACNUM_MAX   32
0395 #define VF_MACNUM_MAX   256
0396     u64 pf_macs[PF_MACNUM_MAX];
0397     u64 vf_macs[VF_MACNUM_MAX];
0398     u64 sclk;
0399     u64 rclk;
0400     u64 mcam_addr;
0401     u64 mcam_sz;
0402     u64 msixtr_base;
0403     u32 ptp_ext_clk_rate;
0404     u32 ptp_ext_tstamp;
0405 #define FWDATA_RESERVED_MEM 1022
0406     u64 reserved[FWDATA_RESERVED_MEM];
0407 #define CGX_MAX         5
0408 #define CGX_LMACS_MAX   4
0409     struct cgx_lmac_fwdata_s cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
0410     /* Do not add new fields below this line */
0411 };
0412 
0413 struct ptp;
0414 
0415 /* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
0416  * source where it came from.
0417  */
0418 struct npc_kpu_profile_adapter {
0419     const char          *name;
0420     u64             version;
0421     const struct npc_lt_def_cfg *lt_def;
0422     const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
0423     const struct npc_kpu_profile    *kpu; /* array[kpus] */
0424     struct npc_mcam_kex     *mkex;
0425     struct npc_mcam_kex_hash    *mkex_hash;
0426     bool                custom;
0427     size_t              pkinds;
0428     size_t              kpus;
0429 };
0430 
0431 #define RVU_SWITCH_LBK_CHAN 63
0432 
0433 struct rvu_switch {
0434     struct mutex switch_lock; /* Serialize flow installation */
0435     u32 used_entries;
0436     u16 *entry2pcifunc;
0437     u16 mode;
0438     u16 start_entry;
0439 };
0440 
0441 struct rvu {
0442     void __iomem        *afreg_base;
0443     void __iomem        *pfreg_base;
0444     struct pci_dev      *pdev;
0445     struct device       *dev;
0446     struct rvu_hwinfo       *hw;
0447     struct rvu_pfvf     *pf;
0448     struct rvu_pfvf     *hwvf;
0449     struct mutex        rsrc_lock; /* Serialize resource alloc/free */
0450     int         vfs; /* Number of VFs attached to RVU */
0451     int         nix_blkaddr[MAX_NIX_BLKS];
0452 
0453     /* Mbox */
0454     struct mbox_wq_info afpf_wq_info;
0455     struct mbox_wq_info afvf_wq_info;
0456 
0457     /* PF FLR */
0458     struct rvu_work     *flr_wrk;
0459     struct workqueue_struct *flr_wq;
0460     struct mutex        flr_lock; /* Serialize FLRs */
0461 
0462     /* MSI-X */
0463     u16         num_vec;
0464     char            *irq_name;
0465     bool            *irq_allocated;
0466     dma_addr_t      msix_base_iova;
0467     u64         msixtr_base_phy; /* Register reset value */
0468 
0469     /* CGX */
0470 #define PF_CGXMAP_BASE      1 /* PF 0 is reserved for RVU PF */
0471     u16         cgx_mapped_vfs; /* maximum CGX mapped VFs */
0472     u8          cgx_mapped_pfs;
0473     u8          cgx_cnt_max;     /* CGX port count max */
0474     u8          *pf2cgxlmac_map; /* pf to cgx_lmac map */
0475     u16         *cgxlmac2pf_map; /* bitmap of mapped pfs for
0476                           * every cgx lmac port
0477                           */
0478     unsigned long       pf_notify_bmap; /* Flags for PF notification */
0479     void            **cgx_idmap; /* cgx id to cgx data map table */
0480     struct          work_struct cgx_evh_work;
0481     struct          workqueue_struct *cgx_evh_wq;
0482     spinlock_t      cgx_evq_lock; /* cgx event queue lock */
0483     struct list_head    cgx_evq_head; /* cgx event queue head */
0484     struct mutex        cgx_cfg_lock; /* serialize cgx configuration */
0485 
0486     char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
0487     char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
0488 
0489     /* Firmware data */
0490     struct rvu_fwdata   *fwdata;
0491     void            *kpu_fwdata;
0492     size_t          kpu_fwdata_sz;
0493     void __iomem        *kpu_prfl_addr;
0494 
0495     /* NPC KPU data */
0496     struct npc_kpu_profile_adapter kpu;
0497 
0498     struct ptp      *ptp;
0499 
0500 #ifdef CONFIG_DEBUG_FS
0501     struct rvu_debugfs  rvu_dbg;
0502 #endif
0503     struct rvu_devlink  *rvu_dl;
0504 
0505     /* RVU switch implementation over NPC with DMAC rules */
0506     struct rvu_switch   rswitch;
0507 };
0508 
0509 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
0510 {
0511     writeq(val, rvu->afreg_base + ((block << 28) | offset));
0512 }
0513 
0514 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
0515 {
0516     return readq(rvu->afreg_base + ((block << 28) | offset));
0517 }
0518 
0519 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
0520 {
0521     writeq(val, rvu->pfreg_base + offset);
0522 }
0523 
0524 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
0525 {
0526     return readq(rvu->pfreg_base + offset);
0527 }
0528 
0529 /* Silicon revisions */
0530 static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
0531 {
0532     struct pci_dev *pdev = rvu->pdev;
0533     /* 96XX A0/B0, 95XX A0/A1/B0 chips */
0534     return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
0535         (pdev->revision == 0x10) || (pdev->revision == 0x11) ||
0536         (pdev->revision == 0x14));
0537 }
0538 
0539 static inline bool is_rvu_96xx_A0(struct rvu *rvu)
0540 {
0541     struct pci_dev *pdev = rvu->pdev;
0542 
0543     return (pdev->revision == 0x00);
0544 }
0545 
0546 static inline bool is_rvu_96xx_B0(struct rvu *rvu)
0547 {
0548     struct pci_dev *pdev = rvu->pdev;
0549 
0550     return (pdev->revision == 0x00) || (pdev->revision == 0x01);
0551 }
0552 
0553 static inline bool is_rvu_95xx_A0(struct rvu *rvu)
0554 {
0555     struct pci_dev *pdev = rvu->pdev;
0556 
0557     return (pdev->revision == 0x10) || (pdev->revision == 0x11);
0558 }
0559 
0560 /* REVID for PCIe devices.
0561  * Bits 0..1: minor pass, bit 3..2: major pass
0562  * bits 7..4: midr id
0563  */
0564 #define PCI_REVISION_ID_96XX        0x00
0565 #define PCI_REVISION_ID_95XX        0x10
0566 #define PCI_REVISION_ID_95XXN       0x20
0567 #define PCI_REVISION_ID_98XX        0x30
0568 #define PCI_REVISION_ID_95XXMM      0x40
0569 #define PCI_REVISION_ID_95XXO       0xE0
0570 
0571 static inline bool is_rvu_otx2(struct rvu *rvu)
0572 {
0573     struct pci_dev *pdev = rvu->pdev;
0574 
0575     u8 midr = pdev->revision & 0xF0;
0576 
0577     return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
0578         midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
0579         midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
0580 }
0581 
0582 static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
0583 {
0584     u64 npc_const3;
0585 
0586     npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
0587     if (!(npc_const3 & BIT_ULL(62)))
0588         return false;
0589 
0590     return true;
0591 }
0592 
0593 static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
0594                    u8 lmacid, u8 chan)
0595 {
0596     u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
0597     u16 cgx_chans = nix_const & 0xFFULL;
0598     struct rvu_hwinfo *hw = rvu->hw;
0599 
0600     if (!hw->cap.programmable_chans)
0601         return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
0602 
0603     return rvu->hw->cgx_chan_base +
0604         (cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
0605 }
0606 
0607 static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
0608                    u8 chan)
0609 {
0610     u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
0611     u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
0612     struct rvu_hwinfo *hw = rvu->hw;
0613 
0614     if (!hw->cap.programmable_chans)
0615         return NIX_CHAN_LBK_CHX(lbkid, chan);
0616 
0617     return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
0618 }
0619 
0620 static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
0621 {
0622     struct rvu_hwinfo *hw = rvu->hw;
0623 
0624     if (!hw->cap.programmable_chans)
0625         return NIX_CHAN_SDP_CHX(chan);
0626 
0627     return hw->sdp_chan_base + chan;
0628 }
0629 
0630 static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
0631 {
0632     return rvu->hw->cpt_chan_base + chan;
0633 }
0634 
0635 /* Function Prototypes
0636  * RVU
0637  */
0638 static inline bool is_afvf(u16 pcifunc)
0639 {
0640     return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
0641 }
0642 
0643 static inline bool is_vf(u16 pcifunc)
0644 {
0645     return !!(pcifunc & RVU_PFVF_FUNC_MASK);
0646 }
0647 
0648 /* check if PF_FUNC is AF */
0649 static inline bool is_pffunc_af(u16 pcifunc)
0650 {
0651     return !pcifunc;
0652 }
0653 
0654 static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
0655 {
0656     return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
0657         (rvu->fwdata->version == RVU_FWDATA_VERSION);
0658 }
0659 
0660 int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
0661 void rvu_free_bitmap(struct rsrc_bmap *rsrc);
0662 int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
0663 void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
0664 bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
0665 int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
0666 int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
0667 bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
0668 u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
0669 int rvu_get_pf(u16 pcifunc);
0670 struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
0671 void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
0672 bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
0673 bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
0674 int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
0675 int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
0676 int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
0677 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
0678 int rvu_get_num_lbk_chans(void);
0679 int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
0680                   u16 global_slot, u16 *slot_in_block);
0681 
0682 /* RVU HW reg validation */
0683 enum regmap_block {
0684     TXSCHQ_HWREGMAP = 0,
0685     MAX_HWREGMAP,
0686 };
0687 
0688 bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
0689 
0690 /* NPA/NIX AQ APIs */
0691 int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
0692          int qsize, int inst_size, int res_size);
0693 void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
0694 
0695 /* SDP APIs */
0696 int rvu_sdp_init(struct rvu *rvu);
0697 bool is_sdp_pfvf(u16 pcifunc);
0698 bool is_sdp_pf(u16 pcifunc);
0699 bool is_sdp_vf(u16 pcifunc);
0700 
0701 /* CGX APIs */
0702 static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
0703 {
0704     return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
0705         !is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
0706 }
0707 
0708 static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
0709 {
0710     *cgx_id = (map >> 4) & 0xF;
0711     *lmac_id = (map & 0xF);
0712 }
0713 
0714 static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
0715 {
0716     return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
0717         is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
0718 }
0719 
0720 #define M(_name, _id, fn_name, req, rsp)                \
0721 int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
0722 MBOX_MESSAGES
0723 #undef M
0724 
0725 int rvu_cgx_init(struct rvu *rvu);
0726 int rvu_cgx_exit(struct rvu *rvu);
0727 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
0728 int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
0729 void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
0730 int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
0731 int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
0732                int rxtxflag, u64 *stat);
0733 void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
0734 
0735 /* NPA APIs */
0736 int rvu_npa_init(struct rvu *rvu);
0737 void rvu_npa_freemem(struct rvu *rvu);
0738 void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
0739 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
0740             struct npa_aq_enq_rsp *rsp);
0741 
0742 /* NIX APIs */
0743 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
0744 int rvu_nix_init(struct rvu *rvu);
0745 int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
0746                 int blkaddr, u32 cfg);
0747 void rvu_nix_freemem(struct rvu *rvu);
0748 int rvu_get_nixlf_count(struct rvu *rvu);
0749 void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
0750 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
0751 int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
0752             struct nix_mce_list *mce_list,
0753             int mce_idx, int mcam_index, bool add);
0754 void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
0755               struct nix_mce_list **mce_list, int *mce_idx);
0756 struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
0757 int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
0758 void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
0759 int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
0760             struct nix_hw **nix_hw, int *blkaddr);
0761 int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
0762                  u16 rq_idx, u16 match_id);
0763 int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
0764             struct nix_cn10k_aq_enq_req *aq_req,
0765             struct nix_cn10k_aq_enq_rsp *aq_rsp,
0766             u16 pcifunc, u8 ctype, u32 qidx);
0767 int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
0768 u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
0769 u32 convert_bytes_to_dwrr_mtu(u32 bytes);
0770 
0771 /* NPC APIs */
0772 void rvu_npc_freemem(struct rvu *rvu);
0773 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
0774 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
0775 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
0776 void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
0777                  int nixlf, u64 chan, u8 *mac_addr);
0778 void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
0779                    int nixlf, u64 chan, u8 chan_cnt);
0780 void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
0781                   bool enable);
0782 void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
0783                        int nixlf, u64 chan);
0784 void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
0785                 bool enable);
0786 void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
0787                     u64 chan);
0788 void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
0789                    bool enable);
0790 
0791 void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
0792                   int nixlf, int type, bool enable);
0793 void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
0794 bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
0795 void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
0796 void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
0797 void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
0798 void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
0799                     int group, int alg_idx, int mcam_index);
0800 
0801 void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
0802                        int blkaddr, int *alloc_cnt,
0803                        int *enable_cnt);
0804 void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
0805                      int blkaddr, int *alloc_cnt,
0806                      int *enable_cnt);
0807 bool is_npc_intf_tx(u8 intf);
0808 bool is_npc_intf_rx(u8 intf);
0809 bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
0810 int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
0811 int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
0812 const char *npc_get_field_name(u8 hdr);
0813 int npc_get_bank(struct npc_mcam *mcam, int index);
0814 void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
0815 void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
0816 void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
0817                int blkaddr, int index, bool enable);
0818 void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
0819              int blkaddr, u16 src, struct mcam_entry *entry,
0820              u8 *intf, u8 *ena);
0821 bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
0822 bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
0823 u32  rvu_cgx_get_fifolen(struct rvu *rvu);
0824 void *rvu_first_cgx_pdata(struct rvu *rvu);
0825 int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
0826 int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
0827 int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
0828                    u16 pfc_en);
0829 int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
0830 u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
0831 int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
0832                  int type);
0833 bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
0834                int index);
0835 int rvu_npc_init(struct rvu *rvu);
0836 int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
0837                    u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
0838                    u64 bcast_mcast_val, u64 bcast_mcast_mask);
0839 void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
0840 
0841 /* CPT APIs */
0842 int rvu_cpt_register_interrupts(struct rvu *rvu);
0843 void rvu_cpt_unregister_interrupts(struct rvu *rvu);
0844 int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
0845             int slot);
0846 int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
0847 
0848 /* CN10K RVU */
0849 int rvu_set_channels_base(struct rvu *rvu);
0850 void rvu_program_channels(struct rvu *rvu);
0851 
0852 /* CN10K RVU - LMT*/
0853 void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
0854 
0855 #ifdef CONFIG_DEBUG_FS
0856 void rvu_dbg_init(struct rvu *rvu);
0857 void rvu_dbg_exit(struct rvu *rvu);
0858 #else
0859 static inline void rvu_dbg_init(struct rvu *rvu) {}
0860 static inline void rvu_dbg_exit(struct rvu *rvu) {}
0861 #endif
0862 
0863 /* RVU Switch */
0864 void rvu_switch_enable(struct rvu *rvu);
0865 void rvu_switch_disable(struct rvu *rvu);
0866 void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
0867 
0868 int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
0869                u64 pkind, u8 var_len_off, u8 var_len_off_mask,
0870                u8 shift_dir);
0871 #endif /* RVU_H */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!