octeontx2/af/npc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Marvell RVU Admin Function driver
0003  *
0004  * Copyright (C) 2018 Marvell.
0005  *
0006  */
0007
0008 #ifndef NPC_H
0009 #define NPC_H
0010
0011 #define NPC_KEX_CHAN_MASK   0xFFFULL
0012
0013 #define SET_KEX_LD(intf, lid, ltype, ld, cfg)   \
0014     rvu_write64(rvu, blkaddr,   \
0015             NPC_AF_INTFX_LIDX_LTX_LDX_CFG(intf, lid, ltype, ld), cfg)
0016
0017 #define SET_KEX_LDFLAGS(intf, ld, flags, cfg)   \
0018     rvu_write64(rvu, blkaddr,   \
0019             NPC_AF_INTFX_LDATAX_FLAGSX_CFG(intf, ld, flags), cfg)
0020
0021 enum NPC_LID_E {
0022     NPC_LID_LA = 0,
0023     NPC_LID_LB,
0024     NPC_LID_LC,
0025     NPC_LID_LD,
0026     NPC_LID_LE,
0027     NPC_LID_LF,
0028     NPC_LID_LG,
0029     NPC_LID_LH,
0030 };
0031
0032 #define NPC_LT_NA 0
0033
0034 enum npc_kpu_la_ltype {
0035     NPC_LT_LA_8023 = 1,
0036     NPC_LT_LA_ETHER,
0037     NPC_LT_LA_IH_NIX_ETHER,
0038     NPC_LT_LA_HIGIG2_ETHER = 7,
0039     NPC_LT_LA_IH_NIX_HIGIG2_ETHER,
0040     NPC_LT_LA_CUSTOM_L2_90B_ETHER,
0041     NPC_LT_LA_CPT_HDR,
0042     NPC_LT_LA_CUSTOM_L2_24B_ETHER,
0043     NPC_LT_LA_CUSTOM_PRE_L2_ETHER,
0044     NPC_LT_LA_CUSTOM0 = 0xE,
0045     NPC_LT_LA_CUSTOM1 = 0xF,
0046 };
0047
0048 enum npc_kpu_lb_ltype {
0049     NPC_LT_LB_ETAG = 1,
0050     NPC_LT_LB_CTAG,
0051     NPC_LT_LB_STAG_QINQ,
0052     NPC_LT_LB_BTAG,
0053     NPC_LT_LB_PPPOE,
0054     NPC_LT_LB_DSA,
0055     NPC_LT_LB_DSA_VLAN,
0056     NPC_LT_LB_EDSA,
0057     NPC_LT_LB_EDSA_VLAN,
0058     NPC_LT_LB_EXDSA,
0059     NPC_LT_LB_EXDSA_VLAN,
0060     NPC_LT_LB_FDSA,
0061     NPC_LT_LB_VLAN_EXDSA,
0062     NPC_LT_LB_CUSTOM0 = 0xE,
0063     NPC_LT_LB_CUSTOM1 = 0xF,
0064 };
0065
0066 enum npc_kpu_lc_ltype {
0067     NPC_LT_LC_IP = 1,
0068     NPC_LT_LC_IP_OPT,
0069     NPC_LT_LC_IP6,
0070     NPC_LT_LC_IP6_EXT,
0071     NPC_LT_LC_ARP,
0072     NPC_LT_LC_RARP,
0073     NPC_LT_LC_MPLS,
0074     NPC_LT_LC_NSH,
0075     NPC_LT_LC_PTP,
0076     NPC_LT_LC_FCOE,
0077     NPC_LT_LC_NGIO,
0078     NPC_LT_LC_CUSTOM0 = 0xE,
0079     NPC_LT_LC_CUSTOM1 = 0xF,
0080 };
0081
0082 /* Don't modify Ltypes upto SCTP, otherwise it will
0083  * effect flow tag calculation and thus RSS.
0084  */
0085 enum npc_kpu_ld_ltype {
0086     NPC_LT_LD_TCP = 1,
0087     NPC_LT_LD_UDP,
0088     NPC_LT_LD_ICMP,
0089     NPC_LT_LD_SCTP,
0090     NPC_LT_LD_ICMP6,
0091     NPC_LT_LD_CUSTOM0,
0092     NPC_LT_LD_CUSTOM1,
0093     NPC_LT_LD_IGMP = 8,
0094     NPC_LT_LD_AH,
0095     NPC_LT_LD_GRE,
0096     NPC_LT_LD_NVGRE,
0097     NPC_LT_LD_NSH,
0098     NPC_LT_LD_TU_MPLS_IN_NSH,
0099     NPC_LT_LD_TU_MPLS_IN_IP,
0100 };
0101
0102 enum npc_kpu_le_ltype {
0103     NPC_LT_LE_VXLAN = 1,
0104     NPC_LT_LE_GENEVE,
0105     NPC_LT_LE_ESP,
0106     NPC_LT_LE_GTPU = 4,
0107     NPC_LT_LE_VXLANGPE,
0108     NPC_LT_LE_GTPC,
0109     NPC_LT_LE_NSH,
0110     NPC_LT_LE_TU_MPLS_IN_GRE,
0111     NPC_LT_LE_TU_NSH_IN_GRE,
0112     NPC_LT_LE_TU_MPLS_IN_UDP,
0113     NPC_LT_LE_CUSTOM0 = 0xE,
0114     NPC_LT_LE_CUSTOM1 = 0xF,
0115 };
0116
0117 enum npc_kpu_lf_ltype {
0118     NPC_LT_LF_TU_ETHER = 1,
0119     NPC_LT_LF_TU_PPP,
0120     NPC_LT_LF_TU_MPLS_IN_VXLANGPE,
0121     NPC_LT_LF_TU_NSH_IN_VXLANGPE,
0122     NPC_LT_LF_TU_MPLS_IN_NSH,
0123     NPC_LT_LF_TU_3RD_NSH,
0124     NPC_LT_LF_CUSTOM0 = 0xE,
0125     NPC_LT_LF_CUSTOM1 = 0xF,
0126 };
0127
0128 enum npc_kpu_lg_ltype {
0129     NPC_LT_LG_TU_IP = 1,
0130     NPC_LT_LG_TU_IP6,
0131     NPC_LT_LG_TU_ARP,
0132     NPC_LT_LG_TU_ETHER_IN_NSH,
0133     NPC_LT_LG_CUSTOM0 = 0xE,
0134     NPC_LT_LG_CUSTOM1 = 0xF,
0135 };
0136
0137 /* Don't modify Ltypes upto SCTP, otherwise it will
0138  * effect flow tag calculation and thus RSS.
0139  */
0140 enum npc_kpu_lh_ltype {
0141     NPC_LT_LH_TU_TCP = 1,
0142     NPC_LT_LH_TU_UDP,
0143     NPC_LT_LH_TU_ICMP,
0144     NPC_LT_LH_TU_SCTP,
0145     NPC_LT_LH_TU_ICMP6,
0146     NPC_LT_LH_TU_IGMP = 8,
0147     NPC_LT_LH_TU_ESP,
0148     NPC_LT_LH_TU_AH,
0149     NPC_LT_LH_CUSTOM0 = 0xE,
0150     NPC_LT_LH_CUSTOM1 = 0xF,
0151 };
0152
0153 /* NPC port kind defines how the incoming or outgoing packets
0154  * are processed. NPC accepts packets from up to 64 pkinds.
0155  * Software assigns pkind for each incoming port such as CGX
0156  * Ethernet interfaces, LBK interfaces, etc.
0157  */
0158 #define NPC_UNRESERVED_PKIND_COUNT NPC_RX_CUSTOM_PRE_L2_PKIND
0159
0160 enum npc_pkind_type {
0161     NPC_RX_LBK_PKIND = 0ULL,
0162     NPC_RX_CUSTOM_PRE_L2_PKIND = 55ULL,
0163     NPC_RX_VLAN_EXDSA_PKIND = 56ULL,
0164     NPC_RX_CHLEN24B_PKIND = 57ULL,
0165     NPC_RX_CPT_HDR_PKIND,
0166     NPC_RX_CHLEN90B_PKIND,
0167     NPC_TX_HIGIG_PKIND,
0168     NPC_RX_HIGIG_PKIND,
0169     NPC_RX_EDSA_PKIND,
0170     NPC_TX_DEF_PKIND,   /* NIX-TX PKIND */
0171 };
0172
0173 enum npc_interface_type {
0174     NPC_INTF_MODE_DEF,
0175 };
0176
0177 /* list of known and supported fields in packet header and
0178  * fields present in key structure.
0179  */
0180 enum key_fields {
0181     NPC_DMAC,
0182     NPC_SMAC,
0183     NPC_ETYPE,
0184     NPC_VLAN_ETYPE_CTAG, /* 0x8100 */
0185     NPC_VLAN_ETYPE_STAG, /* 0x88A8 */
0186     NPC_OUTER_VID,
0187     NPC_TOS,
0188     NPC_SIP_IPV4,
0189     NPC_DIP_IPV4,
0190     NPC_SIP_IPV6,
0191     NPC_DIP_IPV6,
0192     NPC_IPPROTO_TCP,
0193     NPC_IPPROTO_UDP,
0194     NPC_IPPROTO_SCTP,
0195     NPC_IPPROTO_AH,
0196     NPC_IPPROTO_ESP,
0197     NPC_IPPROTO_ICMP,
0198     NPC_IPPROTO_ICMP6,
0199     NPC_SPORT_TCP,
0200     NPC_DPORT_TCP,
0201     NPC_SPORT_UDP,
0202     NPC_DPORT_UDP,
0203     NPC_SPORT_SCTP,
0204     NPC_DPORT_SCTP,
0205     NPC_HEADER_FIELDS_MAX,
0206     NPC_CHAN = NPC_HEADER_FIELDS_MAX, /* Valid when Rx */
0207     NPC_PF_FUNC, /* Valid when Tx */
0208     NPC_ERRLEV,
0209     NPC_ERRCODE,
0210     NPC_LXMB,
0211     NPC_EXACT_RESULT,
0212     NPC_LA,
0213     NPC_LB,
0214     NPC_LC,
0215     NPC_LD,
0216     NPC_LE,
0217     NPC_LF,
0218     NPC_LG,
0219     NPC_LH,
0220     /* Ethertype for untagged frame */
0221     NPC_ETYPE_ETHER,
0222     /* Ethertype for single tagged frame */
0223     NPC_ETYPE_TAG1,
0224     /* Ethertype for double tagged frame */
0225     NPC_ETYPE_TAG2,
0226     /* outer vlan tci for single tagged frame */
0227     NPC_VLAN_TAG1,
0228     /* outer vlan tci for double tagged frame */
0229     NPC_VLAN_TAG2,
0230     /* other header fields programmed to extract but not of our interest */
0231     NPC_UNKNOWN,
0232     NPC_KEY_FIELDS_MAX,
0233 };
0234
0235 struct npc_kpu_profile_cam {
0236     u8 state;
0237     u8 state_mask;
0238     u16 dp0;
0239     u16 dp0_mask;
0240     u16 dp1;
0241     u16 dp1_mask;
0242     u16 dp2;
0243     u16 dp2_mask;
0244 } __packed;
0245
0246 struct npc_kpu_profile_action {
0247     u8 errlev;
0248     u8 errcode;
0249     u8 dp0_offset;
0250     u8 dp1_offset;
0251     u8 dp2_offset;
0252     u8 bypass_count;
0253     u8 parse_done;
0254     u8 next_state;
0255     u8 ptr_advance;
0256     u8 cap_ena;
0257     u8 lid;
0258     u8 ltype;
0259     u8 flags;
0260     u8 offset;
0261     u8 mask;
0262     u8 right;
0263     u8 shift;
0264 } __packed;
0265
0266 struct npc_kpu_profile {
0267     int cam_entries;
0268     int action_entries;
0269     struct npc_kpu_profile_cam *cam;
0270     struct npc_kpu_profile_action *action;
0271 };
0272
0273 /* NPC KPU register formats */
0274 struct npc_kpu_cam {
0275 #if defined(__BIG_ENDIAN_BITFIELD)
0276     u64 rsvd_63_56     : 8;
0277     u64 state          : 8;
0278     u64 dp2_data       : 16;
0279     u64 dp1_data       : 16;
0280     u64 dp0_data       : 16;
0281 #else
0282     u64 dp0_data       : 16;
0283     u64 dp1_data       : 16;
0284     u64 dp2_data       : 16;
0285     u64 state          : 8;
0286     u64 rsvd_63_56     : 8;
0287 #endif
0288 };
0289
0290 struct npc_kpu_action0 {
0291 #if defined(__BIG_ENDIAN_BITFIELD)
0292     u64 rsvd_63_57     : 7;
0293     u64 byp_count      : 3;
0294     u64 capture_ena    : 1;
0295     u64 parse_done     : 1;
0296     u64 next_state     : 8;
0297     u64 rsvd_43        : 1;
0298     u64 capture_lid    : 3;
0299     u64 capture_ltype  : 4;
0300     u64 capture_flags  : 8;
0301     u64 ptr_advance    : 8;
0302     u64 var_len_offset : 8;
0303     u64 var_len_mask   : 8;
0304     u64 var_len_right  : 1;
0305     u64 var_len_shift  : 3;
0306 #else
0307     u64 var_len_shift  : 3;
0308     u64 var_len_right  : 1;
0309     u64 var_len_mask   : 8;
0310     u64 var_len_offset : 8;
0311     u64 ptr_advance    : 8;
0312     u64 capture_flags  : 8;
0313     u64 capture_ltype  : 4;
0314     u64 capture_lid    : 3;
0315     u64 rsvd_43        : 1;
0316     u64 next_state     : 8;
0317     u64 parse_done     : 1;
0318     u64 capture_ena    : 1;
0319     u64 byp_count      : 3;
0320     u64 rsvd_63_57     : 7;
0321 #endif
0322 };
0323
0324 struct npc_kpu_action1 {
0325 #if defined(__BIG_ENDIAN_BITFIELD)
0326     u64 rsvd_63_36     : 28;
0327     u64 errlev         : 4;
0328     u64 errcode        : 8;
0329     u64 dp2_offset     : 8;
0330     u64 dp1_offset     : 8;
0331     u64 dp0_offset     : 8;
0332 #else
0333     u64 dp0_offset     : 8;
0334     u64 dp1_offset     : 8;
0335     u64 dp2_offset     : 8;
0336     u64 errcode        : 8;
0337     u64 errlev         : 4;
0338     u64 rsvd_63_36     : 28;
0339 #endif
0340 };
0341
0342 struct npc_kpu_pkind_cpi_def {
0343 #if defined(__BIG_ENDIAN_BITFIELD)
0344     u64 ena            : 1;
0345     u64 rsvd_62_59     : 4;
0346     u64 lid            : 3;
0347     u64 ltype_match    : 4;
0348     u64 ltype_mask     : 4;
0349     u64 flags_match    : 8;
0350     u64 flags_mask     : 8;
0351     u64 add_offset     : 8;
0352     u64 add_mask       : 8;
0353     u64 rsvd_15        : 1;
0354     u64 add_shift      : 3;
0355     u64 rsvd_11_10     : 2;
0356     u64 cpi_base       : 10;
0357 #else
0358     u64 cpi_base       : 10;
0359     u64 rsvd_11_10     : 2;
0360     u64 add_shift      : 3;
0361     u64 rsvd_15        : 1;
0362     u64 add_mask       : 8;
0363     u64 add_offset     : 8;
0364     u64 flags_mask     : 8;
0365     u64 flags_match    : 8;
0366     u64 ltype_mask     : 4;
0367     u64 ltype_match    : 4;
0368     u64 lid            : 3;
0369     u64 rsvd_62_59     : 4;
0370     u64 ena            : 1;
0371 #endif
0372 };
0373
0374 struct nix_rx_action {
0375 #if defined(__BIG_ENDIAN_BITFIELD)
0376     u64 rsvd_63_61  :3;
0377     u64 flow_key_alg    :5;
0378     u64 match_id    :16;
0379     u64 index       :20;
0380     u64 pf_func     :16;
0381     u64 op      :4;
0382 #else
0383     u64 op      :4;
0384     u64 pf_func     :16;
0385     u64 index       :20;
0386     u64 match_id    :16;
0387     u64 flow_key_alg    :5;
0388     u64 rsvd_63_61  :3;
0389 #endif
0390 };
0391
0392 /* NPC_AF_INTFX_KEX_CFG field masks */
0393 #define NPC_EXACT_NIBBLE_START      40
0394 #define NPC_EXACT_NIBBLE_END        43
0395 #define NPC_EXACT_NIBBLE        GENMASK_ULL(43, 40)
0396
0397 /* NPC_EXACT_KEX_S nibble definitions for each field */
0398 #define NPC_EXACT_NIBBLE_HIT        BIT_ULL(40)
0399 #define NPC_EXACT_NIBBLE_OPC        BIT_ULL(40)
0400 #define NPC_EXACT_NIBBLE_WAY        BIT_ULL(40)
0401 #define NPC_EXACT_NIBBLE_INDEX      GENMASK_ULL(43, 41)
0402
0403 #define NPC_EXACT_RESULT_HIT        BIT_ULL(0)
0404 #define NPC_EXACT_RESULT_OPC        GENMASK_ULL(2, 1)
0405 #define NPC_EXACT_RESULT_WAY        GENMASK_ULL(4, 3)
0406 #define NPC_EXACT_RESULT_IDX        GENMASK_ULL(15, 5)
0407
0408 /* NPC_AF_INTFX_KEX_CFG field masks */
0409 #define NPC_PARSE_NIBBLE        GENMASK_ULL(30, 0)
0410
0411 /* NPC_PARSE_KEX_S nibble definitions for each field */
0412 #define NPC_PARSE_NIBBLE_CHAN       GENMASK_ULL(2, 0)
0413 #define NPC_PARSE_NIBBLE_ERRLEV     BIT_ULL(3)
0414 #define NPC_PARSE_NIBBLE_ERRCODE    GENMASK_ULL(5, 4)
0415 #define NPC_PARSE_NIBBLE_L2L3_BCAST BIT_ULL(6)
0416 #define NPC_PARSE_NIBBLE_LA_FLAGS   GENMASK_ULL(8, 7)
0417 #define NPC_PARSE_NIBBLE_LA_LTYPE   BIT_ULL(9)
0418 #define NPC_PARSE_NIBBLE_LB_FLAGS   GENMASK_ULL(11, 10)
0419 #define NPC_PARSE_NIBBLE_LB_LTYPE   BIT_ULL(12)
0420 #define NPC_PARSE_NIBBLE_LC_FLAGS   GENMASK_ULL(14, 13)
0421 #define NPC_PARSE_NIBBLE_LC_LTYPE   BIT_ULL(15)
0422 #define NPC_PARSE_NIBBLE_LD_FLAGS   GENMASK_ULL(17, 16)
0423 #define NPC_PARSE_NIBBLE_LD_LTYPE   BIT_ULL(18)
0424 #define NPC_PARSE_NIBBLE_LE_FLAGS   GENMASK_ULL(20, 19)
0425 #define NPC_PARSE_NIBBLE_LE_LTYPE   BIT_ULL(21)
0426 #define NPC_PARSE_NIBBLE_LF_FLAGS   GENMASK_ULL(23, 22)
0427 #define NPC_PARSE_NIBBLE_LF_LTYPE   BIT_ULL(24)
0428 #define NPC_PARSE_NIBBLE_LG_FLAGS   GENMASK_ULL(26, 25)
0429 #define NPC_PARSE_NIBBLE_LG_LTYPE   BIT_ULL(27)
0430 #define NPC_PARSE_NIBBLE_LH_FLAGS   GENMASK_ULL(29, 28)
0431 #define NPC_PARSE_NIBBLE_LH_LTYPE   BIT_ULL(30)
0432
0433 struct nix_tx_action {
0434 #if defined(__BIG_ENDIAN_BITFIELD)
0435     u64 rsvd_63_48  :16;
0436     u64 match_id    :16;
0437     u64 index       :20;
0438     u64 rsvd_11_8   :8;
0439     u64 op      :4;
0440 #else
0441     u64 op      :4;
0442     u64 rsvd_11_8   :8;
0443     u64 index       :20;
0444     u64 match_id    :16;
0445     u64 rsvd_63_48  :16;
0446 #endif
0447 };
0448
0449 /* NIX Receive Vtag Action Structure */
0450 #define RX_VTAG0_VALID_BIT      BIT_ULL(15)
0451 #define RX_VTAG0_TYPE_MASK      GENMASK_ULL(14, 12)
0452 #define RX_VTAG0_LID_MASK       GENMASK_ULL(10, 8)
0453 #define RX_VTAG0_RELPTR_MASK        GENMASK_ULL(7, 0)
0454 #define RX_VTAG1_VALID_BIT      BIT_ULL(47)
0455 #define RX_VTAG1_TYPE_MASK      GENMASK_ULL(46, 44)
0456 #define RX_VTAG1_LID_MASK       GENMASK_ULL(42, 40)
0457 #define RX_VTAG1_RELPTR_MASK        GENMASK_ULL(39, 32)
0458
0459 /* NIX Transmit Vtag Action Structure */
0460 #define TX_VTAG0_DEF_MASK       GENMASK_ULL(25, 16)
0461 #define TX_VTAG0_OP_MASK        GENMASK_ULL(13, 12)
0462 #define TX_VTAG0_LID_MASK       GENMASK_ULL(10, 8)
0463 #define TX_VTAG0_RELPTR_MASK        GENMASK_ULL(7, 0)
0464 #define TX_VTAG1_DEF_MASK       GENMASK_ULL(57, 48)
0465 #define TX_VTAG1_OP_MASK        GENMASK_ULL(45, 44)
0466 #define TX_VTAG1_LID_MASK       GENMASK_ULL(42, 40)
0467 #define TX_VTAG1_RELPTR_MASK        GENMASK_ULL(39, 32)
0468
0469 /* NPC MCAM reserved entry index per nixlf */
0470 #define NIXLF_UCAST_ENTRY   0
0471 #define NIXLF_BCAST_ENTRY   1
0472 #define NIXLF_ALLMULTI_ENTRY    2
0473 #define NIXLF_PROMISC_ENTRY 3
0474
0475 struct npc_coalesced_kpu_prfl {
0476 #define NPC_SIGN    0x00666f727063706e
0477 #define NPC_PRFL_NAME   "npc_prfls_array"
0478 #define NPC_NAME_LEN    32
0479     __le64 signature; /* "npcprof\0" (8 bytes/ASCII characters) */
0480     u8 name[NPC_NAME_LEN]; /* KPU Profile name */
0481     u64 version; /* KPU firmware/profile version */
0482     u8 num_prfl; /* No of NPC profiles. */
0483     u16 prfl_sz[];
0484 };
0485
0486 struct npc_mcam_kex {
0487     /* MKEX Profle Header */
0488     u64 mkex_sign; /* "mcam-kex-profile" (8 bytes/ASCII characters) */
0489     u8 name[MKEX_NAME_LEN];   /* MKEX Profile name */
0490     u64 cpu_model;   /* Format as profiled by CPU hardware */
0491     u64 kpu_version; /* KPU firmware/profile version */
0492     u64 reserved; /* Reserved for extension */
0493
0494     /* MKEX Profle Data */
0495     u64 keyx_cfg[NPC_MAX_INTF]; /* NPC_AF_INTF(0..1)_KEX_CFG */
0496     /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
0497     u64 kex_ld_flags[NPC_MAX_LD];
0498     /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
0499     u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
0500     /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
0501     u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
0502 } __packed;
0503
0504 struct npc_kpu_fwdata {
0505     int entries;
0506     /* What follows is:
0507      * struct npc_kpu_profile_cam[entries];
0508      * struct npc_kpu_profile_action[entries];
0509      */
0510     u8  data[];
0511 } __packed;
0512
0513 struct npc_lt_def {
0514     u8  ltype_mask;
0515     u8  ltype_match;
0516     u8  lid;
0517 };
0518
0519 struct npc_lt_def_ipsec {
0520     u8  ltype_mask;
0521     u8  ltype_match;
0522     u8  lid;
0523     u8  spi_offset;
0524     u8  spi_nz;
0525 };
0526
0527 struct npc_lt_def_apad {
0528     u8  ltype_mask;
0529     u8  ltype_match;
0530     u8  lid;
0531     u8  valid;
0532 } __packed;
0533
0534 struct npc_lt_def_color {
0535     u8  ltype_mask;
0536     u8  ltype_match;
0537     u8  lid;
0538     u8  noffset;
0539     u8  offset;
0540 } __packed;
0541
0542 struct npc_lt_def_et {
0543     u8  ltype_mask;
0544     u8  ltype_match;
0545     u8  lid;
0546     u8  valid;
0547     u8  offset;
0548 } __packed;
0549
0550 struct npc_lt_def_cfg {
0551     struct npc_lt_def   rx_ol2;
0552     struct npc_lt_def   rx_oip4;
0553     struct npc_lt_def   rx_iip4;
0554     struct npc_lt_def   rx_oip6;
0555     struct npc_lt_def   rx_iip6;
0556     struct npc_lt_def   rx_otcp;
0557     struct npc_lt_def   rx_itcp;
0558     struct npc_lt_def   rx_oudp;
0559     struct npc_lt_def   rx_iudp;
0560     struct npc_lt_def   rx_osctp;
0561     struct npc_lt_def   rx_isctp;
0562     struct npc_lt_def_ipsec rx_ipsec[2];
0563     struct npc_lt_def   pck_ol2;
0564     struct npc_lt_def   pck_oip4;
0565     struct npc_lt_def   pck_oip6;
0566     struct npc_lt_def   pck_iip4;
0567     struct npc_lt_def_apad  rx_apad0;
0568     struct npc_lt_def_apad  rx_apad1;
0569     struct npc_lt_def_color ovlan;
0570     struct npc_lt_def_color ivlan;
0571     struct npc_lt_def_color rx_gen0_color;
0572     struct npc_lt_def_color rx_gen1_color;
0573     struct npc_lt_def_et    rx_et[2];
0574 } __packed;
0575
0576 /* Loadable KPU profile firmware data */
0577 struct npc_kpu_profile_fwdata {
0578 #define KPU_SIGN    0x00666f727075706b
0579 #define KPU_NAME_LEN    32
0580 /** Maximum number of custom KPU entries supported by the built-in profile. */
0581 #define KPU_MAX_CST_ENT 6
0582     /* KPU Profle Header */
0583     __le64  signature; /* "kpuprof\0" (8 bytes/ASCII characters) */
0584     u8  name[KPU_NAME_LEN]; /* KPU Profile name */
0585     __le64  version; /* KPU profile version */
0586     u8  kpus;
0587     u8  reserved[7];
0588
0589     /* Default MKEX profile to be used with this KPU profile. May be
0590      * overridden with mkex_profile module parameter. Format is same as for
0591      * the MKEX profile to streamline processing.
0592      */
0593     struct npc_mcam_kex mkex;
0594     /* LTYPE values for specific HW offloaded protocols. */
0595     struct npc_lt_def_cfg   lt_def;
0596     /* Dynamically sized data:
0597      *  Custom KPU CAM and ACTION configuration entries.
0598      * struct npc_kpu_fwdata kpu[kpus];
0599      */
0600     u8  data[];
0601 } __packed;
0602
0603 struct rvu_npc_mcam_rule {
0604     struct flow_msg packet;
0605     struct flow_msg mask;
0606     u8 intf;
0607     union {
0608         struct nix_tx_action tx_action;
0609         struct nix_rx_action rx_action;
0610     };
0611     u64 vtag_action;
0612     struct list_head list;
0613     u64 features;
0614     u16 owner;
0615     u16 entry;
0616     u16 cntr;
0617     bool has_cntr;
0618     u8 default_rule;
0619     bool enable;
0620     bool vfvlan_cfg;
0621     u16 chan;
0622     u16 chan_mask;
0623 };
0624
0625 #endif /* NPC_H */