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OSCL-LXR
 
 

     

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Marvell RVU Admin Function driver
0003  *
0004  * Copyright (C) 2018 Marvell.
0005  *
0006  */
0007 
0008 #ifndef MBOX_H
0009 #define MBOX_H
0010 
0011 #include <linux/etherdevice.h>
0012 #include <linux/sizes.h>
0013 
0014 #include "rvu_struct.h"
0015 #include "common.h"
0016 
0017 #define MBOX_SIZE       SZ_64K
0018 
0019 /* AF/PF: PF initiated, PF/VF VF initiated */
0020 #define MBOX_DOWN_RX_START  0
0021 #define MBOX_DOWN_RX_SIZE   (46 * SZ_1K)
0022 #define MBOX_DOWN_TX_START  (MBOX_DOWN_RX_START + MBOX_DOWN_RX_SIZE)
0023 #define MBOX_DOWN_TX_SIZE   (16 * SZ_1K)
0024 /* AF/PF: AF initiated, PF/VF PF initiated */
0025 #define MBOX_UP_RX_START    (MBOX_DOWN_TX_START + MBOX_DOWN_TX_SIZE)
0026 #define MBOX_UP_RX_SIZE     SZ_1K
0027 #define MBOX_UP_TX_START    (MBOX_UP_RX_START + MBOX_UP_RX_SIZE)
0028 #define MBOX_UP_TX_SIZE     SZ_1K
0029 
0030 #if MBOX_UP_TX_SIZE + MBOX_UP_TX_START != MBOX_SIZE
0031 # error "incorrect mailbox area sizes"
0032 #endif
0033 
0034 #define INTR_MASK(pfvfs) ((pfvfs < 64) ? (BIT_ULL(pfvfs) - 1) : (~0ull))
0035 
0036 #define MBOX_RSP_TIMEOUT    6000 /* Time(ms) to wait for mbox response */
0037 
0038 #define MBOX_MSG_ALIGN      16  /* Align mbox msg start to 16bytes */
0039 
0040 /* Mailbox directions */
0041 #define MBOX_DIR_AFPF       0  /* AF replies to PF */
0042 #define MBOX_DIR_PFAF       1  /* PF sends messages to AF */
0043 #define MBOX_DIR_PFVF       2  /* PF replies to VF */
0044 #define MBOX_DIR_VFPF       3  /* VF sends messages to PF */
0045 #define MBOX_DIR_AFPF_UP    4  /* AF sends messages to PF */
0046 #define MBOX_DIR_PFAF_UP    5  /* PF replies to AF */
0047 #define MBOX_DIR_PFVF_UP    6  /* PF sends messages to VF */
0048 #define MBOX_DIR_VFPF_UP    7  /* VF replies to PF */
0049 
0050 struct otx2_mbox_dev {
0051     void        *mbase;   /* This dev's mbox region */
0052     void        *hwbase;
0053     spinlock_t  mbox_lock;
0054     u16         msg_size; /* Total msg size to be sent */
0055     u16         rsp_size; /* Total rsp size to be sure the reply is ok */
0056     u16         num_msgs; /* No of msgs sent or waiting for response */
0057     u16         msgs_acked; /* No of msgs for which response is received */
0058 };
0059 
0060 struct otx2_mbox {
0061     struct pci_dev *pdev;
0062     void   *hwbase;  /* Mbox region advertised by HW */
0063     void   *reg_base;/* CSR base for this dev */
0064     u64    trigger;  /* Trigger mbox notification */
0065     u16    tr_shift; /* Mbox trigger shift */
0066     u64    rx_start; /* Offset of Rx region in mbox memory */
0067     u64    tx_start; /* Offset of Tx region in mbox memory */
0068     u16    rx_size;  /* Size of Rx region */
0069     u16    tx_size;  /* Size of Tx region */
0070     u16    ndevs;    /* The number of peers */
0071     struct otx2_mbox_dev *dev;
0072 };
0073 
0074 /* Header which precedes all mbox messages */
0075 struct mbox_hdr {
0076     u64 msg_size;   /* Total msgs size embedded */
0077     u16  num_msgs;   /* No of msgs embedded */
0078 };
0079 
0080 /* Header which precedes every msg and is also part of it */
0081 struct mbox_msghdr {
0082     u16 pcifunc;     /* Who's sending this msg */
0083     u16 id;          /* Mbox message ID */
0084 #define OTX2_MBOX_REQ_SIG (0xdead)
0085 #define OTX2_MBOX_RSP_SIG (0xbeef)
0086     u16 sig;         /* Signature, for validating corrupted msgs */
0087 #define OTX2_MBOX_VERSION (0x000a)
0088     u16 ver;         /* Version of msg's structure for this ID */
0089     u16 next_msgoff; /* Offset of next msg within mailbox region */
0090     int rc;          /* Msg process'ed response code */
0091 };
0092 
0093 void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
0094 void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
0095 void otx2_mbox_destroy(struct otx2_mbox *mbox);
0096 int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
0097            struct pci_dev *pdev, void __force *reg_base,
0098            int direction, int ndevs);
0099 int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
0100                struct pci_dev *pdev, void __force *reg_base,
0101                int direction, int ndevs);
0102 void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
0103 int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
0104 int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
0105 struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
0106                         int size, int size_rsp);
0107 struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
0108                       struct mbox_msghdr *msg);
0109 int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
0110 int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
0111                u16 pcifunc, u16 id);
0112 bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
0113 const char *otx2_mbox_id2name(u16 id);
0114 static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
0115                               int devid, int size)
0116 {
0117     return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
0118 }
0119 
0120 /* Mailbox message types */
0121 #define MBOX_MSG_MASK               0xFFFF
0122 #define MBOX_MSG_INVALID            0xFFFE
0123 #define MBOX_MSG_MAX                0xFFFF
0124 
0125 #define MBOX_MESSAGES                           \
0126 /* Generic mbox IDs (range 0x000 - 0x1FF) */                \
0127 M(READY,        0x001, ready, msg_req, ready_msg_rsp)       \
0128 M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp)  \
0129 M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp)  \
0130 M(FREE_RSRC_CNT,    0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp)  \
0131 M(MSIX_OFFSET,      0x005, msix_offset, msg_req, msix_offset_rsp)   \
0132 M(VF_FLR,       0x006, vf_flr, msg_req, msg_rsp)        \
0133 M(PTP_OP,       0x007, ptp_op, ptp_req, ptp_rsp)        \
0134 M(GET_HW_CAP,       0x008, get_hw_cap, msg_req, get_hw_cap_rsp) \
0135 M(LMTST_TBL_SETUP,  0x00a, lmtst_tbl_setup, lmtst_tbl_setup_req,    \
0136                 msg_rsp)                \
0137 M(SET_VF_PERM,      0x00b, set_vf_perm, set_vf_perm, msg_rsp)   \
0138 /* CGX mbox IDs (range 0x200 - 0x3FF) */                \
0139 M(CGX_START_RXTX,   0x200, cgx_start_rxtx, msg_req, msg_rsp)    \
0140 M(CGX_STOP_RXTX,    0x201, cgx_stop_rxtx, msg_req, msg_rsp)     \
0141 M(CGX_STATS,        0x202, cgx_stats, msg_req, cgx_stats_rsp)   \
0142 M(CGX_MAC_ADDR_SET, 0x203, cgx_mac_addr_set, cgx_mac_addr_set_or_get,    \
0143                 cgx_mac_addr_set_or_get)        \
0144 M(CGX_MAC_ADDR_GET, 0x204, cgx_mac_addr_get, cgx_mac_addr_set_or_get,    \
0145                 cgx_mac_addr_set_or_get)        \
0146 M(CGX_PROMISC_ENABLE,   0x205, cgx_promisc_enable, msg_req, msg_rsp)    \
0147 M(CGX_PROMISC_DISABLE,  0x206, cgx_promisc_disable, msg_req, msg_rsp)   \
0148 M(CGX_START_LINKEVENTS, 0x207, cgx_start_linkevents, msg_req, msg_rsp)  \
0149 M(CGX_STOP_LINKEVENTS,  0x208, cgx_stop_linkevents, msg_req, msg_rsp)   \
0150 M(CGX_GET_LINKINFO, 0x209, cgx_get_linkinfo, msg_req, cgx_link_info_msg) \
0151 M(CGX_INTLBK_ENABLE,    0x20A, cgx_intlbk_enable, msg_req, msg_rsp) \
0152 M(CGX_INTLBK_DISABLE,   0x20B, cgx_intlbk_disable, msg_req, msg_rsp)    \
0153 M(CGX_PTP_RX_ENABLE,    0x20C, cgx_ptp_rx_enable, msg_req, msg_rsp) \
0154 M(CGX_PTP_RX_DISABLE,   0x20D, cgx_ptp_rx_disable, msg_req, msg_rsp)    \
0155 M(CGX_CFG_PAUSE_FRM,    0x20E, cgx_cfg_pause_frm, cgx_pause_frm_cfg,    \
0156                    cgx_pause_frm_cfg)           \
0157 M(CGX_FW_DATA_GET,  0x20F, cgx_get_aux_link_info, msg_req, cgx_fw_data) \
0158 M(CGX_FEC_SET,      0x210, cgx_set_fec_param, fec_mode, fec_mode) \
0159 M(CGX_MAC_ADDR_ADD, 0x211, cgx_mac_addr_add, cgx_mac_addr_add_req,    \
0160                 cgx_mac_addr_add_rsp)       \
0161 M(CGX_MAC_ADDR_DEL, 0x212, cgx_mac_addr_del, cgx_mac_addr_del_req,    \
0162                    msg_rsp)     \
0163 M(CGX_MAC_MAX_ENTRIES_GET, 0x213, cgx_mac_max_entries_get, msg_req,    \
0164                   cgx_max_dmac_entries_get_rsp)     \
0165 M(CGX_FEC_STATS,    0x217, cgx_fec_stats, msg_req, cgx_fec_stats_rsp) \
0166 M(CGX_SET_LINK_MODE,    0x218, cgx_set_link_mode, cgx_set_link_mode_req,\
0167                    cgx_set_link_mode_rsp)   \
0168 M(CGX_GET_PHY_FEC_STATS, 0x219, cgx_get_phy_fec_stats, msg_req, msg_rsp) \
0169 M(CGX_FEATURES_GET, 0x21B, cgx_features_get, msg_req,       \
0170                    cgx_features_info_msg)           \
0171 M(RPM_STATS,        0x21C, rpm_stats, msg_req, rpm_stats_rsp)   \
0172 M(CGX_MAC_ADDR_RESET,   0x21D, cgx_mac_addr_reset, cgx_mac_addr_reset_req, \
0173                             msg_rsp) \
0174 M(CGX_MAC_ADDR_UPDATE,  0x21E, cgx_mac_addr_update, cgx_mac_addr_update_req, \
0175                             cgx_mac_addr_update_rsp) \
0176 M(CGX_PRIO_FLOW_CTRL_CFG, 0x21F, cgx_prio_flow_ctrl_cfg, cgx_pfc_cfg,  \
0177                  cgx_pfc_rsp)                               \
0178 /* NPA mbox IDs (range 0x400 - 0x5FF) */                \
0179 M(NPA_LF_ALLOC,     0x400, npa_lf_alloc,                \
0180                 npa_lf_alloc_req, npa_lf_alloc_rsp) \
0181 M(NPA_LF_FREE,      0x401, npa_lf_free, msg_req, msg_rsp)       \
0182 M(NPA_AQ_ENQ,       0x402, npa_aq_enq, npa_aq_enq_req, npa_aq_enq_rsp)   \
0183 M(NPA_HWCTX_DISABLE,    0x403, npa_hwctx_disable, hwctx_disable_req, msg_rsp)\
0184 /* SSO/SSOW mbox IDs (range 0x600 - 0x7FF) */               \
0185 /* TIM mbox IDs (range 0x800 - 0x9FF) */                \
0186 /* CPT mbox IDs (range 0xA00 - 0xBFF) */                \
0187 M(CPT_LF_ALLOC,     0xA00, cpt_lf_alloc, cpt_lf_alloc_req_msg,  \
0188                    msg_rsp)                 \
0189 M(CPT_LF_FREE,      0xA01, cpt_lf_free, msg_req, msg_rsp)       \
0190 M(CPT_RD_WR_REGISTER,   0xA02, cpt_rd_wr_register,  cpt_rd_wr_reg_msg,  \
0191                    cpt_rd_wr_reg_msg)           \
0192 M(CPT_INLINE_IPSEC_CFG, 0xA04, cpt_inline_ipsec_cfg,            \
0193                    cpt_inline_ipsec_cfg_msg, msg_rsp)   \
0194 M(CPT_STATS,            0xA05, cpt_sts, cpt_sts_req, cpt_sts_rsp)   \
0195 M(CPT_RXC_TIME_CFG,     0xA06, cpt_rxc_time_cfg, cpt_rxc_time_cfg_req,  \
0196                    msg_rsp)                                 \
0197 M(CPT_CTX_CACHE_SYNC,   0xA07, cpt_ctx_cache_sync, msg_req, msg_rsp)    \
0198 /* SDP mbox IDs (range 0x1000 - 0x11FF) */              \
0199 M(SET_SDP_CHAN_INFO, 0x1000, set_sdp_chan_info, sdp_chan_info_msg, msg_rsp) \
0200 M(GET_SDP_CHAN_INFO, 0x1001, get_sdp_chan_info, msg_req, sdp_get_chan_info_msg) \
0201 /* NPC mbox IDs (range 0x6000 - 0x7FFF) */              \
0202 M(NPC_MCAM_ALLOC_ENTRY, 0x6000, npc_mcam_alloc_entry, npc_mcam_alloc_entry_req,\
0203                 npc_mcam_alloc_entry_rsp)       \
0204 M(NPC_MCAM_FREE_ENTRY,  0x6001, npc_mcam_free_entry,            \
0205                  npc_mcam_free_entry_req, msg_rsp)  \
0206 M(NPC_MCAM_WRITE_ENTRY, 0x6002, npc_mcam_write_entry,           \
0207                  npc_mcam_write_entry_req, msg_rsp) \
0208 M(NPC_MCAM_ENA_ENTRY,   0x6003, npc_mcam_ena_entry,         \
0209                  npc_mcam_ena_dis_entry_req, msg_rsp)   \
0210 M(NPC_MCAM_DIS_ENTRY,   0x6004, npc_mcam_dis_entry,         \
0211                  npc_mcam_ena_dis_entry_req, msg_rsp)   \
0212 M(NPC_MCAM_SHIFT_ENTRY, 0x6005, npc_mcam_shift_entry, npc_mcam_shift_entry_req,\
0213                 npc_mcam_shift_entry_rsp)       \
0214 M(NPC_MCAM_ALLOC_COUNTER, 0x6006, npc_mcam_alloc_counter,       \
0215                     npc_mcam_alloc_counter_req, \
0216                     npc_mcam_alloc_counter_rsp) \
0217 M(NPC_MCAM_FREE_COUNTER,  0x6007, npc_mcam_free_counter,        \
0218                     npc_mcam_oper_counter_req, msg_rsp) \
0219 M(NPC_MCAM_UNMAP_COUNTER, 0x6008, npc_mcam_unmap_counter,       \
0220                    npc_mcam_unmap_counter_req, msg_rsp) \
0221 M(NPC_MCAM_CLEAR_COUNTER, 0x6009, npc_mcam_clear_counter,       \
0222                    npc_mcam_oper_counter_req, msg_rsp)  \
0223 M(NPC_MCAM_COUNTER_STATS, 0x600a, npc_mcam_counter_stats,       \
0224                    npc_mcam_oper_counter_req,       \
0225                    npc_mcam_oper_counter_rsp)       \
0226 M(NPC_MCAM_ALLOC_AND_WRITE_ENTRY, 0x600b, npc_mcam_alloc_and_write_entry,      \
0227                       npc_mcam_alloc_and_write_entry_req,  \
0228                       npc_mcam_alloc_and_write_entry_rsp)  \
0229 M(NPC_GET_KEX_CFG,    0x600c, npc_get_kex_cfg,          \
0230                    msg_req, npc_get_kex_cfg_rsp)    \
0231 M(NPC_INSTALL_FLOW,   0x600d, npc_install_flow,                \
0232                   npc_install_flow_req, npc_install_flow_rsp)  \
0233 M(NPC_DELETE_FLOW,    0x600e, npc_delete_flow,          \
0234                   npc_delete_flow_req, msg_rsp)     \
0235 M(NPC_MCAM_READ_ENTRY,    0x600f, npc_mcam_read_entry,          \
0236                   npc_mcam_read_entry_req,      \
0237                   npc_mcam_read_entry_rsp)      \
0238 M(NPC_SET_PKIND,        0x6010,   npc_set_pkind,                        \
0239                   npc_set_pkind, msg_rsp)               \
0240 M(NPC_MCAM_READ_BASE_RULE, 0x6011, npc_read_base_steer_rule,            \
0241                    msg_req, npc_mcam_read_base_rule_rsp)  \
0242 M(NPC_MCAM_GET_STATS, 0x6012, npc_mcam_entry_stats,                     \
0243                    npc_mcam_get_stats_req,              \
0244                    npc_mcam_get_stats_rsp)              \
0245 M(NPC_GET_SECRET_KEY, 0x6013, npc_get_secret_key,                     \
0246                    npc_get_secret_key_req,              \
0247                    npc_get_secret_key_rsp)              \
0248 /* NIX mbox IDs (range 0x8000 - 0xFFFF) */              \
0249 M(NIX_LF_ALLOC,     0x8000, nix_lf_alloc,               \
0250                  nix_lf_alloc_req, nix_lf_alloc_rsp)    \
0251 M(NIX_LF_FREE,      0x8001, nix_lf_free, nix_lf_free_req, msg_rsp)  \
0252 M(NIX_AQ_ENQ,       0x8002, nix_aq_enq, nix_aq_enq_req, nix_aq_enq_rsp)  \
0253 M(NIX_HWCTX_DISABLE,    0x8003, nix_hwctx_disable,          \
0254                  hwctx_disable_req, msg_rsp)        \
0255 M(NIX_TXSCH_ALLOC,  0x8004, nix_txsch_alloc,            \
0256                  nix_txsch_alloc_req, nix_txsch_alloc_rsp)   \
0257 M(NIX_TXSCH_FREE,   0x8005, nix_txsch_free, nix_txsch_free_req, msg_rsp) \
0258 M(NIX_TXSCHQ_CFG,   0x8006, nix_txschq_cfg, nix_txschq_config,  \
0259                 nix_txschq_config)          \
0260 M(NIX_STATS_RST,    0x8007, nix_stats_rst, msg_req, msg_rsp)    \
0261 M(NIX_VTAG_CFG,     0x8008, nix_vtag_cfg, nix_vtag_config,      \
0262                  nix_vtag_config_rsp)           \
0263 M(NIX_RSS_FLOWKEY_CFG,  0x8009, nix_rss_flowkey_cfg,            \
0264                  nix_rss_flowkey_cfg,           \
0265                  nix_rss_flowkey_cfg_rsp)       \
0266 M(NIX_SET_MAC_ADDR, 0x800a, nix_set_mac_addr, nix_set_mac_addr, msg_rsp) \
0267 M(NIX_SET_RX_MODE,  0x800b, nix_set_rx_mode, nix_rx_mode, msg_rsp)  \
0268 M(NIX_SET_HW_FRS,   0x800c, nix_set_hw_frs, nix_frs_cfg, msg_rsp)   \
0269 M(NIX_LF_START_RX,  0x800d, nix_lf_start_rx, msg_req, msg_rsp)  \
0270 M(NIX_LF_STOP_RX,   0x800e, nix_lf_stop_rx, msg_req, msg_rsp)   \
0271 M(NIX_MARK_FORMAT_CFG,  0x800f, nix_mark_format_cfg,            \
0272                  nix_mark_format_cfg,           \
0273                  nix_mark_format_cfg_rsp)       \
0274 M(NIX_SET_RX_CFG,   0x8010, nix_set_rx_cfg, nix_rx_cfg, msg_rsp)    \
0275 M(NIX_LSO_FORMAT_CFG,   0x8011, nix_lso_format_cfg,         \
0276                  nix_lso_format_cfg,            \
0277                  nix_lso_format_cfg_rsp)        \
0278 M(NIX_LF_PTP_TX_ENABLE, 0x8013, nix_lf_ptp_tx_enable, msg_req, msg_rsp) \
0279 M(NIX_LF_PTP_TX_DISABLE, 0x8014, nix_lf_ptp_tx_disable, msg_req, msg_rsp) \
0280 M(NIX_BP_ENABLE,    0x8016, nix_bp_enable, nix_bp_cfg_req,  \
0281                 nix_bp_cfg_rsp) \
0282 M(NIX_BP_DISABLE,   0x8017, nix_bp_disable, nix_bp_cfg_req, msg_rsp) \
0283 M(NIX_GET_MAC_ADDR, 0x8018, nix_get_mac_addr, msg_req, nix_get_mac_addr_rsp) \
0284 M(NIX_INLINE_IPSEC_CFG, 0x8019, nix_inline_ipsec_cfg,           \
0285                 nix_inline_ipsec_cfg, msg_rsp)      \
0286 M(NIX_INLINE_IPSEC_LF_CFG, 0x801a, nix_inline_ipsec_lf_cfg,     \
0287                 nix_inline_ipsec_lf_cfg, msg_rsp)   \
0288 M(NIX_CN10K_AQ_ENQ, 0x801b, nix_cn10k_aq_enq, nix_cn10k_aq_enq_req, \
0289                 nix_cn10k_aq_enq_rsp)           \
0290 M(NIX_GET_HW_INFO,  0x801c, nix_get_hw_info, msg_req, nix_hw_info)  \
0291 M(NIX_BANDPROF_ALLOC,   0x801d, nix_bandprof_alloc, nix_bandprof_alloc_req, \
0292                 nix_bandprof_alloc_rsp)             \
0293 M(NIX_BANDPROF_FREE,    0x801e, nix_bandprof_free, nix_bandprof_free_req,   \
0294                 msg_rsp)                    \
0295 M(NIX_BANDPROF_GET_HWINFO, 0x801f, nix_bandprof_get_hwinfo, msg_req,        \
0296                 nix_bandprof_get_hwinfo_rsp)
0297 
0298 /* Messages initiated by AF (range 0xC00 - 0xDFF) */
0299 #define MBOX_UP_CGX_MESSAGES                        \
0300 M(CGX_LINK_EVENT,   0xC00, cgx_link_event, cgx_link_info_msg, msg_rsp)
0301 
0302 #define MBOX_UP_CPT_MESSAGES                        \
0303 M(CPT_INST_LMTST,   0xD00, cpt_inst_lmtst, cpt_inst_lmtst_req, msg_rsp)
0304 
0305 enum {
0306 #define M(_name, _id, _1, _2, _3) MBOX_MSG_ ## _name = _id,
0307 MBOX_MESSAGES
0308 MBOX_UP_CGX_MESSAGES
0309 MBOX_UP_CPT_MESSAGES
0310 #undef M
0311 };
0312 
0313 /* Mailbox message formats */
0314 
0315 #define RVU_DEFAULT_PF_FUNC     0xFFFF
0316 
0317 /* Generic request msg used for those mbox messages which
0318  * don't send any data in the request.
0319  */
0320 struct msg_req {
0321     struct mbox_msghdr hdr;
0322 };
0323 
0324 /* Generic response msg used an ack or response for those mbox
0325  * messages which don't have a specific rsp msg format.
0326  */
0327 struct msg_rsp {
0328     struct mbox_msghdr hdr;
0329 };
0330 
0331 /* RVU mailbox error codes
0332  * Range 256 - 300.
0333  */
0334 enum rvu_af_status {
0335     RVU_INVALID_VF_ID           = -256,
0336 };
0337 
0338 struct ready_msg_rsp {
0339     struct mbox_msghdr hdr;
0340     u16    sclk_freq;   /* SCLK frequency (in MHz) */
0341     u16    rclk_freq;   /* RCLK frequency (in MHz) */
0342 };
0343 
0344 /* Structure for requesting resource provisioning.
0345  * 'modify' flag to be used when either requesting more
0346  * or to detach partial of a certain resource type.
0347  * Rest of the fields specify how many of what type to
0348  * be attached.
0349  * To request LFs from two blocks of same type this mailbox
0350  * can be sent twice as below:
0351  *      struct rsrc_attach *attach;
0352  *       .. Allocate memory for message ..
0353  *       attach->cptlfs = 3; <3 LFs from CPT0>
0354  *       .. Send message ..
0355  *       .. Allocate memory for message ..
0356  *       attach->modify = 1;
0357  *       attach->cpt_blkaddr = BLKADDR_CPT1;
0358  *       attach->cptlfs = 2; <2 LFs from CPT1>
0359  *       .. Send message ..
0360  */
0361 struct rsrc_attach {
0362     struct mbox_msghdr hdr;
0363     u8   modify:1;
0364     u8   npalf:1;
0365     u8   nixlf:1;
0366     u16  sso;
0367     u16  ssow;
0368     u16  timlfs;
0369     u16  cptlfs;
0370     int  cpt_blkaddr; /* BLKADDR_CPT0/BLKADDR_CPT1 or 0 for BLKADDR_CPT0 */
0371 };
0372 
0373 /* Structure for relinquishing resources.
0374  * 'partial' flag to be used when relinquishing all resources
0375  * but only of a certain type. If not set, all resources of all
0376  * types provisioned to the RVU function will be detached.
0377  */
0378 struct rsrc_detach {
0379     struct mbox_msghdr hdr;
0380     u8 partial:1;
0381     u8 npalf:1;
0382     u8 nixlf:1;
0383     u8 sso:1;
0384     u8 ssow:1;
0385     u8 timlfs:1;
0386     u8 cptlfs:1;
0387 };
0388 
0389 /* Number of resources available to the caller.
0390  * In reply to MBOX_MSG_FREE_RSRC_CNT.
0391  */
0392 struct free_rsrcs_rsp {
0393     struct mbox_msghdr hdr;
0394     u16 schq[NIX_TXSCH_LVL_CNT];
0395     u16  sso;
0396     u16  tim;
0397     u16  ssow;
0398     u16  cpt;
0399     u8   npa;
0400     u8   nix;
0401     u16  schq_nix1[NIX_TXSCH_LVL_CNT];
0402     u8   nix1;
0403     u8   cpt1;
0404     u8   ree0;
0405     u8   ree1;
0406 };
0407 
0408 #define MSIX_VECTOR_INVALID 0xFFFF
0409 #define MAX_RVU_BLKLF_CNT   256
0410 
0411 struct msix_offset_rsp {
0412     struct mbox_msghdr hdr;
0413     u16  npa_msixoff;
0414     u16  nix_msixoff;
0415     u16  sso;
0416     u16  ssow;
0417     u16  timlfs;
0418     u16  cptlfs;
0419     u16  sso_msixoff[MAX_RVU_BLKLF_CNT];
0420     u16  ssow_msixoff[MAX_RVU_BLKLF_CNT];
0421     u16  timlf_msixoff[MAX_RVU_BLKLF_CNT];
0422     u16  cptlf_msixoff[MAX_RVU_BLKLF_CNT];
0423     u16  cpt1_lfs;
0424     u16  ree0_lfs;
0425     u16  ree1_lfs;
0426     u16  cpt1_lf_msixoff[MAX_RVU_BLKLF_CNT];
0427     u16  ree0_lf_msixoff[MAX_RVU_BLKLF_CNT];
0428     u16  ree1_lf_msixoff[MAX_RVU_BLKLF_CNT];
0429 };
0430 
0431 struct get_hw_cap_rsp {
0432     struct mbox_msghdr hdr;
0433     u8 nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
0434     u8 nix_shaping;          /* Is shaping and coloring supported */
0435     u8 npc_hash_extract;    /* Is hash extract supported */
0436 };
0437 
0438 /* CGX mbox message formats */
0439 
0440 struct cgx_stats_rsp {
0441     struct mbox_msghdr hdr;
0442 #define CGX_RX_STATS_COUNT  9
0443 #define CGX_TX_STATS_COUNT  18
0444     u64 rx_stats[CGX_RX_STATS_COUNT];
0445     u64 tx_stats[CGX_TX_STATS_COUNT];
0446 };
0447 
0448 struct cgx_fec_stats_rsp {
0449     struct mbox_msghdr hdr;
0450     u64 fec_corr_blks;
0451     u64 fec_uncorr_blks;
0452 };
0453 /* Structure for requesting the operation for
0454  * setting/getting mac address in the CGX interface
0455  */
0456 struct cgx_mac_addr_set_or_get {
0457     struct mbox_msghdr hdr;
0458     u8 mac_addr[ETH_ALEN];
0459     u32 index;
0460 };
0461 
0462 /* Structure for requesting the operation to
0463  * add DMAC filter entry into CGX interface
0464  */
0465 struct cgx_mac_addr_add_req {
0466     struct mbox_msghdr hdr;
0467     u8 mac_addr[ETH_ALEN];
0468 };
0469 
0470 /* Structure for response against the operation to
0471  * add DMAC filter entry into CGX interface
0472  */
0473 struct cgx_mac_addr_add_rsp {
0474     struct mbox_msghdr hdr;
0475     u32 index;
0476 };
0477 
0478 /* Structure for requesting the operation to
0479  * delete DMAC filter entry from CGX interface
0480  */
0481 struct cgx_mac_addr_del_req {
0482     struct mbox_msghdr hdr;
0483     u32 index;
0484 };
0485 
0486 /* Structure for response against the operation to
0487  * get maximum supported DMAC filter entries
0488  */
0489 struct cgx_max_dmac_entries_get_rsp {
0490     struct mbox_msghdr hdr;
0491     u32 max_dmac_filters;
0492 };
0493 
0494 struct cgx_link_user_info {
0495     uint64_t link_up:1;
0496     uint64_t full_duplex:1;
0497     uint64_t lmac_type_id:4;
0498     uint64_t speed:20; /* speed in Mbps */
0499     uint64_t an:1;      /* AN supported or not */
0500     uint64_t fec:2;  /* FEC type if enabled else 0 */
0501 #define LMACTYPE_STR_LEN 16
0502     char lmac_type[LMACTYPE_STR_LEN];
0503 };
0504 
0505 struct cgx_link_info_msg {
0506     struct mbox_msghdr hdr;
0507     struct cgx_link_user_info link_info;
0508 };
0509 
0510 struct cgx_pause_frm_cfg {
0511     struct mbox_msghdr hdr;
0512     u8 set;
0513     /* set = 1 if the request is to config pause frames */
0514     /* set = 0 if the request is to fetch pause frames config */
0515     u8 rx_pause;
0516     u8 tx_pause;
0517 };
0518 
0519 enum fec_type {
0520     OTX2_FEC_NONE,
0521     OTX2_FEC_BASER,
0522     OTX2_FEC_RS,
0523     OTX2_FEC_STATS_CNT = 2,
0524     OTX2_FEC_OFF,
0525 };
0526 
0527 struct fec_mode {
0528     struct mbox_msghdr hdr;
0529     int fec;
0530 };
0531 
0532 struct sfp_eeprom_s {
0533 #define SFP_EEPROM_SIZE 256
0534     u16 sff_id;
0535     u8 buf[SFP_EEPROM_SIZE];
0536     u64 reserved;
0537 };
0538 
0539 struct phy_s {
0540     struct {
0541         u64 can_change_mod_type:1;
0542         u64 mod_type:1;
0543         u64 has_fec_stats:1;
0544     } misc;
0545     struct fec_stats_s {
0546         u32 rsfec_corr_cws;
0547         u32 rsfec_uncorr_cws;
0548         u32 brfec_corr_blks;
0549         u32 brfec_uncorr_blks;
0550     } fec_stats;
0551 };
0552 
0553 struct cgx_lmac_fwdata_s {
0554     u16 rw_valid;
0555     u64 supported_fec;
0556     u64 supported_an;
0557     u64 supported_link_modes;
0558     /* only applicable if AN is supported */
0559     u64 advertised_fec;
0560     u64 advertised_link_modes;
0561     /* Only applicable if SFP/QSFP slot is present */
0562     struct sfp_eeprom_s sfp_eeprom;
0563     struct phy_s phy;
0564 #define LMAC_FWDATA_RESERVED_MEM 1021
0565     u64 reserved[LMAC_FWDATA_RESERVED_MEM];
0566 };
0567 
0568 struct cgx_fw_data {
0569     struct mbox_msghdr hdr;
0570     struct cgx_lmac_fwdata_s fwdata;
0571 };
0572 
0573 struct cgx_set_link_mode_args {
0574     u32 speed;
0575     u8 duplex;
0576     u8 an;
0577     u8 ports;
0578     u64 mode;
0579 };
0580 
0581 struct cgx_set_link_mode_req {
0582 #define AUTONEG_UNKNOWN     0xff
0583     struct mbox_msghdr hdr;
0584     struct cgx_set_link_mode_args args;
0585 };
0586 
0587 struct cgx_set_link_mode_rsp {
0588     struct mbox_msghdr hdr;
0589     int status;
0590 };
0591 
0592 struct cgx_mac_addr_reset_req {
0593     struct mbox_msghdr hdr;
0594     u32 index;
0595 };
0596 
0597 struct cgx_mac_addr_update_req {
0598     struct mbox_msghdr hdr;
0599     u8 mac_addr[ETH_ALEN];
0600     u32 index;
0601 };
0602 
0603 struct cgx_mac_addr_update_rsp {
0604     struct mbox_msghdr hdr;
0605     u32 index;
0606 };
0607 
0608 #define RVU_LMAC_FEAT_FC        BIT_ULL(0) /* pause frames */
0609 #define RVU_LMAC_FEAT_HIGIG2        BIT_ULL(1)
0610             /* flow control from physical link higig2 messages */
0611 #define RVU_LMAC_FEAT_PTP       BIT_ULL(2) /* precison time protocol */
0612 #define RVU_LMAC_FEAT_DMACF     BIT_ULL(3) /* DMAC FILTER */
0613 #define RVU_MAC_VERSION         BIT_ULL(4)
0614 #define RVU_MAC_CGX         BIT_ULL(5)
0615 #define RVU_MAC_RPM         BIT_ULL(6)
0616 
0617 struct cgx_features_info_msg {
0618     struct mbox_msghdr hdr;
0619     u64    lmac_features;
0620 };
0621 
0622 struct rpm_stats_rsp {
0623     struct mbox_msghdr hdr;
0624 #define RPM_RX_STATS_COUNT      43
0625 #define RPM_TX_STATS_COUNT      34
0626     u64 rx_stats[RPM_RX_STATS_COUNT];
0627     u64 tx_stats[RPM_TX_STATS_COUNT];
0628 };
0629 
0630 struct cgx_pfc_cfg {
0631     struct mbox_msghdr hdr;
0632     u8 rx_pause;
0633     u8 tx_pause;
0634     u16 pfc_en; /*  bitmap indicating pfc enabled traffic classes */
0635 };
0636 
0637 struct cgx_pfc_rsp {
0638     struct mbox_msghdr hdr;
0639     u8 rx_pause;
0640     u8 tx_pause;
0641 };
0642 
0643  /* NPA mbox message formats */
0644 
0645 struct npc_set_pkind {
0646     struct mbox_msghdr hdr;
0647 #define OTX2_PRIV_FLAGS_DEFAULT  BIT_ULL(0)
0648 #define OTX2_PRIV_FLAGS_CUSTOM   BIT_ULL(63)
0649     u64 mode;
0650 #define PKIND_TX        BIT_ULL(0)
0651 #define PKIND_RX        BIT_ULL(1)
0652     u8 dir;
0653     u8 pkind; /* valid only in case custom flag */
0654     u8 var_len_off; /* Offset of custom header length field.
0655              * Valid only for pkind NPC_RX_CUSTOM_PRE_L2_PKIND
0656              */
0657     u8 var_len_off_mask; /* Mask for length with in offset */
0658     u8 shift_dir; /* shift direction to get length of the header at var_len_off */
0659 };
0660 
0661 /* NPA mbox message formats */
0662 
0663 /* NPA mailbox error codes
0664  * Range 301 - 400.
0665  */
0666 enum npa_af_status {
0667     NPA_AF_ERR_PARAM            = -301,
0668     NPA_AF_ERR_AQ_FULL          = -302,
0669     NPA_AF_ERR_AQ_ENQUEUE       = -303,
0670     NPA_AF_ERR_AF_LF_INVALID    = -304,
0671     NPA_AF_ERR_AF_LF_ALLOC      = -305,
0672     NPA_AF_ERR_LF_RESET         = -306,
0673 };
0674 
0675 /* For NPA LF context alloc and init */
0676 struct npa_lf_alloc_req {
0677     struct mbox_msghdr hdr;
0678     int node;
0679     int aura_sz;  /* No of auras */
0680     u32 nr_pools; /* No of pools */
0681     u64 way_mask;
0682 };
0683 
0684 struct npa_lf_alloc_rsp {
0685     struct mbox_msghdr hdr;
0686     u32 stack_pg_ptrs;  /* No of ptrs per stack page */
0687     u32 stack_pg_bytes; /* Size of stack page */
0688     u16 qints; /* NPA_AF_CONST::QINTS */
0689     u8 cache_lines; /*BATCH ALLOC DMA */
0690 };
0691 
0692 /* NPA AQ enqueue msg */
0693 struct npa_aq_enq_req {
0694     struct mbox_msghdr hdr;
0695     u32 aura_id;
0696     u8 ctype;
0697     u8 op;
0698     union {
0699         /* Valid when op == WRITE/INIT and ctype == AURA.
0700          * LF fills the pool_id in aura.pool_addr. AF will translate
0701          * the pool_id to pool context pointer.
0702          */
0703         struct npa_aura_s aura;
0704         /* Valid when op == WRITE/INIT and ctype == POOL */
0705         struct npa_pool_s pool;
0706     };
0707     /* Mask data when op == WRITE (1=write, 0=don't write) */
0708     union {
0709         /* Valid when op == WRITE and ctype == AURA */
0710         struct npa_aura_s aura_mask;
0711         /* Valid when op == WRITE and ctype == POOL */
0712         struct npa_pool_s pool_mask;
0713     };
0714 };
0715 
0716 struct npa_aq_enq_rsp {
0717     struct mbox_msghdr hdr;
0718     union {
0719         /* Valid when op == READ and ctype == AURA */
0720         struct npa_aura_s aura;
0721         /* Valid when op == READ and ctype == POOL */
0722         struct npa_pool_s pool;
0723     };
0724 };
0725 
0726 /* Disable all contexts of type 'ctype' */
0727 struct hwctx_disable_req {
0728     struct mbox_msghdr hdr;
0729     u8 ctype;
0730 };
0731 
0732 /* NIX mbox message formats */
0733 
0734 /* NIX mailbox error codes
0735  * Range 401 - 500.
0736  */
0737 enum nix_af_status {
0738     NIX_AF_ERR_PARAM            = -401,
0739     NIX_AF_ERR_AQ_FULL          = -402,
0740     NIX_AF_ERR_AQ_ENQUEUE       = -403,
0741     NIX_AF_ERR_AF_LF_INVALID    = -404,
0742     NIX_AF_ERR_AF_LF_ALLOC      = -405,
0743     NIX_AF_ERR_TLX_ALLOC_FAIL   = -406,
0744     NIX_AF_ERR_TLX_INVALID      = -407,
0745     NIX_AF_ERR_RSS_SIZE_INVALID = -408,
0746     NIX_AF_ERR_RSS_GRPS_INVALID = -409,
0747     NIX_AF_ERR_FRS_INVALID      = -410,
0748     NIX_AF_ERR_RX_LINK_INVALID  = -411,
0749     NIX_AF_INVAL_TXSCHQ_CFG     = -412,
0750     NIX_AF_SMQ_FLUSH_FAILED     = -413,
0751     NIX_AF_ERR_LF_RESET         = -414,
0752     NIX_AF_ERR_RSS_NOSPC_FIELD  = -415,
0753     NIX_AF_ERR_RSS_NOSPC_ALGO   = -416,
0754     NIX_AF_ERR_MARK_CFG_FAIL    = -417,
0755     NIX_AF_ERR_LSO_CFG_FAIL     = -418,
0756     NIX_AF_INVAL_NPA_PF_FUNC    = -419,
0757     NIX_AF_INVAL_SSO_PF_FUNC    = -420,
0758     NIX_AF_ERR_TX_VTAG_NOSPC    = -421,
0759     NIX_AF_ERR_RX_VTAG_INUSE    = -422,
0760     NIX_AF_ERR_PTP_CONFIG_FAIL  = -423,
0761     NIX_AF_ERR_NPC_KEY_NOT_SUPP = -424,
0762     NIX_AF_ERR_INVALID_NIXBLK   = -425,
0763     NIX_AF_ERR_INVALID_BANDPROF = -426,
0764     NIX_AF_ERR_IPOLICER_NOTSUPP = -427,
0765     NIX_AF_ERR_BANDPROF_INVAL_REQ  = -428,
0766     NIX_AF_ERR_CQ_CTX_WRITE_ERR  = -429,
0767     NIX_AF_ERR_AQ_CTX_RETRY_WRITE  = -430,
0768     NIX_AF_ERR_LINK_CREDITS  = -431,
0769 };
0770 
0771 /* For NIX RX vtag action  */
0772 enum nix_rx_vtag0_type {
0773     NIX_AF_LFX_RX_VTAG_TYPE0, /* reserved for rx vlan offload */
0774     NIX_AF_LFX_RX_VTAG_TYPE1,
0775     NIX_AF_LFX_RX_VTAG_TYPE2,
0776     NIX_AF_LFX_RX_VTAG_TYPE3,
0777     NIX_AF_LFX_RX_VTAG_TYPE4,
0778     NIX_AF_LFX_RX_VTAG_TYPE5,
0779     NIX_AF_LFX_RX_VTAG_TYPE6,
0780     NIX_AF_LFX_RX_VTAG_TYPE7,
0781 };
0782 
0783 /* For NIX LF context alloc and init */
0784 struct nix_lf_alloc_req {
0785     struct mbox_msghdr hdr;
0786     int node;
0787     u32 rq_cnt;   /* No of receive queues */
0788     u32 sq_cnt;   /* No of send queues */
0789     u32 cq_cnt;   /* No of completion queues */
0790     u8  xqe_sz;
0791     u16 rss_sz;
0792     u8  rss_grps;
0793     u16 npa_func;
0794     u16 sso_func;
0795     u64 rx_cfg;   /* See NIX_AF_LF(0..127)_RX_CFG */
0796     u64 way_mask;
0797 #define NIX_LF_RSS_TAG_LSB_AS_ADDER BIT_ULL(0)
0798 #define NIX_LF_LBK_BLK_SEL      BIT_ULL(1)
0799     u64 flags;
0800 };
0801 
0802 struct nix_lf_alloc_rsp {
0803     struct mbox_msghdr hdr;
0804     u16 sqb_size;
0805     u16 rx_chan_base;
0806     u16 tx_chan_base;
0807     u8      rx_chan_cnt; /* total number of RX channels */
0808     u8      tx_chan_cnt; /* total number of TX channels */
0809     u8  lso_tsov4_idx;
0810     u8  lso_tsov6_idx;
0811     u8      mac_addr[ETH_ALEN];
0812     u8  lf_rx_stats; /* NIX_AF_CONST1::LF_RX_STATS */
0813     u8  lf_tx_stats; /* NIX_AF_CONST1::LF_TX_STATS */
0814     u16 cints; /* NIX_AF_CONST2::CINTS */
0815     u16 qints; /* NIX_AF_CONST2::QINTS */
0816     u8  cgx_links;  /* No. of CGX links present in HW */
0817     u8  lbk_links;  /* No. of LBK links present in HW */
0818     u8  sdp_links;  /* No. of SDP links present in HW */
0819     u8  tx_link;    /* Transmit channel link number */
0820 };
0821 
0822 struct nix_lf_free_req {
0823     struct mbox_msghdr hdr;
0824 #define NIX_LF_DISABLE_FLOWS        BIT_ULL(0)
0825 #define NIX_LF_DONT_FREE_TX_VTAG    BIT_ULL(1)
0826     u64 flags;
0827 };
0828 
0829 /* CN10K NIX AQ enqueue msg */
0830 struct nix_cn10k_aq_enq_req {
0831     struct mbox_msghdr hdr;
0832     u32  qidx;
0833     u8 ctype;
0834     u8 op;
0835     union {
0836         struct nix_cn10k_rq_ctx_s rq;
0837         struct nix_cn10k_sq_ctx_s sq;
0838         struct nix_cq_ctx_s cq;
0839         struct nix_rsse_s   rss;
0840         struct nix_rx_mce_s mce;
0841         struct nix_bandprof_s prof;
0842     };
0843     union {
0844         struct nix_cn10k_rq_ctx_s rq_mask;
0845         struct nix_cn10k_sq_ctx_s sq_mask;
0846         struct nix_cq_ctx_s cq_mask;
0847         struct nix_rsse_s   rss_mask;
0848         struct nix_rx_mce_s mce_mask;
0849         struct nix_bandprof_s prof_mask;
0850     };
0851 };
0852 
0853 struct nix_cn10k_aq_enq_rsp {
0854     struct mbox_msghdr hdr;
0855     union {
0856         struct nix_cn10k_rq_ctx_s rq;
0857         struct nix_cn10k_sq_ctx_s sq;
0858         struct nix_cq_ctx_s cq;
0859         struct nix_rsse_s   rss;
0860         struct nix_rx_mce_s mce;
0861         struct nix_bandprof_s prof;
0862     };
0863 };
0864 
0865 /* NIX AQ enqueue msg */
0866 struct nix_aq_enq_req {
0867     struct mbox_msghdr hdr;
0868     u32  qidx;
0869     u8 ctype;
0870     u8 op;
0871     union {
0872         struct nix_rq_ctx_s rq;
0873         struct nix_sq_ctx_s sq;
0874         struct nix_cq_ctx_s cq;
0875         struct nix_rsse_s   rss;
0876         struct nix_rx_mce_s mce;
0877         u64 prof;
0878     };
0879     union {
0880         struct nix_rq_ctx_s rq_mask;
0881         struct nix_sq_ctx_s sq_mask;
0882         struct nix_cq_ctx_s cq_mask;
0883         struct nix_rsse_s   rss_mask;
0884         struct nix_rx_mce_s mce_mask;
0885         u64 prof_mask;
0886     };
0887 };
0888 
0889 struct nix_aq_enq_rsp {
0890     struct mbox_msghdr hdr;
0891     union {
0892         struct nix_rq_ctx_s rq;
0893         struct nix_sq_ctx_s sq;
0894         struct nix_cq_ctx_s cq;
0895         struct nix_rsse_s   rss;
0896         struct nix_rx_mce_s mce;
0897         struct nix_bandprof_s prof;
0898     };
0899 };
0900 
0901 /* Tx scheduler/shaper mailbox messages */
0902 
0903 #define MAX_TXSCHQ_PER_FUNC     128
0904 
0905 struct nix_txsch_alloc_req {
0906     struct mbox_msghdr hdr;
0907     /* Scheduler queue count request at each level */
0908     u16 schq_contig[NIX_TXSCH_LVL_CNT]; /* No of contiguous queues */
0909     u16 schq[NIX_TXSCH_LVL_CNT]; /* No of non-contiguous queues */
0910 };
0911 
0912 struct nix_txsch_alloc_rsp {
0913     struct mbox_msghdr hdr;
0914     /* Scheduler queue count allocated at each level */
0915     u16 schq_contig[NIX_TXSCH_LVL_CNT];
0916     u16 schq[NIX_TXSCH_LVL_CNT];
0917     /* Scheduler queue list allocated at each level */
0918     u16 schq_contig_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
0919     u16 schq_list[NIX_TXSCH_LVL_CNT][MAX_TXSCHQ_PER_FUNC];
0920     u8  aggr_level; /* Traffic aggregation scheduler level */
0921     u8  aggr_lvl_rr_prio; /* Aggregation lvl's RR_PRIO config */
0922     u8  link_cfg_lvl; /* LINKX_CFG CSRs mapped to TL3 or TL2's index ? */
0923 };
0924 
0925 struct nix_txsch_free_req {
0926     struct mbox_msghdr hdr;
0927 #define TXSCHQ_FREE_ALL BIT_ULL(0)
0928     u16 flags;
0929     /* Scheduler queue level to be freed */
0930     u16 schq_lvl;
0931     /* List of scheduler queues to be freed */
0932     u16 schq;
0933 };
0934 
0935 struct nix_txschq_config {
0936     struct mbox_msghdr hdr;
0937     u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */
0938     u8 read;
0939 #define TXSCHQ_IDX_SHIFT    16
0940 #define TXSCHQ_IDX_MASK     (BIT_ULL(10) - 1)
0941 #define TXSCHQ_IDX(reg, shift)  (((reg) >> (shift)) & TXSCHQ_IDX_MASK)
0942     u8 num_regs;
0943 #define MAX_REGS_PER_MBOX_MSG   20
0944     u64 reg[MAX_REGS_PER_MBOX_MSG];
0945     u64 regval[MAX_REGS_PER_MBOX_MSG];
0946     /* All 0's => overwrite with new value */
0947     u64 regval_mask[MAX_REGS_PER_MBOX_MSG];
0948 };
0949 
0950 struct nix_vtag_config {
0951     struct mbox_msghdr hdr;
0952     /* '0' for 4 octet VTAG, '1' for 8 octet VTAG */
0953     u8 vtag_size;
0954     /* cfg_type is '0' for tx vlan cfg
0955      * cfg_type is '1' for rx vlan cfg
0956      */
0957     u8 cfg_type;
0958     union {
0959         /* valid when cfg_type is '0' */
0960         struct {
0961             u64 vtag0;
0962             u64 vtag1;
0963 
0964             /* cfg_vtag0 & cfg_vtag1 fields are valid
0965              * when free_vtag0 & free_vtag1 are '0's.
0966              */
0967             /* cfg_vtag0 = 1 to configure vtag0 */
0968             u8 cfg_vtag0 :1;
0969             /* cfg_vtag1 = 1 to configure vtag1 */
0970             u8 cfg_vtag1 :1;
0971 
0972             /* vtag0_idx & vtag1_idx are only valid when
0973              * both cfg_vtag0 & cfg_vtag1 are '0's,
0974              * these fields are used along with free_vtag0
0975              * & free_vtag1 to free the nix lf's tx_vlan
0976              * configuration.
0977              *
0978              * Denotes the indices of tx_vtag def registers
0979              * that needs to be cleared and freed.
0980              */
0981             int vtag0_idx;
0982             int vtag1_idx;
0983 
0984             /* free_vtag0 & free_vtag1 fields are valid
0985              * when cfg_vtag0 & cfg_vtag1 are '0's.
0986              */
0987             /* free_vtag0 = 1 clears vtag0 configuration
0988              * vtag0_idx denotes the index to be cleared.
0989              */
0990             u8 free_vtag0 :1;
0991             /* free_vtag1 = 1 clears vtag1 configuration
0992              * vtag1_idx denotes the index to be cleared.
0993              */
0994             u8 free_vtag1 :1;
0995         } tx;
0996 
0997         /* valid when cfg_type is '1' */
0998         struct {
0999             /* rx vtag type index, valid values are in 0..7 range */
1000             u8 vtag_type;
1001             /* rx vtag strip */
1002             u8 strip_vtag :1;
1003             /* rx vtag capture */
1004             u8 capture_vtag :1;
1005         } rx;
1006     };
1007 };
1008 
1009 struct nix_vtag_config_rsp {
1010     struct mbox_msghdr hdr;
1011     int vtag0_idx;
1012     int vtag1_idx;
1013     /* Indices of tx_vtag def registers used to configure
1014      * tx vtag0 & vtag1 headers, these indices are valid
1015      * when nix_vtag_config mbox requested for vtag0 and/
1016      * or vtag1 configuration.
1017      */
1018 };
1019 
1020 struct nix_rss_flowkey_cfg {
1021     struct mbox_msghdr hdr;
1022     int mcam_index;  /* MCAM entry index to modify */
1023 #define NIX_FLOW_KEY_TYPE_PORT  BIT(0)
1024 #define NIX_FLOW_KEY_TYPE_IPV4  BIT(1)
1025 #define NIX_FLOW_KEY_TYPE_IPV6  BIT(2)
1026 #define NIX_FLOW_KEY_TYPE_TCP   BIT(3)
1027 #define NIX_FLOW_KEY_TYPE_UDP   BIT(4)
1028 #define NIX_FLOW_KEY_TYPE_SCTP  BIT(5)
1029 #define NIX_FLOW_KEY_TYPE_NVGRE    BIT(6)
1030 #define NIX_FLOW_KEY_TYPE_VXLAN    BIT(7)
1031 #define NIX_FLOW_KEY_TYPE_GENEVE   BIT(8)
1032 #define NIX_FLOW_KEY_TYPE_ETH_DMAC BIT(9)
1033 #define NIX_FLOW_KEY_TYPE_IPV6_EXT BIT(10)
1034 #define NIX_FLOW_KEY_TYPE_GTPU       BIT(11)
1035 #define NIX_FLOW_KEY_TYPE_INNR_IPV4     BIT(12)
1036 #define NIX_FLOW_KEY_TYPE_INNR_IPV6     BIT(13)
1037 #define NIX_FLOW_KEY_TYPE_INNR_TCP      BIT(14)
1038 #define NIX_FLOW_KEY_TYPE_INNR_UDP      BIT(15)
1039 #define NIX_FLOW_KEY_TYPE_INNR_SCTP     BIT(16)
1040 #define NIX_FLOW_KEY_TYPE_INNR_ETH_DMAC BIT(17)
1041 #define NIX_FLOW_KEY_TYPE_VLAN      BIT(20)
1042 #define NIX_FLOW_KEY_TYPE_IPV4_PROTO    BIT(21)
1043 #define NIX_FLOW_KEY_TYPE_AH        BIT(22)
1044 #define NIX_FLOW_KEY_TYPE_ESP       BIT(23)
1045     u32 flowkey_cfg; /* Flowkey types selected */
1046     u8  group;       /* RSS context or group */
1047 };
1048 
1049 struct nix_rss_flowkey_cfg_rsp {
1050     struct mbox_msghdr hdr;
1051     u8  alg_idx; /* Selected algo index */
1052 };
1053 
1054 struct nix_set_mac_addr {
1055     struct mbox_msghdr hdr;
1056     u8 mac_addr[ETH_ALEN]; /* MAC address to be set for this pcifunc */
1057 };
1058 
1059 struct nix_get_mac_addr_rsp {
1060     struct mbox_msghdr hdr;
1061     u8 mac_addr[ETH_ALEN];
1062 };
1063 
1064 struct nix_mark_format_cfg {
1065     struct mbox_msghdr hdr;
1066     u8 offset;
1067     u8 y_mask;
1068     u8 y_val;
1069     u8 r_mask;
1070     u8 r_val;
1071 };
1072 
1073 struct nix_mark_format_cfg_rsp {
1074     struct mbox_msghdr hdr;
1075     u8 mark_format_idx;
1076 };
1077 
1078 struct nix_rx_mode {
1079     struct mbox_msghdr hdr;
1080 #define NIX_RX_MODE_UCAST   BIT(0)
1081 #define NIX_RX_MODE_PROMISC BIT(1)
1082 #define NIX_RX_MODE_ALLMULTI    BIT(2)
1083 #define NIX_RX_MODE_USE_MCE BIT(3)
1084     u16 mode;
1085 };
1086 
1087 struct nix_rx_cfg {
1088     struct mbox_msghdr hdr;
1089 #define NIX_RX_OL3_VERIFY   BIT(0)
1090 #define NIX_RX_OL4_VERIFY   BIT(1)
1091     u8 len_verify; /* Outer L3/L4 len check */
1092 #define NIX_RX_CSUM_OL4_VERIFY  BIT(0)
1093     u8 csum_verify; /* Outer L4 checksum verification */
1094 };
1095 
1096 struct nix_frs_cfg {
1097     struct mbox_msghdr hdr;
1098     u8  update_smq;    /* Update SMQ's min/max lens */
1099     u8  update_minlen; /* Set minlen also */
1100     u8  sdp_link;      /* Set SDP RX link */
1101     u16 maxlen;
1102     u16 minlen;
1103 };
1104 
1105 struct nix_lso_format_cfg {
1106     struct mbox_msghdr hdr;
1107     u64 field_mask;
1108 #define NIX_LSO_FIELD_MAX   8
1109     u64 fields[NIX_LSO_FIELD_MAX];
1110 };
1111 
1112 struct nix_lso_format_cfg_rsp {
1113     struct mbox_msghdr hdr;
1114     u8 lso_format_idx;
1115 };
1116 
1117 struct nix_bp_cfg_req {
1118     struct mbox_msghdr hdr;
1119     u16 chan_base; /* Starting channel number */
1120     u8  chan_cnt; /* Number of channels */
1121     u8  bpid_per_chan;
1122     /* bpid_per_chan = 0 assigns single bp id for range of channels */
1123     /* bpid_per_chan = 1 assigns separate bp id for each channel */
1124 };
1125 
1126 /* PF can be mapped to either CGX or LBK interface,
1127  * so maximum 64 channels are possible.
1128  */
1129 #define NIX_MAX_BPID_CHAN   64
1130 struct nix_bp_cfg_rsp {
1131     struct mbox_msghdr hdr;
1132     u16 chan_bpid[NIX_MAX_BPID_CHAN]; /* Channel and bpid mapping */
1133     u8  chan_cnt; /* Number of channel for which bpids are assigned */
1134 };
1135 
1136 /* Global NIX inline IPSec configuration */
1137 struct nix_inline_ipsec_cfg {
1138     struct mbox_msghdr hdr;
1139     u32 cpt_credit;
1140     struct {
1141         u8 egrp;
1142         u8 opcode;
1143         u16 param1;
1144         u16 param2;
1145     } gen_cfg;
1146     struct {
1147         u16 cpt_pf_func;
1148         u8 cpt_slot;
1149     } inst_qsel;
1150     u8 enable;
1151 };
1152 
1153 /* Per NIX LF inline IPSec configuration */
1154 struct nix_inline_ipsec_lf_cfg {
1155     struct mbox_msghdr hdr;
1156     u64 sa_base_addr;
1157     struct {
1158         u32 tag_const;
1159         u16 lenm1_max;
1160         u8 sa_pow2_size;
1161         u8 tt;
1162     } ipsec_cfg0;
1163     struct {
1164         u32 sa_idx_max;
1165         u8 sa_idx_w;
1166     } ipsec_cfg1;
1167     u8 enable;
1168 };
1169 
1170 struct nix_hw_info {
1171     struct mbox_msghdr hdr;
1172     u16 rsvs16;
1173     u16 max_mtu;
1174     u16 min_mtu;
1175     u32 rpm_dwrr_mtu;
1176     u32 sdp_dwrr_mtu;
1177     u64 rsvd[16]; /* Add reserved fields for future expansion */
1178 };
1179 
1180 struct nix_bandprof_alloc_req {
1181     struct mbox_msghdr hdr;
1182     /* Count of profiles needed per layer */
1183     u16 prof_count[BAND_PROF_NUM_LAYERS];
1184 };
1185 
1186 struct nix_bandprof_alloc_rsp {
1187     struct mbox_msghdr hdr;
1188     u16 prof_count[BAND_PROF_NUM_LAYERS];
1189 
1190     /* There is no need to allocate morethan 1 bandwidth profile
1191      * per RQ of a PF_FUNC's NIXLF. So limit the maximum
1192      * profiles to 64 per PF_FUNC.
1193      */
1194 #define MAX_BANDPROF_PER_PFFUNC 64
1195     u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1196 };
1197 
1198 struct nix_bandprof_free_req {
1199     struct mbox_msghdr hdr;
1200     u8 free_all;
1201     u16 prof_count[BAND_PROF_NUM_LAYERS];
1202     u16 prof_idx[BAND_PROF_NUM_LAYERS][MAX_BANDPROF_PER_PFFUNC];
1203 };
1204 
1205 struct nix_bandprof_get_hwinfo_rsp {
1206     struct mbox_msghdr hdr;
1207     u16 prof_count[BAND_PROF_NUM_LAYERS];
1208     u32 policer_timeunit;
1209 };
1210 
1211 /* NPC mbox message structs */
1212 
1213 #define NPC_MCAM_ENTRY_INVALID  0xFFFF
1214 #define NPC_MCAM_INVALID_MAP    0xFFFF
1215 
1216 /* NPC mailbox error codes
1217  * Range 701 - 800.
1218  */
1219 enum npc_af_status {
1220     NPC_MCAM_INVALID_REQ    = -701,
1221     NPC_MCAM_ALLOC_DENIED   = -702,
1222     NPC_MCAM_ALLOC_FAILED   = -703,
1223     NPC_MCAM_PERM_DENIED    = -704,
1224     NPC_FLOW_INTF_INVALID   = -707,
1225     NPC_FLOW_CHAN_INVALID   = -708,
1226     NPC_FLOW_NO_NIXLF   = -709,
1227     NPC_FLOW_NOT_SUPPORTED  = -710,
1228     NPC_FLOW_VF_PERM_DENIED = -711,
1229     NPC_FLOW_VF_NOT_INIT    = -712,
1230     NPC_FLOW_VF_OVERLAP = -713,
1231 };
1232 
1233 struct npc_mcam_alloc_entry_req {
1234     struct mbox_msghdr hdr;
1235 #define NPC_MAX_NONCONTIG_ENTRIES   256
1236     u8  contig;   /* Contiguous entries ? */
1237 #define NPC_MCAM_ANY_PRIO       0
1238 #define NPC_MCAM_LOWER_PRIO     1
1239 #define NPC_MCAM_HIGHER_PRIO        2
1240     u8  priority; /* Lower or higher w.r.t ref_entry */
1241     u16 ref_entry;
1242     u16 count;    /* Number of entries requested */
1243 };
1244 
1245 struct npc_mcam_alloc_entry_rsp {
1246     struct mbox_msghdr hdr;
1247     u16 entry; /* Entry allocated or start index if contiguous.
1248             * Invalid incase of non-contiguous.
1249             */
1250     u16 count; /* Number of entries allocated */
1251     u16 free_count; /* Number of entries available */
1252     u16 entry_list[NPC_MAX_NONCONTIG_ENTRIES];
1253 };
1254 
1255 struct npc_mcam_free_entry_req {
1256     struct mbox_msghdr hdr;
1257     u16 entry; /* Entry index to be freed */
1258     u8  all;   /* If all entries allocated to this PFVF to be freed */
1259 };
1260 
1261 struct mcam_entry {
1262 #define NPC_MAX_KWS_IN_KEY  7 /* Number of keywords in max keywidth */
1263     u64 kw[NPC_MAX_KWS_IN_KEY];
1264     u64 kw_mask[NPC_MAX_KWS_IN_KEY];
1265     u64 action;
1266     u64 vtag_action;
1267 };
1268 
1269 struct npc_mcam_write_entry_req {
1270     struct mbox_msghdr hdr;
1271     struct mcam_entry entry_data;
1272     u16 entry;   /* MCAM entry to write this match key */
1273     u16 cntr;    /* Counter for this MCAM entry */
1274     u8  intf;    /* Rx or Tx interface */
1275     u8  enable_entry;/* Enable this MCAM entry ? */
1276     u8  set_cntr;    /* Set counter for this entry ? */
1277 };
1278 
1279 /* Enable/Disable a given entry */
1280 struct npc_mcam_ena_dis_entry_req {
1281     struct mbox_msghdr hdr;
1282     u16 entry;
1283 };
1284 
1285 struct npc_mcam_shift_entry_req {
1286     struct mbox_msghdr hdr;
1287 #define NPC_MCAM_MAX_SHIFTS 64
1288     u16 curr_entry[NPC_MCAM_MAX_SHIFTS];
1289     u16 new_entry[NPC_MCAM_MAX_SHIFTS];
1290     u16 shift_count; /* Number of entries to shift */
1291 };
1292 
1293 struct npc_mcam_shift_entry_rsp {
1294     struct mbox_msghdr hdr;
1295     u16 failed_entry_idx; /* Index in 'curr_entry', not entry itself */
1296 };
1297 
1298 struct npc_mcam_alloc_counter_req {
1299     struct mbox_msghdr hdr;
1300     u8  contig; /* Contiguous counters ? */
1301 #define NPC_MAX_NONCONTIG_COUNTERS       64
1302     u16 count;  /* Number of counters requested */
1303 };
1304 
1305 struct npc_mcam_alloc_counter_rsp {
1306     struct mbox_msghdr hdr;
1307     u16 cntr;   /* Counter allocated or start index if contiguous.
1308              * Invalid incase of non-contiguous.
1309              */
1310     u16 count;  /* Number of counters allocated */
1311     u16 cntr_list[NPC_MAX_NONCONTIG_COUNTERS];
1312 };
1313 
1314 struct npc_mcam_oper_counter_req {
1315     struct mbox_msghdr hdr;
1316     u16 cntr;   /* Free a counter or clear/fetch it's stats */
1317 };
1318 
1319 struct npc_mcam_oper_counter_rsp {
1320     struct mbox_msghdr hdr;
1321     u64 stat;  /* valid only while fetching counter's stats */
1322 };
1323 
1324 struct npc_mcam_unmap_counter_req {
1325     struct mbox_msghdr hdr;
1326     u16 cntr;
1327     u16 entry; /* Entry and counter to be unmapped */
1328     u8  all;   /* Unmap all entries using this counter ? */
1329 };
1330 
1331 struct npc_mcam_alloc_and_write_entry_req {
1332     struct mbox_msghdr hdr;
1333     struct mcam_entry entry_data;
1334     u16 ref_entry;
1335     u8  priority;    /* Lower or higher w.r.t ref_entry */
1336     u8  intf;    /* Rx or Tx interface */
1337     u8  enable_entry;/* Enable this MCAM entry ? */
1338     u8  alloc_cntr;  /* Allocate counter and map ? */
1339 };
1340 
1341 struct npc_mcam_alloc_and_write_entry_rsp {
1342     struct mbox_msghdr hdr;
1343     u16 entry;
1344     u16 cntr;
1345 };
1346 
1347 struct npc_get_kex_cfg_rsp {
1348     struct mbox_msghdr hdr;
1349     u64 rx_keyx_cfg;   /* NPC_AF_INTF(0)_KEX_CFG */
1350     u64 tx_keyx_cfg;   /* NPC_AF_INTF(1)_KEX_CFG */
1351 #define NPC_MAX_INTF    2
1352 #define NPC_MAX_LID 8
1353 #define NPC_MAX_LT  16
1354 #define NPC_MAX_LD  2
1355 #define NPC_MAX_LFL 16
1356     /* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
1357     u64 kex_ld_flags[NPC_MAX_LD];
1358     /* NPC_AF_INTF(0..1)_LID(0..7)_LT(0..15)_LD(0..1)_CFG */
1359     u64 intf_lid_lt_ld[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT][NPC_MAX_LD];
1360     /* NPC_AF_INTF(0..1)_LDATA(0..1)_FLAGS(0..15)_CFG */
1361     u64 intf_ld_flags[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
1362 #define MKEX_NAME_LEN 128
1363     u8 mkex_pfl_name[MKEX_NAME_LEN];
1364 };
1365 
1366 struct flow_msg {
1367     unsigned char dmac[6];
1368     unsigned char smac[6];
1369     __be16 etype;
1370     __be16 vlan_etype;
1371     __be16 vlan_tci;
1372     union {
1373         __be32 ip4src;
1374         __be32 ip6src[4];
1375     };
1376     union {
1377         __be32 ip4dst;
1378         __be32 ip6dst[4];
1379     };
1380     u8 tos;
1381     u8 ip_ver;
1382     u8 ip_proto;
1383     u8 tc;
1384     __be16 sport;
1385     __be16 dport;
1386 };
1387 
1388 struct npc_install_flow_req {
1389     struct mbox_msghdr hdr;
1390     struct flow_msg packet;
1391     struct flow_msg mask;
1392     u64 features;
1393     u16 entry;
1394     u16 channel;
1395     u16 chan_mask;
1396     u8 intf;
1397     u8 set_cntr; /* If counter is available set counter for this entry ? */
1398     u8 default_rule;
1399     u8 append; /* overwrite(0) or append(1) flow to default rule? */
1400     u16 vf;
1401     /* action */
1402     u32 index;
1403     u16 match_id;
1404     u8 flow_key_alg;
1405     u8 op;
1406     /* vtag rx action */
1407     u8 vtag0_type;
1408     u8 vtag0_valid;
1409     u8 vtag1_type;
1410     u8 vtag1_valid;
1411     /* vtag tx action */
1412     u16 vtag0_def;
1413     u8  vtag0_op;
1414     u16 vtag1_def;
1415     u8  vtag1_op;
1416 };
1417 
1418 struct npc_install_flow_rsp {
1419     struct mbox_msghdr hdr;
1420     int counter; /* negative if no counter else counter number */
1421 };
1422 
1423 struct npc_delete_flow_req {
1424     struct mbox_msghdr hdr;
1425     u16 entry;
1426     u16 start;/*Disable range of entries */
1427     u16 end;
1428     u8 all; /* PF + VFs */
1429 };
1430 
1431 struct npc_mcam_read_entry_req {
1432     struct mbox_msghdr hdr;
1433     u16 entry;   /* MCAM entry to read */
1434 };
1435 
1436 struct npc_mcam_read_entry_rsp {
1437     struct mbox_msghdr hdr;
1438     struct mcam_entry entry_data;
1439     u8 intf;
1440     u8 enable;
1441 };
1442 
1443 struct npc_mcam_read_base_rule_rsp {
1444     struct mbox_msghdr hdr;
1445     struct mcam_entry entry;
1446 };
1447 
1448 struct npc_mcam_get_stats_req {
1449     struct mbox_msghdr hdr;
1450     u16 entry; /* mcam entry */
1451 };
1452 
1453 struct npc_mcam_get_stats_rsp {
1454     struct mbox_msghdr hdr;
1455     u64 stat;  /* counter stats */
1456     u8 stat_ena; /* enabled */
1457 };
1458 
1459 struct npc_get_secret_key_req {
1460     struct mbox_msghdr hdr;
1461     u8 intf;
1462 };
1463 
1464 struct npc_get_secret_key_rsp {
1465     struct mbox_msghdr hdr;
1466     u64 secret_key[3];
1467 };
1468 
1469 enum ptp_op {
1470     PTP_OP_ADJFINE = 0,
1471     PTP_OP_GET_CLOCK = 1,
1472     PTP_OP_GET_TSTMP = 2,
1473     PTP_OP_SET_THRESH = 3,
1474 };
1475 
1476 struct ptp_req {
1477     struct mbox_msghdr hdr;
1478     u8 op;
1479     s64 scaled_ppm;
1480     u64 thresh;
1481 };
1482 
1483 struct ptp_rsp {
1484     struct mbox_msghdr hdr;
1485     u64 clk;
1486 };
1487 
1488 struct set_vf_perm  {
1489     struct  mbox_msghdr hdr;
1490     u16 vf;
1491 #define RESET_VF_PERM       BIT_ULL(0)
1492 #define VF_TRUSTED      BIT_ULL(1)
1493     u64 flags;
1494 };
1495 
1496 struct lmtst_tbl_setup_req {
1497     struct mbox_msghdr hdr;
1498     u64 dis_sched_early_comp :1;
1499     u64 sch_ena      :1;
1500     u64 dis_line_pref    :1;
1501     u64 ssow_pf_func     :13;
1502     u16 base_pcifunc;
1503     u8  use_local_lmt_region;
1504     u64 lmt_iova;
1505     u64 rsvd[4];
1506 };
1507 
1508 /* CPT mailbox error codes
1509  * Range 901 - 1000.
1510  */
1511 enum cpt_af_status {
1512     CPT_AF_ERR_PARAM        = -901,
1513     CPT_AF_ERR_GRP_INVALID      = -902,
1514     CPT_AF_ERR_LF_INVALID       = -903,
1515     CPT_AF_ERR_ACCESS_DENIED    = -904,
1516     CPT_AF_ERR_SSO_PF_FUNC_INVALID  = -905,
1517     CPT_AF_ERR_NIX_PF_FUNC_INVALID  = -906,
1518     CPT_AF_ERR_INLINE_IPSEC_INB_ENA = -907,
1519     CPT_AF_ERR_INLINE_IPSEC_OUT_ENA = -908
1520 };
1521 
1522 /* CPT mbox message formats */
1523 struct cpt_rd_wr_reg_msg {
1524     struct mbox_msghdr hdr;
1525     u64 reg_offset;
1526     u64 *ret_val;
1527     u64 val;
1528     u8 is_write;
1529     int blkaddr;
1530 };
1531 
1532 struct cpt_lf_alloc_req_msg {
1533     struct mbox_msghdr hdr;
1534     u16 nix_pf_func;
1535     u16 sso_pf_func;
1536     u16 eng_grpmsk;
1537     int blkaddr;
1538 };
1539 
1540 #define CPT_INLINE_INBOUND      0
1541 #define CPT_INLINE_OUTBOUND     1
1542 
1543 /* Mailbox message request format for CPT IPsec
1544  * inline inbound and outbound configuration.
1545  */
1546 struct cpt_inline_ipsec_cfg_msg {
1547     struct mbox_msghdr hdr;
1548     u8 enable;
1549     u8 slot;
1550     u8 dir;
1551     u8 sso_pf_func_ovrd;
1552     u16 sso_pf_func; /* inbound path SSO_PF_FUNC */
1553     u16 nix_pf_func; /* outbound path NIX_PF_FUNC */
1554 };
1555 
1556 /* Mailbox message request and response format for CPT stats. */
1557 struct cpt_sts_req {
1558     struct mbox_msghdr hdr;
1559     u8 blkaddr;
1560 };
1561 
1562 struct cpt_sts_rsp {
1563     struct mbox_msghdr hdr;
1564     u64 inst_req_pc;
1565     u64 inst_lat_pc;
1566     u64 rd_req_pc;
1567     u64 rd_lat_pc;
1568     u64 rd_uc_pc;
1569     u64 active_cycles_pc;
1570     u64 ctx_mis_pc;
1571     u64 ctx_hit_pc;
1572     u64 ctx_aop_pc;
1573     u64 ctx_aop_lat_pc;
1574     u64 ctx_ifetch_pc;
1575     u64 ctx_ifetch_lat_pc;
1576     u64 ctx_ffetch_pc;
1577     u64 ctx_ffetch_lat_pc;
1578     u64 ctx_wback_pc;
1579     u64 ctx_wback_lat_pc;
1580     u64 ctx_psh_pc;
1581     u64 ctx_psh_lat_pc;
1582     u64 ctx_err;
1583     u64 ctx_enc_id;
1584     u64 ctx_flush_timer;
1585     u64 rxc_time;
1586     u64 rxc_time_cfg;
1587     u64 rxc_active_sts;
1588     u64 rxc_zombie_sts;
1589     u64 busy_sts_ae;
1590     u64 free_sts_ae;
1591     u64 busy_sts_se;
1592     u64 free_sts_se;
1593     u64 busy_sts_ie;
1594     u64 free_sts_ie;
1595     u64 exe_err_info;
1596     u64 cptclk_cnt;
1597     u64 diag;
1598     u64 rxc_dfrg;
1599     u64 x2p_link_cfg0;
1600     u64 x2p_link_cfg1;
1601 };
1602 
1603 /* Mailbox message request format to configure reassembly timeout. */
1604 struct cpt_rxc_time_cfg_req {
1605     struct mbox_msghdr hdr;
1606     int blkaddr;
1607     u32 step;
1608     u16 zombie_thres;
1609     u16 zombie_limit;
1610     u16 active_thres;
1611     u16 active_limit;
1612 };
1613 
1614 /* Mailbox message request format to request for CPT_INST_S lmtst. */
1615 struct cpt_inst_lmtst_req {
1616     struct mbox_msghdr hdr;
1617     u64 inst[8];
1618     u64 rsvd;
1619 };
1620 
1621 struct sdp_node_info {
1622     /* Node to which this PF belons to */
1623     u8 node_id;
1624     u8 max_vfs;
1625     u8 num_pf_rings;
1626     u8 pf_srn;
1627 #define SDP_MAX_VFS 128
1628     u8 vf_rings[SDP_MAX_VFS];
1629 };
1630 
1631 struct sdp_chan_info_msg {
1632     struct mbox_msghdr hdr;
1633     struct sdp_node_info info;
1634 };
1635 
1636 struct sdp_get_chan_info_msg {
1637     struct mbox_msghdr hdr;
1638     u16 chan_base;
1639     u16 num_chan;
1640 };
1641 
1642 /* CGX mailbox error codes
1643  * Range 1101 - 1200.
1644  */
1645 enum cgx_af_status {
1646     LMAC_AF_ERR_INVALID_PARAM   = -1101,
1647     LMAC_AF_ERR_PF_NOT_MAPPED   = -1102,
1648     LMAC_AF_ERR_PERM_DENIED     = -1103,
1649     LMAC_AF_ERR_PFC_ENADIS_PERM_DENIED       = -1104,
1650     LMAC_AF_ERR_8023PAUSE_ENADIS_PERM_DENIED = -1105,
1651     LMAC_AF_ERR_CMD_TIMEOUT = -1106,
1652     LMAC_AF_ERR_FIRMWARE_DATA_NOT_MAPPED = -1107,
1653     LMAC_AF_ERR_EXACT_MATCH_TBL_ADD_FAILED = -1108,
1654     LMAC_AF_ERR_EXACT_MATCH_TBL_DEL_FAILED = -1109,
1655     LMAC_AF_ERR_EXACT_MATCH_TBL_LOOK_UP_FAILED = -1110,
1656 };
1657 
1658 #endif /* MBOX_H */
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