octeontx2/af/common.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Marvell RVU Admin Function driver
0003  *
0004  * Copyright (C) 2018 Marvell.
0005  */
0006
0007 #ifndef COMMON_H
0008 #define COMMON_H
0009
0010 #include "rvu_struct.h"
0011
0012 #define OTX2_ALIGN          128  /* Align to cacheline */
0013
0014 #define Q_SIZE_16       0ULL /* 16 entries */
0015 #define Q_SIZE_64       1ULL /* 64 entries */
0016 #define Q_SIZE_256      2ULL
0017 #define Q_SIZE_1K       3ULL
0018 #define Q_SIZE_4K       4ULL
0019 #define Q_SIZE_16K      5ULL
0020 #define Q_SIZE_64K      6ULL
0021 #define Q_SIZE_256K     7ULL
0022 #define Q_SIZE_1M       8ULL /* Million entries */
0023 #define Q_SIZE_MIN      Q_SIZE_16
0024 #define Q_SIZE_MAX      Q_SIZE_1M
0025
0026 #define Q_COUNT(x)      (16ULL << (2 * x))
0027 #define Q_SIZE(x, n)        ((ilog2(x) - (n)) / 2)
0028
0029 /* Admin queue info */
0030
0031 /* Since we intend to add only one instruction at a time,
0032  * keep queue size to it's minimum.
0033  */
0034 #define AQ_SIZE         Q_SIZE_16
0035 /* HW head & tail pointer mask */
0036 #define AQ_PTR_MASK     0xFFFFF
0037
0038 struct qmem {
0039     void            *base;
0040     dma_addr_t  iova;
0041     int     alloc_sz;
0042     u16     entry_sz;
0043     u8      align;
0044     u32     qsize;
0045 };
0046
0047 static inline int qmem_alloc(struct device *dev, struct qmem **q,
0048                  int qsize, int entry_sz)
0049 {
0050     struct qmem *qmem;
0051     int aligned_addr;
0052
0053     if (!qsize)
0054         return -EINVAL;
0055
0056     *q = devm_kzalloc(dev, sizeof(*qmem), GFP_KERNEL);
0057     if (!*q)
0058         return -ENOMEM;
0059     qmem = *q;
0060
0061     qmem->entry_sz = entry_sz;
0062     qmem->alloc_sz = (qsize * entry_sz) + OTX2_ALIGN;
0063     qmem->base = dma_alloc_attrs(dev, qmem->alloc_sz, &qmem->iova,
0064                      GFP_KERNEL, DMA_ATTR_FORCE_CONTIGUOUS);
0065     if (!qmem->base)
0066         return -ENOMEM;
0067
0068     qmem->qsize = qsize;
0069
0070     aligned_addr = ALIGN((u64)qmem->iova, OTX2_ALIGN);
0071     qmem->align = (aligned_addr - qmem->iova);
0072     qmem->base += qmem->align;
0073     qmem->iova += qmem->align;
0074     return 0;
0075 }
0076
0077 static inline void qmem_free(struct device *dev, struct qmem *qmem)
0078 {
0079     if (!qmem)
0080         return;
0081
0082     if (qmem->base)
0083         dma_free_attrs(dev, qmem->alloc_sz,
0084                    qmem->base - qmem->align,
0085                    qmem->iova - qmem->align,
0086                    DMA_ATTR_FORCE_CONTIGUOUS);
0087     devm_kfree(dev, qmem);
0088 }
0089
0090 struct admin_queue {
0091     struct qmem *inst;
0092     struct qmem *res;
0093     spinlock_t  lock; /* Serialize inst enqueue from PFs */
0094 };
0095
0096 /* NPA aura count */
0097 enum npa_aura_sz {
0098     NPA_AURA_SZ_0,
0099     NPA_AURA_SZ_128,
0100     NPA_AURA_SZ_256,
0101     NPA_AURA_SZ_512,
0102     NPA_AURA_SZ_1K,
0103     NPA_AURA_SZ_2K,
0104     NPA_AURA_SZ_4K,
0105     NPA_AURA_SZ_8K,
0106     NPA_AURA_SZ_16K,
0107     NPA_AURA_SZ_32K,
0108     NPA_AURA_SZ_64K,
0109     NPA_AURA_SZ_128K,
0110     NPA_AURA_SZ_256K,
0111     NPA_AURA_SZ_512K,
0112     NPA_AURA_SZ_1M,
0113     NPA_AURA_SZ_MAX,
0114 };
0115
0116 #define NPA_AURA_COUNT(x)   (1ULL << ((x) + 6))
0117
0118 /* NPA AQ result structure for init/read/write of aura HW contexts */
0119 struct npa_aq_aura_res {
0120     struct  npa_aq_res_s    res;
0121     struct  npa_aura_s  aura_ctx;
0122     struct  npa_aura_s  ctx_mask;
0123 };
0124
0125 /* NPA AQ result structure for init/read/write of pool HW contexts */
0126 struct npa_aq_pool_res {
0127     struct  npa_aq_res_s    res;
0128     struct  npa_pool_s  pool_ctx;
0129     struct  npa_pool_s  ctx_mask;
0130 };
0131
0132 /* NIX Transmit schedulers */
0133 enum nix_scheduler {
0134     NIX_TXSCH_LVL_SMQ = 0x0,
0135     NIX_TXSCH_LVL_MDQ = 0x0,
0136     NIX_TXSCH_LVL_TL4 = 0x1,
0137     NIX_TXSCH_LVL_TL3 = 0x2,
0138     NIX_TXSCH_LVL_TL2 = 0x3,
0139     NIX_TXSCH_LVL_TL1 = 0x4,
0140     NIX_TXSCH_LVL_CNT = 0x5,
0141 };
0142
0143 #define TXSCH_RR_QTM_MAX        ((1 << 24) - 1)
0144 #define TXSCH_TL1_DFLT_RR_QTM       TXSCH_RR_QTM_MAX
0145 #define TXSCH_TL1_DFLT_RR_PRIO      (0x1ull)
0146 #define CN10K_MAX_DWRR_WEIGHT          16384 /* Weight is 14bit on CN10K */
0147
0148 /* Min/Max packet sizes, excluding FCS */
0149 #define NIC_HW_MIN_FRS          40
0150 #define NIC_HW_MAX_FRS          9212
0151 #define SDP_HW_MAX_FRS          65535
0152 #define CN10K_LMAC_LINK_MAX_FRS     16380 /* 16k - FCS */
0153 #define CN10K_LBK_LINK_MAX_FRS      65535 /* 64k */
0154
0155 /* NIX RX action operation*/
0156 #define NIX_RX_ACTIONOP_DROP        (0x0ull)
0157 #define NIX_RX_ACTIONOP_UCAST       (0x1ull)
0158 #define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)
0159 #define NIX_RX_ACTIONOP_MCAST       (0x3ull)
0160 #define NIX_RX_ACTIONOP_RSS     (0x4ull)
0161 /* Use the RX action set in the default unicast entry */
0162 #define NIX_RX_ACTION_DEFAULT       (0xfull)
0163
0164 /* NIX TX action operation*/
0165 #define NIX_TX_ACTIONOP_DROP        (0x0ull)
0166 #define NIX_TX_ACTIONOP_UCAST_DEFAULT   (0x1ull)
0167 #define NIX_TX_ACTIONOP_UCAST_CHAN  (0x2ull)
0168 #define NIX_TX_ACTIONOP_MCAST       (0x3ull)
0169 #define NIX_TX_ACTIONOP_DROP_VIOL   (0x5ull)
0170
0171 #define NPC_MCAM_KEY_X1         0
0172 #define NPC_MCAM_KEY_X2         1
0173 #define NPC_MCAM_KEY_X4         2
0174
0175 #define NIX_INTFX_RX(a)         (0x0ull | (a) << 1)
0176 #define NIX_INTFX_TX(a)         (0x1ull | (a) << 1)
0177
0178 /* Default interfaces are NIX0_RX and NIX0_TX */
0179 #define NIX_INTF_RX         NIX_INTFX_RX(0)
0180 #define NIX_INTF_TX         NIX_INTFX_TX(0)
0181
0182 #define NIX_INTF_TYPE_CGX       0
0183 #define NIX_INTF_TYPE_LBK       1
0184 #define NIX_INTF_TYPE_SDP       2
0185
0186 #define MAX_LMAC_PKIND          12
0187 #define NIX_LINK_CGX_LMAC(a, b)     (0 + 4 * (a) + (b))
0188 #define NIX_LINK_LBK(a)         (12 + (a))
0189 #define NIX_CHAN_CGX_LMAC_CHX(a, b, c)  (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
0190 #define NIX_CHAN_LBK_CHX(a, b)      (0 + 0x100 * (a) + (b))
0191 #define NIX_CHAN_SDP_CH_START          (0x700ull)
0192 #define NIX_CHAN_SDP_CHX(a)            (NIX_CHAN_SDP_CH_START + (a))
0193 #define NIX_CHAN_SDP_NUM_CHANS      256
0194 #define NIX_CHAN_CPT_CH_START          (0x800ull)
0195
0196 /* The mask is to extract lower 10-bits of channel number
0197  * which CPT will pass to X2P.
0198  */
0199 #define NIX_CHAN_CPT_X2P_MASK          (0x3ffull)
0200
0201 /* NIX LSO format indices.
0202  * As of now TSO is the only one using, so statically assigning indices.
0203  */
0204 #define NIX_LSO_FORMAT_IDX_TSOV4    0
0205 #define NIX_LSO_FORMAT_IDX_TSOV6    1
0206
0207 /* RSS info */
0208 #define MAX_RSS_GROUPS          8
0209 /* Group 0 has to be used in default pkt forwarding MCAM entries
0210  * reserved for NIXLFs. Groups 1-7 can be used for RSS for ntuple
0211  * filters.
0212  */
0213 #define DEFAULT_RSS_CONTEXT_GROUP   0
0214 #define MAX_RSS_INDIR_TBL_SIZE      256 /* 1 << Max adder bits */
0215
0216 /* NDC info */
0217 enum ndc_idx_e {
0218     NIX0_RX = 0x0,
0219     NIX0_TX = 0x1,
0220     NPA0_U  = 0x2,
0221     NIX1_RX = 0x4,
0222     NIX1_TX = 0x5,
0223 };
0224
0225 enum ndc_ctype_e {
0226     CACHING = 0x0,
0227     BYPASS = 0x1,
0228 };
0229
0230 #define NDC_MAX_PORT 6
0231 #define NDC_READ_TRANS 0
0232 #define NDC_WRITE_TRANS 1
0233
0234 #endif /* COMMON_H */