octeontx2/af/cgx_fw_if.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Marvell OcteonTx2 CGX driver
0003  *
0004  * Copyright (C) 2018 Marvell.
0005  *
0006  */
0007
0008 #ifndef __CGX_FW_INTF_H__
0009 #define __CGX_FW_INTF_H__
0010
0011 #include <linux/bitops.h>
0012 #include <linux/bitfield.h>
0013
0014 #define CGX_FIRMWARE_MAJOR_VER      1
0015 #define CGX_FIRMWARE_MINOR_VER      0
0016
0017 #define CGX_EVENT_ACK                   1UL
0018
0019 /* CGX error types. set for cmd response status as CGX_STAT_FAIL */
0020 enum cgx_error_type {
0021     CGX_ERR_NONE,
0022     CGX_ERR_LMAC_NOT_ENABLED,
0023     CGX_ERR_LMAC_MODE_INVALID,
0024     CGX_ERR_REQUEST_ID_INVALID,
0025     CGX_ERR_PREV_ACK_NOT_CLEAR,
0026     CGX_ERR_PHY_LINK_DOWN,
0027     CGX_ERR_PCS_RESET_FAIL,
0028     CGX_ERR_AN_CPT_FAIL,
0029     CGX_ERR_TX_NOT_IDLE,
0030     CGX_ERR_RX_NOT_IDLE,
0031     CGX_ERR_SPUX_BR_BLKLOCK_FAIL,
0032     CGX_ERR_SPUX_RX_ALIGN_FAIL,
0033     CGX_ERR_SPUX_TX_FAULT,
0034     CGX_ERR_SPUX_RX_FAULT,
0035     CGX_ERR_SPUX_RESET_FAIL,
0036     CGX_ERR_SPUX_AN_RESET_FAIL,
0037     CGX_ERR_SPUX_USX_AN_RESET_FAIL,
0038     CGX_ERR_SMUX_RX_LINK_NOT_OK,
0039     CGX_ERR_PCS_RECV_LINK_FAIL,
0040     CGX_ERR_TRAINING_FAIL,
0041     CGX_ERR_RX_EQU_FAIL,
0042     CGX_ERR_SPUX_BER_FAIL,
0043     CGX_ERR_SPUX_RSFEC_ALGN_FAIL,
0044     CGX_ERR_SPUX_MARKER_LOCK_FAIL,
0045     CGX_ERR_SET_FEC_INVALID,
0046     CGX_ERR_SET_FEC_FAIL,
0047     CGX_ERR_MODULE_INVALID,
0048     CGX_ERR_MODULE_NOT_PRESENT,
0049     CGX_ERR_SPEED_CHANGE_INVALID,
0050 };
0051
0052 /* LINK speed types */
0053 enum cgx_link_speed {
0054     CGX_LINK_NONE,
0055     CGX_LINK_10M,
0056     CGX_LINK_100M,
0057     CGX_LINK_1G,
0058     CGX_LINK_2HG,
0059     CGX_LINK_5G,
0060     CGX_LINK_10G,
0061     CGX_LINK_20G,
0062     CGX_LINK_25G,
0063     CGX_LINK_40G,
0064     CGX_LINK_50G,
0065     CGX_LINK_80G,
0066     CGX_LINK_100G,
0067     CGX_LINK_SPEED_MAX,
0068 };
0069
0070 enum CGX_MODE_ {
0071     CGX_MODE_SGMII,
0072     CGX_MODE_1000_BASEX,
0073     CGX_MODE_QSGMII,
0074     CGX_MODE_10G_C2C,
0075     CGX_MODE_10G_C2M,
0076     CGX_MODE_10G_KR,
0077     CGX_MODE_20G_C2C,
0078     CGX_MODE_25G_C2C,
0079     CGX_MODE_25G_C2M,
0080     CGX_MODE_25G_2_C2C,
0081     CGX_MODE_25G_CR,
0082     CGX_MODE_25G_KR,
0083     CGX_MODE_40G_C2C,
0084     CGX_MODE_40G_C2M,
0085     CGX_MODE_40G_CR4,
0086     CGX_MODE_40G_KR4,
0087     CGX_MODE_40GAUI_C2C,
0088     CGX_MODE_50G_C2C,
0089     CGX_MODE_50G_C2M,
0090     CGX_MODE_50G_4_C2C,
0091     CGX_MODE_50G_CR,
0092     CGX_MODE_50G_KR,
0093     CGX_MODE_80GAUI_C2C,
0094     CGX_MODE_100G_C2C,
0095     CGX_MODE_100G_C2M,
0096     CGX_MODE_100G_CR4,
0097     CGX_MODE_100G_KR4,
0098     CGX_MODE_MAX /* = 29 */
0099 };
0100 /* REQUEST ID types. Input to firmware */
0101 enum cgx_cmd_id {
0102     CGX_CMD_NONE,
0103     CGX_CMD_GET_FW_VER,
0104     CGX_CMD_GET_MAC_ADDR,
0105     CGX_CMD_SET_MTU,
0106     CGX_CMD_GET_LINK_STS,       /* optional to user */
0107     CGX_CMD_LINK_BRING_UP,
0108     CGX_CMD_LINK_BRING_DOWN,
0109     CGX_CMD_INTERNAL_LBK,
0110     CGX_CMD_EXTERNAL_LBK,
0111     CGX_CMD_HIGIG,
0112     CGX_CMD_LINK_STAT_CHANGE,
0113     CGX_CMD_MODE_CHANGE,        /* hot plug support */
0114     CGX_CMD_INTF_SHUTDOWN,
0115     CGX_CMD_GET_MKEX_PRFL_SIZE,
0116     CGX_CMD_GET_MKEX_PRFL_ADDR,
0117     CGX_CMD_GET_FWD_BASE,       /* get base address of shared FW data */
0118     CGX_CMD_GET_LINK_MODES,     /* Supported Link Modes */
0119     CGX_CMD_SET_LINK_MODE,
0120     CGX_CMD_GET_SUPPORTED_FEC,
0121     CGX_CMD_SET_FEC,
0122     CGX_CMD_GET_AN,
0123     CGX_CMD_SET_AN,
0124     CGX_CMD_GET_ADV_LINK_MODES,
0125     CGX_CMD_GET_ADV_FEC,
0126     CGX_CMD_GET_PHY_MOD_TYPE, /* line-side modulation type: NRZ or PAM4 */
0127     CGX_CMD_SET_PHY_MOD_TYPE,
0128     CGX_CMD_PRBS,
0129     CGX_CMD_DISPLAY_EYE,
0130     CGX_CMD_GET_PHY_FEC_STATS,
0131 };
0132
0133 /* async event ids */
0134 enum cgx_evt_id {
0135     CGX_EVT_NONE,
0136     CGX_EVT_LINK_CHANGE,
0137 };
0138
0139 /* event types - cause of interrupt */
0140 enum cgx_evt_type {
0141     CGX_EVT_ASYNC,
0142     CGX_EVT_CMD_RESP
0143 };
0144
0145 enum cgx_stat {
0146     CGX_STAT_SUCCESS,
0147     CGX_STAT_FAIL
0148 };
0149
0150 enum cgx_cmd_own {
0151     CGX_CMD_OWN_NS,
0152     CGX_CMD_OWN_FIRMWARE,
0153 };
0154
0155 /* m - bit mask
0156  * y - value to be written in the bitrange
0157  * x - input value whose bitrange to be modified
0158  */
0159 #define FIELD_SET(m, y, x)      \
0160     (((x) & ~(m)) |         \
0161     FIELD_PREP((m), (y)))
0162
0163 /* scratchx(0) CSR used for ATF->non-secure SW communication.
0164  * This acts as the status register
0165  * Provides details on command ack/status, command response, error details
0166  */
0167 #define EVTREG_ACK      BIT_ULL(0)
0168 #define EVTREG_EVT_TYPE     BIT_ULL(1)
0169 #define EVTREG_STAT     BIT_ULL(2)
0170 #define EVTREG_ID       GENMASK_ULL(8, 3)
0171
0172 /* Response to command IDs with command status as CGX_STAT_FAIL
0173  *
0174  * Not applicable for commands :
0175  * CGX_CMD_LINK_BRING_UP/DOWN/CGX_EVT_LINK_CHANGE
0176  */
0177 #define EVTREG_ERRTYPE      GENMASK_ULL(18, 9)
0178
0179 /* Response to cmd ID as CGX_CMD_GET_FW_VER with cmd status as
0180  * CGX_STAT_SUCCESS
0181  */
0182 #define RESP_MAJOR_VER      GENMASK_ULL(12, 9)
0183 #define RESP_MINOR_VER      GENMASK_ULL(16, 13)
0184
0185 /* Response to cmd ID as CGX_CMD_GET_MAC_ADDR with cmd status as
0186  * CGX_STAT_SUCCESS
0187  */
0188 #define RESP_MAC_ADDR       GENMASK_ULL(56, 9)
0189
0190 /* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_SIZE with cmd status as
0191  * CGX_STAT_SUCCESS
0192  */
0193 #define RESP_MKEX_PRFL_SIZE     GENMASK_ULL(63, 9)
0194
0195 /* Response to cmd ID as CGX_CMD_GET_MKEX_PRFL_ADDR with cmd status as
0196  * CGX_STAT_SUCCESS
0197  */
0198 #define RESP_MKEX_PRFL_ADDR     GENMASK_ULL(63, 9)
0199
0200 /* Response to cmd ID as CGX_CMD_GET_FWD_BASE with cmd status as
0201  * CGX_STAT_SUCCESS
0202  */
0203 #define RESP_FWD_BASE       GENMASK_ULL(56, 9)
0204 #define RESP_LINKSTAT_LMAC_TYPE                GENMASK_ULL(35, 28)
0205
0206 /* Response to cmd ID - CGX_CMD_LINK_BRING_UP/DOWN, event ID CGX_EVT_LINK_CHANGE
0207  * status can be either CGX_STAT_FAIL or CGX_STAT_SUCCESS
0208  *
0209  * In case of CGX_STAT_FAIL, it indicates CGX configuration failed
0210  * when processing link up/down/change command.
0211  * Both err_type and current link status will be updated
0212  *
0213  * In case of CGX_STAT_SUCCESS, err_type will be CGX_ERR_NONE and current
0214  * link status will be updated
0215  */
0216 struct cgx_lnk_sts {
0217     uint64_t reserved1:9;
0218     uint64_t link_up:1;
0219     uint64_t full_duplex:1;
0220     uint64_t speed:4;       /* cgx_link_speed */
0221     uint64_t err_type:10;
0222     uint64_t an:1;          /* AN supported or not */
0223     uint64_t fec:2;         /* FEC type if enabled, if not 0 */
0224     uint64_t port:8;
0225     uint64_t reserved2:28;
0226 };
0227
0228 #define RESP_LINKSTAT_UP        GENMASK_ULL(9, 9)
0229 #define RESP_LINKSTAT_FDUPLEX       GENMASK_ULL(10, 10)
0230 #define RESP_LINKSTAT_SPEED     GENMASK_ULL(14, 11)
0231 #define RESP_LINKSTAT_ERRTYPE       GENMASK_ULL(24, 15)
0232 #define RESP_LINKSTAT_AN        GENMASK_ULL(25, 25)
0233 #define RESP_LINKSTAT_FEC       GENMASK_ULL(27, 26)
0234 #define RESP_LINKSTAT_PORT      GENMASK_ULL(35, 28)
0235
0236 /* scratchx(1) CSR used for non-secure SW->ATF communication
0237  * This CSR acts as a command register
0238  */
0239 #define CMDREG_OWN  BIT_ULL(0)
0240 #define CMDREG_ID   GENMASK_ULL(7, 2)
0241
0242 /* Any command using enable/disable as an argument need
0243  * to set this bitfield.
0244  * Ex: Loopback, HiGig...
0245  */
0246 #define CMDREG_ENABLE   BIT_ULL(8)
0247
0248 /* command argument to be passed for cmd ID - CGX_CMD_SET_MTU */
0249 #define CMDMTU_SIZE GENMASK_ULL(23, 8)
0250
0251 /* command argument to be passed for cmd ID - CGX_CMD_LINK_CHANGE */
0252 #define CMDLINKCHANGE_LINKUP    BIT_ULL(8)
0253 #define CMDLINKCHANGE_FULLDPLX  BIT_ULL(9)
0254 #define CMDLINKCHANGE_SPEED GENMASK_ULL(13, 10)
0255
0256 #define CMDSETFEC           GENMASK_ULL(9, 8)
0257 /* command argument to be passed for cmd ID - CGX_CMD_MODE_CHANGE */
0258 #define CMDMODECHANGE_SPEED     GENMASK_ULL(11, 8)
0259 #define CMDMODECHANGE_DUPLEX        GENMASK_ULL(12, 12)
0260 #define CMDMODECHANGE_AN        GENMASK_ULL(13, 13)
0261 #define CMDMODECHANGE_PORT      GENMASK_ULL(21, 14)
0262 #define CMDMODECHANGE_FLAGS     GENMASK_ULL(63, 22)
0263
0264 /* LINK_BRING_UP command timeout */
0265 #define LINKCFG_TIMEOUT     GENMASK_ULL(21, 8)
0266 #endif /* __CGX_FW_INTF_H__ */