octeontx2/af/cgx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Marvell OcteonTx2 CGX driver
0003  *
0004  * Copyright (C) 2018 Marvell.
0005  *
0006  */
0007
0008 #ifndef CGX_H
0009 #define CGX_H
0010
0011 #include "mbox.h"
0012 #include "cgx_fw_if.h"
0013 #include "rpm.h"
0014
0015  /* PCI device IDs */
0016 #define PCI_DEVID_OCTEONTX2_CGX     0xA059
0017
0018 /* PCI BAR nos */
0019 #define PCI_CFG_REG_BAR_NUM     0
0020
0021 #define CGX_ID_MASK         0x7
0022 #define MAX_LMAC_PER_CGX        4
0023 #define MAX_DMAC_ENTRIES_PER_CGX    32
0024 #define CGX_FIFO_LEN            65536 /* 64K for both Rx & Tx */
0025 #define CGX_OFFSET(x)           ((x) * MAX_LMAC_PER_CGX)
0026
0027 /* Registers */
0028 #define CGXX_CMRX_CFG           0x00
0029 #define CMR_P2X_SEL_MASK        GENMASK_ULL(61, 59)
0030 #define CMR_P2X_SEL_SHIFT       59ULL
0031 #define CMR_P2X_SEL_NIX0        1ULL
0032 #define CMR_P2X_SEL_NIX1        2ULL
0033 #define CMR_EN              BIT_ULL(55)
0034 #define DATA_PKT_TX_EN          BIT_ULL(53)
0035 #define DATA_PKT_RX_EN          BIT_ULL(54)
0036 #define CGX_LMAC_TYPE_SHIFT     40
0037 #define CGX_LMAC_TYPE_MASK      0xF
0038 #define CGXX_CMRX_INT           0x040
0039 #define FW_CGX_INT          BIT_ULL(1)
0040 #define CGXX_CMRX_INT_ENA_W1S       0x058
0041 #define CGXX_CMRX_RX_ID_MAP     0x060
0042 #define CGXX_CMRX_RX_STAT0      0x070
0043 #define CGXX_CMRX_RX_LMACS      0x128
0044 #define CGXX_CMRX_RX_DMAC_CTL0      (0x1F8 + mac_ops->csr_offset)
0045 #define CGX_DMAC_CTL0_CAM_ENABLE    BIT_ULL(3)
0046 #define CGX_DMAC_CAM_ACCEPT     BIT_ULL(3)
0047 #define CGX_DMAC_MCAST_MODE_CAM     BIT_ULL(2)
0048 #define CGX_DMAC_MCAST_MODE     BIT_ULL(1)
0049 #define CGX_DMAC_BCAST_MODE     BIT_ULL(0)
0050 #define CGXX_CMRX_RX_DMAC_CAM0      (0x200 + mac_ops->csr_offset)
0051 #define CGX_DMAC_CAM_ADDR_ENABLE    BIT_ULL(48)
0052 #define CGX_DMAC_CAM_ENTRY_LMACID   GENMASK_ULL(50, 49)
0053 #define CGXX_CMRX_RX_DMAC_CAM1      0x400
0054 #define CGX_RX_DMAC_ADR_MASK        GENMASK_ULL(47, 0)
0055 #define CGXX_CMRX_TX_STAT0      0x700
0056 #define CGXX_SCRATCH0_REG       0x1050
0057 #define CGXX_SCRATCH1_REG       0x1058
0058 #define CGX_CONST           0x2000
0059 #define CGX_CONST_RXFIFO_SIZE           GENMASK_ULL(23, 0)
0060 #define CGXX_SPUX_CONTROL1      0x10000
0061 #define CGXX_SPUX_LNX_FEC_CORR_BLOCKS   0x10700
0062 #define CGXX_SPUX_LNX_FEC_UNCORR_BLOCKS 0x10800
0063 #define CGXX_SPUX_RSFEC_CORR        0x10088
0064 #define CGXX_SPUX_RSFEC_UNCORR      0x10090
0065
0066 #define CGXX_SPUX_CONTROL1_LBK      BIT_ULL(14)
0067 #define CGXX_GMP_PCS_MRX_CTL        0x30000
0068 #define CGXX_GMP_PCS_MRX_CTL_LBK    BIT_ULL(14)
0069
0070 #define CGXX_SMUX_RX_FRM_CTL        0x20020
0071 #define CGX_SMUX_RX_FRM_CTL_CTL_BCK BIT_ULL(3)
0072 #define CGX_SMUX_RX_FRM_CTL_PTP_MODE    BIT_ULL(12)
0073 #define CGXX_GMP_GMI_RXX_FRM_CTL    0x38028
0074 #define CGX_GMP_GMI_RXX_FRM_CTL_CTL_BCK BIT_ULL(3)
0075 #define CGX_GMP_GMI_RXX_FRM_CTL_PTP_MODE BIT_ULL(12)
0076 #define CGXX_SMUX_TX_CTL        0x20178
0077 #define CGXX_SMUX_TX_PAUSE_PKT_TIME 0x20110
0078 #define CGXX_SMUX_TX_PAUSE_PKT_INTERVAL 0x20120
0079 #define CGXX_SMUX_SMAC                        0x20108
0080 #define CGXX_SMUX_CBFC_CTL                    0x20218
0081 #define CGXX_SMUX_CBFC_CTL_RX_EN             BIT_ULL(0)
0082 #define CGXX_SMUX_CBFC_CTL_TX_EN             BIT_ULL(1)
0083 #define CGXX_SMUX_CBFC_CTL_DRP_EN            BIT_ULL(2)
0084 #define CGXX_SMUX_CBFC_CTL_BCK_EN            BIT_ULL(3)
0085 #define CGX_PFC_CLASS_MASK           GENMASK_ULL(47, 32)
0086 #define CGXX_GMP_GMI_TX_PAUSE_PKT_TIME  0x38230
0087 #define CGXX_GMP_GMI_TX_PAUSE_PKT_INTERVAL  0x38248
0088 #define CGX_SMUX_TX_CTL_L2P_BP_CONV BIT_ULL(7)
0089 #define CGXX_CMR_RX_OVR_BP      0x130
0090 #define CGX_CMR_RX_OVR_BP_EN(X)     BIT_ULL(((X) + 8))
0091 #define CGX_CMR_RX_OVR_BP_BP(X)     BIT_ULL(((X) + 4))
0092
0093 #define CGX_COMMAND_REG         CGXX_SCRATCH1_REG
0094 #define CGX_EVENT_REG           CGXX_SCRATCH0_REG
0095 #define CGX_CMD_TIMEOUT         5000 /* msecs */
0096 #define DEFAULT_PAUSE_TIME      0x7FF
0097
0098 #define CGX_LMAC_FWI            0
0099
0100 enum  cgx_nix_stat_type {
0101     NIX_STATS_RX,
0102     NIX_STATS_TX,
0103 };
0104
0105 enum LMAC_TYPE {
0106     LMAC_MODE_SGMII     = 0,
0107     LMAC_MODE_XAUI      = 1,
0108     LMAC_MODE_RXAUI     = 2,
0109     LMAC_MODE_10G_R     = 3,
0110     LMAC_MODE_40G_R     = 4,
0111     LMAC_MODE_QSGMII    = 6,
0112     LMAC_MODE_25G_R     = 7,
0113     LMAC_MODE_50G_R     = 8,
0114     LMAC_MODE_100G_R    = 9,
0115     LMAC_MODE_USXGMII   = 10,
0116     LMAC_MODE_MAX,
0117 };
0118
0119 struct cgx_link_event {
0120     struct cgx_link_user_info link_uinfo;
0121     u8 cgx_id;
0122     u8 lmac_id;
0123 };
0124
0125 /**
0126  * struct cgx_event_cb
0127  * @notify_link_chg:    callback for link change notification
0128  * @data:   data passed to callback function
0129  */
0130 struct cgx_event_cb {
0131     int (*notify_link_chg)(struct cgx_link_event *event, void *data);
0132     void *data;
0133 };
0134
0135 extern struct pci_driver cgx_driver;
0136
0137 int cgx_get_cgxcnt_max(void);
0138 int cgx_get_cgxid(void *cgxd);
0139 int cgx_get_lmac_cnt(void *cgxd);
0140 void *cgx_get_pdata(int cgx_id);
0141 int cgx_set_pkind(void *cgxd, u8 lmac_id, int pkind);
0142 int cgx_lmac_evh_register(struct cgx_event_cb *cb, void *cgxd, int lmac_id);
0143 int cgx_lmac_evh_unregister(void *cgxd, int lmac_id);
0144 int cgx_get_tx_stats(void *cgxd, int lmac_id, int idx, u64 *tx_stat);
0145 int cgx_get_rx_stats(void *cgxd, int lmac_id, int idx, u64 *rx_stat);
0146 int cgx_lmac_rx_tx_enable(void *cgxd, int lmac_id, bool enable);
0147 int cgx_lmac_tx_enable(void *cgxd, int lmac_id, bool enable);
0148 int cgx_lmac_addr_set(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
0149 int cgx_lmac_addr_reset(u8 cgx_id, u8 lmac_id);
0150 u64 cgx_lmac_addr_get(u8 cgx_id, u8 lmac_id);
0151 int cgx_lmac_addr_add(u8 cgx_id, u8 lmac_id, u8 *mac_addr);
0152 int cgx_lmac_addr_del(u8 cgx_id, u8 lmac_id, u8 index);
0153 int cgx_lmac_addr_max_entries_get(u8 cgx_id, u8 lmac_id);
0154 void cgx_lmac_promisc_config(int cgx_id, int lmac_id, bool enable);
0155 void cgx_lmac_enadis_rx_pause_fwding(void *cgxd, int lmac_id, bool enable);
0156 int cgx_lmac_internal_loopback(void *cgxd, int lmac_id, bool enable);
0157 int cgx_get_link_info(void *cgxd, int lmac_id,
0158               struct cgx_link_user_info *linfo);
0159 int cgx_lmac_linkup_start(void *cgxd);
0160 int cgx_get_fwdata_base(u64 *base);
0161 int cgx_lmac_get_pause_frm(void *cgxd, int lmac_id,
0162                u8 *tx_pause, u8 *rx_pause);
0163 int cgx_lmac_set_pause_frm(void *cgxd, int lmac_id,
0164                u8 tx_pause, u8 rx_pause);
0165 void cgx_lmac_ptp_config(void *cgxd, int lmac_id, bool enable);
0166 u8 cgx_lmac_get_p2x(int cgx_id, int lmac_id);
0167 int cgx_set_fec(u64 fec, int cgx_id, int lmac_id);
0168 int cgx_get_fec_stats(void *cgxd, int lmac_id, struct cgx_fec_stats_rsp *rsp);
0169 int cgx_get_phy_fec_stats(void *cgxd, int lmac_id);
0170 int cgx_set_link_mode(void *cgxd, struct cgx_set_link_mode_args args,
0171               int cgx_id, int lmac_id);
0172 u64 cgx_features_get(void *cgxd);
0173 struct mac_ops *get_mac_ops(void *cgxd);
0174 int cgx_get_nr_lmacs(void *cgxd);
0175 u8 cgx_get_lmacid(void *cgxd, u8 lmac_index);
0176 unsigned long cgx_get_lmac_bmap(void *cgxd);
0177 void cgx_lmac_write(int cgx_id, int lmac_id, u64 offset, u64 val);
0178 u64 cgx_lmac_read(int cgx_id, int lmac_id, u64 offset);
0179 int cgx_lmac_addr_update(u8 cgx_id, u8 lmac_id, u8 *mac_addr, u8 index);
0180 u64 cgx_read_dmac_ctrl(void *cgxd, int lmac_id);
0181 u64 cgx_read_dmac_entry(void *cgxd, int index);
0182 int cgx_lmac_pfc_config(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
0183             u16 pfc_en);
0184 int cgx_lmac_get_pfc_frm_cfg(void *cgxd, int lmac_id, u8 *tx_pause,
0185                  u8 *rx_pause);
0186 int verify_lmac_fc_cfg(void *cgxd, int lmac_id, u8 tx_pause, u8 rx_pause,
0187                int pfvf_idx);
0188 #endif /* CGX_H */