ethernet/marvell/mvneta_bm.h

0001 /*
0002  * Driver for Marvell NETA network controller Buffer Manager.
0003  *
0004  * Copyright (C) 2015 Marvell
0005  *
0006  * Marcin Wojtas <mw@semihalf.com>
0007  *
0008  * This file is licensed under the terms of the GNU General Public
0009  * License version 2. This program is licensed "as is" without any
0010  * warranty of any kind, whether express or implied.
0011  */
0012
0013 #ifndef _MVNETA_BM_H_
0014 #define _MVNETA_BM_H_
0015
0016 /* BM Configuration Register */
0017 #define MVNETA_BM_CONFIG_REG            0x0
0018 #define    MVNETA_BM_STATUS_MASK        0x30
0019 #define    MVNETA_BM_ACTIVE_MASK        BIT(4)
0020 #define    MVNETA_BM_MAX_IN_BURST_SIZE_MASK 0x60000
0021 #define    MVNETA_BM_MAX_IN_BURST_SIZE_16BP BIT(18)
0022 #define    MVNETA_BM_EMPTY_LIMIT_MASK       BIT(19)
0023
0024 /* BM Activation Register */
0025 #define MVNETA_BM_COMMAND_REG           0x4
0026 #define    MVNETA_BM_START_MASK         BIT(0)
0027 #define    MVNETA_BM_STOP_MASK          BIT(1)
0028 #define    MVNETA_BM_PAUSE_MASK         BIT(2)
0029
0030 /* BM Xbar interface Register */
0031 #define MVNETA_BM_XBAR_01_REG           0x8
0032 #define MVNETA_BM_XBAR_23_REG           0xc
0033 #define MVNETA_BM_XBAR_POOL_REG(pool)       \
0034         (((pool) < 2) ? MVNETA_BM_XBAR_01_REG : MVNETA_BM_XBAR_23_REG)
0035 #define     MVNETA_BM_TARGET_ID_OFFS(pool)  (((pool) & 1) ? 16 : 0)
0036 #define     MVNETA_BM_TARGET_ID_MASK(pool)  \
0037         (0xf << MVNETA_BM_TARGET_ID_OFFS(pool))
0038 #define     MVNETA_BM_TARGET_ID_VAL(pool, id)   \
0039         ((id) << MVNETA_BM_TARGET_ID_OFFS(pool))
0040 #define     MVNETA_BM_XBAR_ATTR_OFFS(pool)  (((pool) & 1) ? 20 : 4)
0041 #define     MVNETA_BM_XBAR_ATTR_MASK(pool)  \
0042         (0xff << MVNETA_BM_XBAR_ATTR_OFFS(pool))
0043 #define     MVNETA_BM_XBAR_ATTR_VAL(pool, attr) \
0044         ((attr) << MVNETA_BM_XBAR_ATTR_OFFS(pool))
0045
0046 /* Address of External Buffer Pointers Pool Register */
0047 #define MVNETA_BM_POOL_BASE_REG(pool)       (0x10 + ((pool) << 4))
0048 #define     MVNETA_BM_POOL_ENABLE_MASK      BIT(0)
0049
0050 /* External Buffer Pointers Pool RD pointer Register */
0051 #define MVNETA_BM_POOL_READ_PTR_REG(pool)   (0x14 + ((pool) << 4))
0052 #define     MVNETA_BM_POOL_SET_READ_PTR_MASK    0xfffc
0053 #define     MVNETA_BM_POOL_GET_READ_PTR_OFFS    16
0054 #define     MVNETA_BM_POOL_GET_READ_PTR_MASK    0xfffc0000
0055
0056 /* External Buffer Pointers Pool WR pointer */
0057 #define MVNETA_BM_POOL_WRITE_PTR_REG(pool)  (0x18 + ((pool) << 4))
0058 #define     MVNETA_BM_POOL_SET_WRITE_PTR_OFFS   0
0059 #define     MVNETA_BM_POOL_SET_WRITE_PTR_MASK   0xfffc
0060 #define     MVNETA_BM_POOL_GET_WRITE_PTR_OFFS   16
0061 #define     MVNETA_BM_POOL_GET_WRITE_PTR_MASK   0xfffc0000
0062
0063 /* External Buffer Pointers Pool Size Register */
0064 #define MVNETA_BM_POOL_SIZE_REG(pool)       (0x1c + ((pool) << 4))
0065 #define     MVNETA_BM_POOL_SIZE_MASK        0x3fff
0066
0067 /* BM Interrupt Cause Register */
0068 #define MVNETA_BM_INTR_CAUSE_REG        (0x50)
0069
0070 /* BM interrupt Mask Register */
0071 #define MVNETA_BM_INTR_MASK_REG         (0x54)
0072
0073 /* Other definitions */
0074 #define MVNETA_BM_SHORT_PKT_SIZE        256
0075 #define MVNETA_BM_POOLS_NUM         4
0076 #define MVNETA_BM_POOL_CAP_MIN          128
0077 #define MVNETA_BM_POOL_CAP_DEF          2048
0078 #define MVNETA_BM_POOL_CAP_MAX          \
0079         (16 * 1024 - MVNETA_BM_POOL_CAP_ALIGN)
0080 #define MVNETA_BM_POOL_CAP_ALIGN        32
0081 #define MVNETA_BM_POOL_PTR_ALIGN        32
0082
0083 #define MVNETA_BM_POOL_ACCESS_OFFS      8
0084
0085 #define MVNETA_BM_BPPI_SIZE         0x100000
0086
0087 #define MVNETA_RX_BUF_SIZE(pkt_size)   ((pkt_size) + NET_SKB_PAD)
0088
0089 enum mvneta_bm_type {
0090     MVNETA_BM_FREE,
0091     MVNETA_BM_LONG,
0092     MVNETA_BM_SHORT
0093 };
0094
0095 struct mvneta_bm {
0096     void __iomem *reg_base;
0097     struct clk *clk;
0098     struct platform_device *pdev;
0099
0100     struct gen_pool *bppi_pool;
0101     /* BPPI virtual base address */
0102     void __iomem *bppi_virt_addr;
0103     /* BPPI physical base address */
0104     dma_addr_t bppi_phys_addr;
0105
0106     /* BM pools */
0107     struct mvneta_bm_pool *bm_pools;
0108 };
0109
0110 struct mvneta_bm_pool {
0111     struct hwbm_pool hwbm_pool;
0112     /* Pool number in the range 0-3 */
0113     u8 id;
0114     enum mvneta_bm_type type;
0115
0116     /* Packet size */
0117     int pkt_size;
0118     /* Size of the buffer acces through DMA*/
0119     u32 buf_size;
0120
0121     /* BPPE virtual base address */
0122     u32 *virt_addr;
0123     /* BPPE physical base address */
0124     dma_addr_t phys_addr;
0125
0126     /* Ports using BM pool */
0127     u8 port_map;
0128
0129     struct mvneta_bm *priv;
0130 };
0131
0132 /* Declarations and definitions */
0133 #if IS_ENABLED(CONFIG_MVNETA_BM)
0134 struct mvneta_bm *mvneta_bm_get(struct device_node *node);
0135 void mvneta_bm_put(struct mvneta_bm *priv);
0136
0137 void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
0138                 struct mvneta_bm_pool *bm_pool, u8 port_map);
0139 void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
0140              u8 port_map);
0141 int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf);
0142 int mvneta_bm_pool_refill(struct mvneta_bm *priv,
0143               struct mvneta_bm_pool *bm_pool);
0144 struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
0145                       enum mvneta_bm_type type, u8 port_id,
0146                       int pkt_size);
0147
0148 static inline void mvneta_bm_pool_put_bp(struct mvneta_bm *priv,
0149                      struct mvneta_bm_pool *bm_pool,
0150                      dma_addr_t buf_phys_addr)
0151 {
0152     writel_relaxed(buf_phys_addr, priv->bppi_virt_addr +
0153                (bm_pool->id << MVNETA_BM_POOL_ACCESS_OFFS));
0154 }
0155
0156 static inline u32 mvneta_bm_pool_get_bp(struct mvneta_bm *priv,
0157                     struct mvneta_bm_pool *bm_pool)
0158 {
0159     return readl_relaxed(priv->bppi_virt_addr +
0160                  (bm_pool->id << MVNETA_BM_POOL_ACCESS_OFFS));
0161 }
0162 #else
0163 static inline void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
0164                       struct mvneta_bm_pool *bm_pool,
0165                       u8 port_map) {}
0166 static inline void mvneta_bm_bufs_free(struct mvneta_bm *priv,
0167                        struct mvneta_bm_pool *bm_pool,
0168                        u8 port_map) {}
0169 static inline int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf)
0170 { return 0; }
0171 static inline int mvneta_bm_pool_refill(struct mvneta_bm *priv,
0172                     struct mvneta_bm_pool *bm_pool)
0173 { return 0; }
0174 static inline struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv,
0175                             u8 pool_id,
0176                             enum mvneta_bm_type type,
0177                             u8 port_id,
0178                             int pkt_size)
0179 { return NULL; }
0180
0181 static inline void mvneta_bm_pool_put_bp(struct mvneta_bm *priv,
0182                      struct mvneta_bm_pool *bm_pool,
0183                      dma_addr_t buf_phys_addr) {}
0184
0185 static inline u32 mvneta_bm_pool_get_bp(struct mvneta_bm *priv,
0186                     struct mvneta_bm_pool *bm_pool)
0187 { return 0; }
0188 static inline struct mvneta_bm *mvneta_bm_get(struct device_node *node)
0189 { return NULL; }
0190 static inline void mvneta_bm_put(struct mvneta_bm *priv) {}
0191 #endif /* CONFIG_MVNETA_BM */
0192 #endif