ethernet/marvell/mvneta_bm.c

0001 /*
0002  * Driver for Marvell NETA network controller Buffer Manager.
0003  *
0004  * Copyright (C) 2015 Marvell
0005  *
0006  * Marcin Wojtas <mw@semihalf.com>
0007  *
0008  * This file is licensed under the terms of the GNU General Public
0009  * License version 2. This program is licensed "as is" without any
0010  * warranty of any kind, whether express or implied.
0011  */
0012
0013 #include <linux/clk.h>
0014 #include <linux/genalloc.h>
0015 #include <linux/io.h>
0016 #include <linux/kernel.h>
0017 #include <linux/mbus.h>
0018 #include <linux/module.h>
0019 #include <linux/netdevice.h>
0020 #include <linux/of.h>
0021 #include <linux/of_platform.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/skbuff.h>
0024 #include <net/hwbm.h>
0025 #include "mvneta_bm.h"
0026
0027 #define MVNETA_BM_DRIVER_NAME "mvneta_bm"
0028 #define MVNETA_BM_DRIVER_VERSION "1.0"
0029
0030 static void mvneta_bm_write(struct mvneta_bm *priv, u32 offset, u32 data)
0031 {
0032     writel(data, priv->reg_base + offset);
0033 }
0034
0035 static u32 mvneta_bm_read(struct mvneta_bm *priv, u32 offset)
0036 {
0037     return readl(priv->reg_base + offset);
0038 }
0039
0040 static void mvneta_bm_pool_enable(struct mvneta_bm *priv, int pool_id)
0041 {
0042     u32 val;
0043
0044     val = mvneta_bm_read(priv, MVNETA_BM_POOL_BASE_REG(pool_id));
0045     val |= MVNETA_BM_POOL_ENABLE_MASK;
0046     mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(pool_id), val);
0047
0048     /* Clear BM cause register */
0049     mvneta_bm_write(priv, MVNETA_BM_INTR_CAUSE_REG, 0);
0050 }
0051
0052 static void mvneta_bm_pool_disable(struct mvneta_bm *priv, int pool_id)
0053 {
0054     u32 val;
0055
0056     val = mvneta_bm_read(priv, MVNETA_BM_POOL_BASE_REG(pool_id));
0057     val &= ~MVNETA_BM_POOL_ENABLE_MASK;
0058     mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(pool_id), val);
0059 }
0060
0061 static inline void mvneta_bm_config_set(struct mvneta_bm *priv, u32 mask)
0062 {
0063     u32 val;
0064
0065     val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
0066     val |= mask;
0067     mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
0068 }
0069
0070 static inline void mvneta_bm_config_clear(struct mvneta_bm *priv, u32 mask)
0071 {
0072     u32 val;
0073
0074     val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
0075     val &= ~mask;
0076     mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
0077 }
0078
0079 static void mvneta_bm_pool_target_set(struct mvneta_bm *priv, int pool_id,
0080                       u8 target_id, u8 attr)
0081 {
0082     u32 val;
0083
0084     val = mvneta_bm_read(priv, MVNETA_BM_XBAR_POOL_REG(pool_id));
0085     val &= ~MVNETA_BM_TARGET_ID_MASK(pool_id);
0086     val &= ~MVNETA_BM_XBAR_ATTR_MASK(pool_id);
0087     val |= MVNETA_BM_TARGET_ID_VAL(pool_id, target_id);
0088     val |= MVNETA_BM_XBAR_ATTR_VAL(pool_id, attr);
0089
0090     mvneta_bm_write(priv, MVNETA_BM_XBAR_POOL_REG(pool_id), val);
0091 }
0092
0093 int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf)
0094 {
0095     struct mvneta_bm_pool *bm_pool =
0096         (struct mvneta_bm_pool *)hwbm_pool->priv;
0097     struct mvneta_bm *priv = bm_pool->priv;
0098     dma_addr_t phys_addr;
0099
0100     /* In order to update buf_cookie field of RX descriptor properly,
0101      * BM hardware expects buf virtual address to be placed in the
0102      * first four bytes of mapped buffer.
0103      */
0104     *(u32 *)buf = (u32)buf;
0105     phys_addr = dma_map_single(&priv->pdev->dev, buf, bm_pool->buf_size,
0106                    DMA_FROM_DEVICE);
0107     if (unlikely(dma_mapping_error(&priv->pdev->dev, phys_addr)))
0108         return -ENOMEM;
0109
0110     mvneta_bm_pool_put_bp(priv, bm_pool, phys_addr);
0111     return 0;
0112 }
0113 EXPORT_SYMBOL_GPL(mvneta_bm_construct);
0114
0115 /* Create pool */
0116 static int mvneta_bm_pool_create(struct mvneta_bm *priv,
0117                  struct mvneta_bm_pool *bm_pool)
0118 {
0119     struct platform_device *pdev = priv->pdev;
0120     u8 target_id, attr;
0121     int size_bytes, err;
0122     size_bytes = sizeof(u32) * bm_pool->hwbm_pool.size;
0123     bm_pool->virt_addr = dma_alloc_coherent(&pdev->dev, size_bytes,
0124                         &bm_pool->phys_addr,
0125                         GFP_KERNEL);
0126     if (!bm_pool->virt_addr)
0127         return -ENOMEM;
0128
0129     if (!IS_ALIGNED((u32)bm_pool->virt_addr, MVNETA_BM_POOL_PTR_ALIGN)) {
0130         dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
0131                   bm_pool->phys_addr);
0132         dev_err(&pdev->dev, "BM pool %d is not %d bytes aligned\n",
0133             bm_pool->id, MVNETA_BM_POOL_PTR_ALIGN);
0134         return -ENOMEM;
0135     }
0136
0137     err = mvebu_mbus_get_dram_win_info(bm_pool->phys_addr, &target_id,
0138                        &attr);
0139     if (err < 0) {
0140         dma_free_coherent(&pdev->dev, size_bytes, bm_pool->virt_addr,
0141                   bm_pool->phys_addr);
0142         return err;
0143     }
0144
0145     /* Set pool address */
0146     mvneta_bm_write(priv, MVNETA_BM_POOL_BASE_REG(bm_pool->id),
0147             bm_pool->phys_addr);
0148
0149     mvneta_bm_pool_target_set(priv, bm_pool->id, target_id,  attr);
0150     mvneta_bm_pool_enable(priv, bm_pool->id);
0151
0152     return 0;
0153 }
0154
0155 /* Notify the driver that BM pool is being used as specific type and return the
0156  * pool pointer on success
0157  */
0158 struct mvneta_bm_pool *mvneta_bm_pool_use(struct mvneta_bm *priv, u8 pool_id,
0159                       enum mvneta_bm_type type, u8 port_id,
0160                       int pkt_size)
0161 {
0162     struct mvneta_bm_pool *new_pool = &priv->bm_pools[pool_id];
0163     int num, err;
0164
0165     if (new_pool->type == MVNETA_BM_LONG &&
0166         new_pool->port_map != 1 << port_id) {
0167         dev_err(&priv->pdev->dev,
0168             "long pool cannot be shared by the ports\n");
0169         return NULL;
0170     }
0171
0172     if (new_pool->type == MVNETA_BM_SHORT && new_pool->type != type) {
0173         dev_err(&priv->pdev->dev,
0174             "mixing pools' types between the ports is forbidden\n");
0175         return NULL;
0176     }
0177
0178     if (new_pool->pkt_size == 0 || type != MVNETA_BM_SHORT)
0179         new_pool->pkt_size = pkt_size;
0180
0181     /* Allocate buffers in case BM pool hasn't been used yet */
0182     if (new_pool->type == MVNETA_BM_FREE) {
0183         struct hwbm_pool *hwbm_pool = &new_pool->hwbm_pool;
0184
0185         new_pool->priv = priv;
0186         new_pool->type = type;
0187         new_pool->buf_size = MVNETA_RX_BUF_SIZE(new_pool->pkt_size);
0188         hwbm_pool->frag_size =
0189             SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(new_pool->pkt_size)) +
0190             SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
0191         hwbm_pool->construct = mvneta_bm_construct;
0192         hwbm_pool->priv = new_pool;
0193         mutex_init(&hwbm_pool->buf_lock);
0194
0195         /* Create new pool */
0196         err = mvneta_bm_pool_create(priv, new_pool);
0197         if (err) {
0198             dev_err(&priv->pdev->dev, "fail to create pool %d\n",
0199                 new_pool->id);
0200             return NULL;
0201         }
0202
0203         /* Allocate buffers for this pool */
0204         num = hwbm_pool_add(hwbm_pool, hwbm_pool->size);
0205         if (num != hwbm_pool->size) {
0206             WARN(1, "pool %d: %d of %d allocated\n",
0207                  new_pool->id, num, hwbm_pool->size);
0208             return NULL;
0209         }
0210     }
0211
0212     return new_pool;
0213 }
0214 EXPORT_SYMBOL_GPL(mvneta_bm_pool_use);
0215
0216 /* Free all buffers from the pool */
0217 void mvneta_bm_bufs_free(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
0218              u8 port_map)
0219 {
0220     int i;
0221
0222     bm_pool->port_map &= ~port_map;
0223     if (bm_pool->port_map)
0224         return;
0225
0226     mvneta_bm_config_set(priv, MVNETA_BM_EMPTY_LIMIT_MASK);
0227
0228     for (i = 0; i < bm_pool->hwbm_pool.buf_num; i++) {
0229         dma_addr_t buf_phys_addr;
0230         u32 *vaddr;
0231
0232         /* Get buffer physical address (indirect access) */
0233         buf_phys_addr = mvneta_bm_pool_get_bp(priv, bm_pool);
0234
0235         /* Work-around to the problems when destroying the pool,
0236          * when it occurs that a read access to BPPI returns 0.
0237          */
0238         if (buf_phys_addr == 0)
0239             continue;
0240
0241         vaddr = phys_to_virt(buf_phys_addr);
0242         if (!vaddr)
0243             break;
0244
0245         dma_unmap_single(&priv->pdev->dev, buf_phys_addr,
0246                  bm_pool->buf_size, DMA_FROM_DEVICE);
0247         hwbm_buf_free(&bm_pool->hwbm_pool, vaddr);
0248     }
0249
0250     mvneta_bm_config_clear(priv, MVNETA_BM_EMPTY_LIMIT_MASK);
0251
0252     /* Update BM driver with number of buffers removed from pool */
0253     bm_pool->hwbm_pool.buf_num -= i;
0254 }
0255 EXPORT_SYMBOL_GPL(mvneta_bm_bufs_free);
0256
0257 /* Cleanup pool */
0258 void mvneta_bm_pool_destroy(struct mvneta_bm *priv,
0259                 struct mvneta_bm_pool *bm_pool, u8 port_map)
0260 {
0261     struct hwbm_pool *hwbm_pool = &bm_pool->hwbm_pool;
0262     bm_pool->port_map &= ~port_map;
0263     if (bm_pool->port_map)
0264         return;
0265
0266     bm_pool->type = MVNETA_BM_FREE;
0267
0268     mvneta_bm_bufs_free(priv, bm_pool, port_map);
0269     if (hwbm_pool->buf_num)
0270         WARN(1, "cannot free all buffers in pool %d\n", bm_pool->id);
0271
0272     if (bm_pool->virt_addr) {
0273         dma_free_coherent(&priv->pdev->dev,
0274                   sizeof(u32) * hwbm_pool->size,
0275                   bm_pool->virt_addr, bm_pool->phys_addr);
0276         bm_pool->virt_addr = NULL;
0277     }
0278
0279     mvneta_bm_pool_disable(priv, bm_pool->id);
0280 }
0281 EXPORT_SYMBOL_GPL(mvneta_bm_pool_destroy);
0282
0283 static void mvneta_bm_pools_init(struct mvneta_bm *priv)
0284 {
0285     struct device_node *dn = priv->pdev->dev.of_node;
0286     struct mvneta_bm_pool *bm_pool;
0287     char prop[15];
0288     u32 size;
0289     int i;
0290
0291     /* Activate BM unit */
0292     mvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_START_MASK);
0293
0294     /* Create all pools with maximum size */
0295     for (i = 0; i < MVNETA_BM_POOLS_NUM; i++) {
0296         bm_pool = &priv->bm_pools[i];
0297         bm_pool->id = i;
0298         bm_pool->type = MVNETA_BM_FREE;
0299
0300         /* Reset read pointer */
0301         mvneta_bm_write(priv, MVNETA_BM_POOL_READ_PTR_REG(i), 0);
0302
0303         /* Reset write pointer */
0304         mvneta_bm_write(priv, MVNETA_BM_POOL_WRITE_PTR_REG(i), 0);
0305
0306         /* Configure pool size according to DT or use default value */
0307         sprintf(prop, "pool%d,capacity", i);
0308         if (of_property_read_u32(dn, prop, &size)) {
0309             size = MVNETA_BM_POOL_CAP_DEF;
0310         } else if (size > MVNETA_BM_POOL_CAP_MAX) {
0311             dev_warn(&priv->pdev->dev,
0312                  "Illegal pool %d capacity %d, set to %d\n",
0313                  i, size, MVNETA_BM_POOL_CAP_MAX);
0314             size = MVNETA_BM_POOL_CAP_MAX;
0315         } else if (size < MVNETA_BM_POOL_CAP_MIN) {
0316             dev_warn(&priv->pdev->dev,
0317                  "Illegal pool %d capacity %d, set to %d\n",
0318                  i, size, MVNETA_BM_POOL_CAP_MIN);
0319             size = MVNETA_BM_POOL_CAP_MIN;
0320         } else if (!IS_ALIGNED(size, MVNETA_BM_POOL_CAP_ALIGN)) {
0321             dev_warn(&priv->pdev->dev,
0322                  "Illegal pool %d capacity %d, round to %d\n",
0323                  i, size, ALIGN(size,
0324                  MVNETA_BM_POOL_CAP_ALIGN));
0325             size = ALIGN(size, MVNETA_BM_POOL_CAP_ALIGN);
0326         }
0327         bm_pool->hwbm_pool.size = size;
0328
0329         mvneta_bm_write(priv, MVNETA_BM_POOL_SIZE_REG(i),
0330                 bm_pool->hwbm_pool.size);
0331
0332         /* Obtain custom pkt_size from DT */
0333         sprintf(prop, "pool%d,pkt-size", i);
0334         if (of_property_read_u32(dn, prop, &bm_pool->pkt_size))
0335             bm_pool->pkt_size = 0;
0336     }
0337 }
0338
0339 static void mvneta_bm_default_set(struct mvneta_bm *priv)
0340 {
0341     u32 val;
0342
0343     /* Mask BM all interrupts */
0344     mvneta_bm_write(priv, MVNETA_BM_INTR_MASK_REG, 0);
0345
0346     /* Clear BM cause register */
0347     mvneta_bm_write(priv, MVNETA_BM_INTR_CAUSE_REG, 0);
0348
0349     /* Set BM configuration register */
0350     val = mvneta_bm_read(priv, MVNETA_BM_CONFIG_REG);
0351
0352     /* Reduce MaxInBurstSize from 32 BPs to 16 BPs */
0353     val &= ~MVNETA_BM_MAX_IN_BURST_SIZE_MASK;
0354     val |= MVNETA_BM_MAX_IN_BURST_SIZE_16BP;
0355     mvneta_bm_write(priv, MVNETA_BM_CONFIG_REG, val);
0356 }
0357
0358 static int mvneta_bm_init(struct mvneta_bm *priv)
0359 {
0360     mvneta_bm_default_set(priv);
0361
0362     /* Allocate and initialize BM pools structures */
0363     priv->bm_pools = devm_kcalloc(&priv->pdev->dev, MVNETA_BM_POOLS_NUM,
0364                       sizeof(struct mvneta_bm_pool),
0365                       GFP_KERNEL);
0366     if (!priv->bm_pools)
0367         return -ENOMEM;
0368
0369     mvneta_bm_pools_init(priv);
0370
0371     return 0;
0372 }
0373
0374 static int mvneta_bm_get_sram(struct device_node *dn,
0375                   struct mvneta_bm *priv)
0376 {
0377     priv->bppi_pool = of_gen_pool_get(dn, "internal-mem", 0);
0378     if (!priv->bppi_pool)
0379         return -ENOMEM;
0380
0381     priv->bppi_virt_addr = gen_pool_dma_alloc(priv->bppi_pool,
0382                           MVNETA_BM_BPPI_SIZE,
0383                           &priv->bppi_phys_addr);
0384     if (!priv->bppi_virt_addr)
0385         return -ENOMEM;
0386
0387     return 0;
0388 }
0389
0390 static void mvneta_bm_put_sram(struct mvneta_bm *priv)
0391 {
0392     gen_pool_free(priv->bppi_pool, priv->bppi_phys_addr,
0393               MVNETA_BM_BPPI_SIZE);
0394 }
0395
0396 struct mvneta_bm *mvneta_bm_get(struct device_node *node)
0397 {
0398     struct platform_device *pdev = of_find_device_by_node(node);
0399
0400     return pdev ? platform_get_drvdata(pdev) : NULL;
0401 }
0402 EXPORT_SYMBOL_GPL(mvneta_bm_get);
0403
0404 void mvneta_bm_put(struct mvneta_bm *priv)
0405 {
0406     platform_device_put(priv->pdev);
0407 }
0408 EXPORT_SYMBOL_GPL(mvneta_bm_put);
0409
0410 static int mvneta_bm_probe(struct platform_device *pdev)
0411 {
0412     struct device_node *dn = pdev->dev.of_node;
0413     struct mvneta_bm *priv;
0414     int err;
0415
0416     priv = devm_kzalloc(&pdev->dev, sizeof(struct mvneta_bm), GFP_KERNEL);
0417     if (!priv)
0418         return -ENOMEM;
0419
0420     priv->reg_base = devm_platform_ioremap_resource(pdev, 0);
0421     if (IS_ERR(priv->reg_base))
0422         return PTR_ERR(priv->reg_base);
0423
0424     priv->clk = devm_clk_get(&pdev->dev, NULL);
0425     if (IS_ERR(priv->clk))
0426         return PTR_ERR(priv->clk);
0427     err = clk_prepare_enable(priv->clk);
0428     if (err < 0)
0429         return err;
0430
0431     err = mvneta_bm_get_sram(dn, priv);
0432     if (err < 0) {
0433         dev_err(&pdev->dev, "failed to allocate internal memory\n");
0434         goto err_clk;
0435     }
0436
0437     priv->pdev = pdev;
0438
0439     /* Initialize buffer manager internals */
0440     err = mvneta_bm_init(priv);
0441     if (err < 0) {
0442         dev_err(&pdev->dev, "failed to initialize controller\n");
0443         goto err_sram;
0444     }
0445
0446     dn->data = priv;
0447     platform_set_drvdata(pdev, priv);
0448
0449     dev_info(&pdev->dev, "Buffer Manager for network controller enabled\n");
0450
0451     return 0;
0452
0453 err_sram:
0454     mvneta_bm_put_sram(priv);
0455 err_clk:
0456     clk_disable_unprepare(priv->clk);
0457     return err;
0458 }
0459
0460 static int mvneta_bm_remove(struct platform_device *pdev)
0461 {
0462     struct mvneta_bm *priv = platform_get_drvdata(pdev);
0463     u8 all_ports_map = 0xff;
0464     int i = 0;
0465
0466     for (i = 0; i < MVNETA_BM_POOLS_NUM; i++) {
0467         struct mvneta_bm_pool *bm_pool = &priv->bm_pools[i];
0468
0469         mvneta_bm_pool_destroy(priv, bm_pool, all_ports_map);
0470     }
0471
0472     mvneta_bm_put_sram(priv);
0473
0474     /* Dectivate BM unit */
0475     mvneta_bm_write(priv, MVNETA_BM_COMMAND_REG, MVNETA_BM_STOP_MASK);
0476
0477     clk_disable_unprepare(priv->clk);
0478
0479     return 0;
0480 }
0481
0482 static const struct of_device_id mvneta_bm_match[] = {
0483     { .compatible = "marvell,armada-380-neta-bm" },
0484     { }
0485 };
0486 MODULE_DEVICE_TABLE(of, mvneta_bm_match);
0487
0488 static struct platform_driver mvneta_bm_driver = {
0489     .probe = mvneta_bm_probe,
0490     .remove = mvneta_bm_remove,
0491     .driver = {
0492         .name = MVNETA_BM_DRIVER_NAME,
0493         .of_match_table = mvneta_bm_match,
0494     },
0495 };
0496
0497 module_platform_driver(mvneta_bm_driver);
0498
0499 MODULE_DESCRIPTION("Marvell NETA Buffer Manager Driver - www.marvell.com");
0500 MODULE_AUTHOR("Marcin Wojtas <mw@semihalf.com>");
0501 MODULE_LICENSE("GPL v2");