ethernet/marvell/mvmdio.c

0001 /*
0002  * Driver for the MDIO interface of Marvell network interfaces.
0003  *
0004  * Since the MDIO interface of Marvell network interfaces is shared
0005  * between all network interfaces, having a single driver allows to
0006  * handle concurrent accesses properly (you may have four Ethernet
0007  * ports, but they in fact share the same SMI interface to access
0008  * the MDIO bus). This driver is currently used by the mvneta and
0009  * mv643xx_eth drivers.
0010  *
0011  * Copyright (C) 2012 Marvell
0012  *
0013  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
0014  *
0015  * This file is licensed under the terms of the GNU General Public
0016  * License version 2. This program is licensed "as is" without any
0017  * warranty of any kind, whether express or implied.
0018  */
0019
0020 #include <linux/acpi.h>
0021 #include <linux/acpi_mdio.h>
0022 #include <linux/clk.h>
0023 #include <linux/delay.h>
0024 #include <linux/interrupt.h>
0025 #include <linux/io.h>
0026 #include <linux/kernel.h>
0027 #include <linux/module.h>
0028 #include <linux/of_device.h>
0029 #include <linux/of_mdio.h>
0030 #include <linux/phy.h>
0031 #include <linux/platform_device.h>
0032 #include <linux/sched.h>
0033 #include <linux/wait.h>
0034
0035 #define MVMDIO_SMI_DATA_SHIFT       0
0036 #define MVMDIO_SMI_PHY_ADDR_SHIFT   16
0037 #define MVMDIO_SMI_PHY_REG_SHIFT    21
0038 #define MVMDIO_SMI_READ_OPERATION   BIT(26)
0039 #define MVMDIO_SMI_WRITE_OPERATION  0
0040 #define MVMDIO_SMI_READ_VALID       BIT(27)
0041 #define MVMDIO_SMI_BUSY         BIT(28)
0042 #define MVMDIO_ERR_INT_CAUSE        0x007C
0043 #define  MVMDIO_ERR_INT_SMI_DONE    0x00000010
0044 #define MVMDIO_ERR_INT_MASK     0x0080
0045
0046 #define MVMDIO_XSMI_MGNT_REG        0x0
0047 #define  MVMDIO_XSMI_PHYADDR_SHIFT  16
0048 #define  MVMDIO_XSMI_DEVADDR_SHIFT  21
0049 #define  MVMDIO_XSMI_WRITE_OPERATION    (0x5 << 26)
0050 #define  MVMDIO_XSMI_READ_OPERATION (0x7 << 26)
0051 #define  MVMDIO_XSMI_READ_VALID     BIT(29)
0052 #define  MVMDIO_XSMI_BUSY       BIT(30)
0053 #define MVMDIO_XSMI_ADDR_REG        0x8
0054
0055 /*
0056  * SMI Timeout measurements:
0057  * - Kirkwood 88F6281 (Globalscale Dreamplug): 45us to 95us (Interrupt)
0058  * - Armada 370       (Globalscale Mirabox):   41us to 43us (Polled)
0059  */
0060 #define MVMDIO_SMI_TIMEOUT      1000 /* 1000us = 1ms */
0061 #define MVMDIO_SMI_POLL_INTERVAL_MIN    45
0062 #define MVMDIO_SMI_POLL_INTERVAL_MAX    55
0063
0064 #define MVMDIO_XSMI_POLL_INTERVAL_MIN   150
0065 #define MVMDIO_XSMI_POLL_INTERVAL_MAX   160
0066
0067 struct orion_mdio_dev {
0068     void __iomem *regs;
0069     struct clk *clk[4];
0070     /*
0071      * If we have access to the error interrupt pin (which is
0072      * somewhat misnamed as it not only reflects internal errors
0073      * but also reflects SMI completion), use that to wait for
0074      * SMI access completion instead of polling the SMI busy bit.
0075      */
0076     int err_interrupt;
0077     wait_queue_head_t smi_busy_wait;
0078 };
0079
0080 enum orion_mdio_bus_type {
0081     BUS_TYPE_SMI,
0082     BUS_TYPE_XSMI
0083 };
0084
0085 struct orion_mdio_ops {
0086     int (*is_done)(struct orion_mdio_dev *);
0087     unsigned int poll_interval_min;
0088     unsigned int poll_interval_max;
0089 };
0090
0091 /* Wait for the SMI unit to be ready for another operation
0092  */
0093 static int orion_mdio_wait_ready(const struct orion_mdio_ops *ops,
0094                  struct mii_bus *bus)
0095 {
0096     struct orion_mdio_dev *dev = bus->priv;
0097     unsigned long timeout = usecs_to_jiffies(MVMDIO_SMI_TIMEOUT);
0098     unsigned long end = jiffies + timeout;
0099     int timedout = 0;
0100
0101     while (1) {
0102             if (ops->is_done(dev))
0103             return 0;
0104             else if (timedout)
0105             break;
0106
0107             if (dev->err_interrupt <= 0) {
0108             usleep_range(ops->poll_interval_min,
0109                      ops->poll_interval_max);
0110
0111             if (time_is_before_jiffies(end))
0112                 ++timedout;
0113             } else {
0114             /* wait_event_timeout does not guarantee a delay of at
0115              * least one whole jiffie, so timeout must be no less
0116              * than two.
0117              */
0118             if (timeout < 2)
0119                 timeout = 2;
0120             wait_event_timeout(dev->smi_busy_wait,
0121                            ops->is_done(dev), timeout);
0122
0123             ++timedout;
0124             }
0125     }
0126
0127     dev_err(bus->parent, "Timeout: SMI busy for too long\n");
0128     return  -ETIMEDOUT;
0129 }
0130
0131 static int orion_mdio_smi_is_done(struct orion_mdio_dev *dev)
0132 {
0133     return !(readl(dev->regs) & MVMDIO_SMI_BUSY);
0134 }
0135
0136 static const struct orion_mdio_ops orion_mdio_smi_ops = {
0137     .is_done = orion_mdio_smi_is_done,
0138     .poll_interval_min = MVMDIO_SMI_POLL_INTERVAL_MIN,
0139     .poll_interval_max = MVMDIO_SMI_POLL_INTERVAL_MAX,
0140 };
0141
0142 static int orion_mdio_smi_read(struct mii_bus *bus, int mii_id,
0143                    int regnum)
0144 {
0145     struct orion_mdio_dev *dev = bus->priv;
0146     u32 val;
0147     int ret;
0148
0149     if (regnum & MII_ADDR_C45)
0150         return -EOPNOTSUPP;
0151
0152     ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
0153     if (ret < 0)
0154         return ret;
0155
0156     writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
0157         (regnum << MVMDIO_SMI_PHY_REG_SHIFT)  |
0158         MVMDIO_SMI_READ_OPERATION),
0159            dev->regs);
0160
0161     ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
0162     if (ret < 0)
0163         return ret;
0164
0165     val = readl(dev->regs);
0166     if (!(val & MVMDIO_SMI_READ_VALID)) {
0167         dev_err(bus->parent, "SMI bus read not valid\n");
0168         return -ENODEV;
0169     }
0170
0171     return val & GENMASK(15, 0);
0172 }
0173
0174 static int orion_mdio_smi_write(struct mii_bus *bus, int mii_id,
0175                 int regnum, u16 value)
0176 {
0177     struct orion_mdio_dev *dev = bus->priv;
0178     int ret;
0179
0180     if (regnum & MII_ADDR_C45)
0181         return -EOPNOTSUPP;
0182
0183     ret = orion_mdio_wait_ready(&orion_mdio_smi_ops, bus);
0184     if (ret < 0)
0185         return ret;
0186
0187     writel(((mii_id << MVMDIO_SMI_PHY_ADDR_SHIFT) |
0188         (regnum << MVMDIO_SMI_PHY_REG_SHIFT)  |
0189         MVMDIO_SMI_WRITE_OPERATION            |
0190         (value << MVMDIO_SMI_DATA_SHIFT)),
0191            dev->regs);
0192
0193     return 0;
0194 }
0195
0196 static int orion_mdio_xsmi_is_done(struct orion_mdio_dev *dev)
0197 {
0198     return !(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & MVMDIO_XSMI_BUSY);
0199 }
0200
0201 static const struct orion_mdio_ops orion_mdio_xsmi_ops = {
0202     .is_done = orion_mdio_xsmi_is_done,
0203     .poll_interval_min = MVMDIO_XSMI_POLL_INTERVAL_MIN,
0204     .poll_interval_max = MVMDIO_XSMI_POLL_INTERVAL_MAX,
0205 };
0206
0207 static int orion_mdio_xsmi_read(struct mii_bus *bus, int mii_id,
0208                 int regnum)
0209 {
0210     struct orion_mdio_dev *dev = bus->priv;
0211     u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
0212     int ret;
0213
0214     if (!(regnum & MII_ADDR_C45))
0215         return -EOPNOTSUPP;
0216
0217     ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
0218     if (ret < 0)
0219         return ret;
0220
0221     writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
0222     writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
0223            (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
0224            MVMDIO_XSMI_READ_OPERATION,
0225            dev->regs + MVMDIO_XSMI_MGNT_REG);
0226
0227     ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
0228     if (ret < 0)
0229         return ret;
0230
0231     if (!(readl(dev->regs + MVMDIO_XSMI_MGNT_REG) &
0232           MVMDIO_XSMI_READ_VALID)) {
0233         dev_err(bus->parent, "XSMI bus read not valid\n");
0234         return -ENODEV;
0235     }
0236
0237     return readl(dev->regs + MVMDIO_XSMI_MGNT_REG) & GENMASK(15, 0);
0238 }
0239
0240 static int orion_mdio_xsmi_write(struct mii_bus *bus, int mii_id,
0241                 int regnum, u16 value)
0242 {
0243     struct orion_mdio_dev *dev = bus->priv;
0244     u16 dev_addr = (regnum >> 16) & GENMASK(4, 0);
0245     int ret;
0246
0247     if (!(regnum & MII_ADDR_C45))
0248         return -EOPNOTSUPP;
0249
0250     ret = orion_mdio_wait_ready(&orion_mdio_xsmi_ops, bus);
0251     if (ret < 0)
0252         return ret;
0253
0254     writel(regnum & GENMASK(15, 0), dev->regs + MVMDIO_XSMI_ADDR_REG);
0255     writel((mii_id << MVMDIO_XSMI_PHYADDR_SHIFT) |
0256            (dev_addr << MVMDIO_XSMI_DEVADDR_SHIFT) |
0257            MVMDIO_XSMI_WRITE_OPERATION | value,
0258            dev->regs + MVMDIO_XSMI_MGNT_REG);
0259
0260     return 0;
0261 }
0262
0263 static irqreturn_t orion_mdio_err_irq(int irq, void *dev_id)
0264 {
0265     struct orion_mdio_dev *dev = dev_id;
0266
0267     if (readl(dev->regs + MVMDIO_ERR_INT_CAUSE) &
0268             MVMDIO_ERR_INT_SMI_DONE) {
0269         writel(~MVMDIO_ERR_INT_SMI_DONE,
0270                 dev->regs + MVMDIO_ERR_INT_CAUSE);
0271         wake_up(&dev->smi_busy_wait);
0272         return IRQ_HANDLED;
0273     }
0274
0275     return IRQ_NONE;
0276 }
0277
0278 static int orion_mdio_probe(struct platform_device *pdev)
0279 {
0280     enum orion_mdio_bus_type type;
0281     struct resource *r;
0282     struct mii_bus *bus;
0283     struct orion_mdio_dev *dev;
0284     int i, ret;
0285
0286     type = (enum orion_mdio_bus_type)device_get_match_data(&pdev->dev);
0287
0288     r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0289     if (!r) {
0290         dev_err(&pdev->dev, "No SMI register address given\n");
0291         return -ENODEV;
0292     }
0293
0294     bus = devm_mdiobus_alloc_size(&pdev->dev,
0295                       sizeof(struct orion_mdio_dev));
0296     if (!bus)
0297         return -ENOMEM;
0298
0299     switch (type) {
0300     case BUS_TYPE_SMI:
0301         bus->read = orion_mdio_smi_read;
0302         bus->write = orion_mdio_smi_write;
0303         break;
0304     case BUS_TYPE_XSMI:
0305         bus->read = orion_mdio_xsmi_read;
0306         bus->write = orion_mdio_xsmi_write;
0307         break;
0308     }
0309
0310     bus->name = "orion_mdio_bus";
0311     snprintf(bus->id, MII_BUS_ID_SIZE, "%s-mii",
0312          dev_name(&pdev->dev));
0313     bus->parent = &pdev->dev;
0314
0315     dev = bus->priv;
0316     dev->regs = devm_ioremap(&pdev->dev, r->start, resource_size(r));
0317     if (!dev->regs) {
0318         dev_err(&pdev->dev, "Unable to remap SMI register\n");
0319         return -ENODEV;
0320     }
0321
0322     init_waitqueue_head(&dev->smi_busy_wait);
0323
0324     if (pdev->dev.of_node) {
0325         for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
0326             dev->clk[i] = of_clk_get(pdev->dev.of_node, i);
0327             if (PTR_ERR(dev->clk[i]) == -EPROBE_DEFER) {
0328                 ret = -EPROBE_DEFER;
0329                 goto out_clk;
0330             }
0331             if (IS_ERR(dev->clk[i]))
0332                 break;
0333             clk_prepare_enable(dev->clk[i]);
0334         }
0335
0336         if (!IS_ERR(of_clk_get(pdev->dev.of_node,
0337                        ARRAY_SIZE(dev->clk))))
0338             dev_warn(&pdev->dev,
0339                  "unsupported number of clocks, limiting to the first "
0340                  __stringify(ARRAY_SIZE(dev->clk)) "\n");
0341     } else {
0342         dev->clk[0] = clk_get(&pdev->dev, NULL);
0343         if (PTR_ERR(dev->clk[0]) == -EPROBE_DEFER) {
0344             ret = -EPROBE_DEFER;
0345             goto out_clk;
0346         }
0347         if (!IS_ERR(dev->clk[0]))
0348             clk_prepare_enable(dev->clk[0]);
0349     }
0350
0351
0352     dev->err_interrupt = platform_get_irq_optional(pdev, 0);
0353     if (dev->err_interrupt > 0 &&
0354         resource_size(r) < MVMDIO_ERR_INT_MASK + 4) {
0355         dev_err(&pdev->dev,
0356             "disabling interrupt, resource size is too small\n");
0357         dev->err_interrupt = 0;
0358     }
0359     if (dev->err_interrupt > 0) {
0360         ret = devm_request_irq(&pdev->dev, dev->err_interrupt,
0361                     orion_mdio_err_irq,
0362                     IRQF_SHARED, pdev->name, dev);
0363         if (ret)
0364             goto out_mdio;
0365
0366         writel(MVMDIO_ERR_INT_SMI_DONE,
0367             dev->regs + MVMDIO_ERR_INT_MASK);
0368
0369     } else if (dev->err_interrupt == -EPROBE_DEFER) {
0370         ret = -EPROBE_DEFER;
0371         goto out_mdio;
0372     }
0373
0374     /* For the platforms not supporting DT/ACPI fall-back
0375      * to mdiobus_register via of_mdiobus_register.
0376      */
0377     if (is_acpi_node(pdev->dev.fwnode))
0378         ret = acpi_mdiobus_register(bus, pdev->dev.fwnode);
0379     else
0380         ret = of_mdiobus_register(bus, pdev->dev.of_node);
0381     if (ret < 0) {
0382         dev_err(&pdev->dev, "Cannot register MDIO bus (%d)\n", ret);
0383         goto out_mdio;
0384     }
0385
0386     platform_set_drvdata(pdev, bus);
0387
0388     return 0;
0389
0390 out_mdio:
0391     if (dev->err_interrupt > 0)
0392         writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
0393
0394 out_clk:
0395     for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
0396         if (IS_ERR(dev->clk[i]))
0397             break;
0398         clk_disable_unprepare(dev->clk[i]);
0399         clk_put(dev->clk[i]);
0400     }
0401
0402     return ret;
0403 }
0404
0405 static int orion_mdio_remove(struct platform_device *pdev)
0406 {
0407     struct mii_bus *bus = platform_get_drvdata(pdev);
0408     struct orion_mdio_dev *dev = bus->priv;
0409     int i;
0410
0411     if (dev->err_interrupt > 0)
0412         writel(0, dev->regs + MVMDIO_ERR_INT_MASK);
0413     mdiobus_unregister(bus);
0414
0415     for (i = 0; i < ARRAY_SIZE(dev->clk); i++) {
0416         if (IS_ERR(dev->clk[i]))
0417             break;
0418         clk_disable_unprepare(dev->clk[i]);
0419         clk_put(dev->clk[i]);
0420     }
0421
0422     return 0;
0423 }
0424
0425 static const struct of_device_id orion_mdio_match[] = {
0426     { .compatible = "marvell,orion-mdio", .data = (void *)BUS_TYPE_SMI },
0427     { .compatible = "marvell,xmdio", .data = (void *)BUS_TYPE_XSMI },
0428     { }
0429 };
0430 MODULE_DEVICE_TABLE(of, orion_mdio_match);
0431
0432 #ifdef CONFIG_ACPI
0433 static const struct acpi_device_id orion_mdio_acpi_match[] = {
0434     { "MRVL0100", BUS_TYPE_SMI },
0435     { "MRVL0101", BUS_TYPE_XSMI },
0436     { },
0437 };
0438 MODULE_DEVICE_TABLE(acpi, orion_mdio_acpi_match);
0439 #endif
0440
0441 static struct platform_driver orion_mdio_driver = {
0442     .probe = orion_mdio_probe,
0443     .remove = orion_mdio_remove,
0444     .driver = {
0445         .name = "orion-mdio",
0446         .of_match_table = orion_mdio_match,
0447         .acpi_match_table = ACPI_PTR(orion_mdio_acpi_match),
0448     },
0449 };
0450
0451 module_platform_driver(orion_mdio_driver);
0452
0453 MODULE_DESCRIPTION("Marvell MDIO interface driver");
0454 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
0455 MODULE_LICENSE("GPL");
0456 MODULE_ALIAS("platform:orion-mdio");