Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *
0004  *   Copyright (C) 2011 John Crispin <blogic@openwrt.org>
0005  */
0006 
0007 #include <linux/kernel.h>
0008 #include <linux/slab.h>
0009 #include <linux/errno.h>
0010 #include <linux/types.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/uaccess.h>
0013 #include <linux/in.h>
0014 #include <linux/netdevice.h>
0015 #include <linux/etherdevice.h>
0016 #include <linux/phy.h>
0017 #include <linux/ip.h>
0018 #include <linux/tcp.h>
0019 #include <linux/skbuff.h>
0020 #include <linux/mm.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/ethtool.h>
0023 #include <linux/init.h>
0024 #include <linux/delay.h>
0025 #include <linux/io.h>
0026 #include <linux/dma-mapping.h>
0027 #include <linux/module.h>
0028 #include <linux/property.h>
0029 
0030 #include <asm/checksum.h>
0031 
0032 #include <lantiq_soc.h>
0033 #include <xway_dma.h>
0034 #include <lantiq_platform.h>
0035 
0036 #define LTQ_ETOP_MDIO       0x11804
0037 #define MDIO_REQUEST        0x80000000
0038 #define MDIO_READ       0x40000000
0039 #define MDIO_ADDR_MASK      0x1f
0040 #define MDIO_ADDR_OFFSET    0x15
0041 #define MDIO_REG_MASK       0x1f
0042 #define MDIO_REG_OFFSET     0x10
0043 #define MDIO_VAL_MASK       0xffff
0044 
0045 #define PPE32_CGEN      0x800
0046 #define LQ_PPE32_ENET_MAC_CFG   0x1840
0047 
0048 #define LTQ_ETOP_ENETS0     0x11850
0049 #define LTQ_ETOP_MAC_DA0    0x1186C
0050 #define LTQ_ETOP_MAC_DA1    0x11870
0051 #define LTQ_ETOP_CFG        0x16020
0052 #define LTQ_ETOP_IGPLEN     0x16080
0053 
0054 #define MAX_DMA_CHAN        0x8
0055 #define MAX_DMA_CRC_LEN     0x4
0056 #define MAX_DMA_DATA_LEN    0x600
0057 
0058 #define ETOP_FTCU       BIT(28)
0059 #define ETOP_MII_MASK       0xf
0060 #define ETOP_MII_NORMAL     0xd
0061 #define ETOP_MII_REVERSE    0xe
0062 #define ETOP_PLEN_UNDER     0x40
0063 #define ETOP_CGEN       0x800
0064 
0065 /* use 2 static channels for TX/RX */
0066 #define LTQ_ETOP_TX_CHANNEL 1
0067 #define LTQ_ETOP_RX_CHANNEL 6
0068 #define IS_TX(x)        ((x) == LTQ_ETOP_TX_CHANNEL)
0069 #define IS_RX(x)        ((x) == LTQ_ETOP_RX_CHANNEL)
0070 
0071 #define ltq_etop_r32(x)     ltq_r32(ltq_etop_membase + (x))
0072 #define ltq_etop_w32(x, y)  ltq_w32(x, ltq_etop_membase + (y))
0073 #define ltq_etop_w32_mask(x, y, z)  \
0074         ltq_w32_mask(x, y, ltq_etop_membase + (z))
0075 
0076 #define DRV_VERSION "1.0"
0077 
0078 static void __iomem *ltq_etop_membase;
0079 
0080 struct ltq_etop_chan {
0081     int idx;
0082     int tx_free;
0083     struct net_device *netdev;
0084     struct napi_struct napi;
0085     struct ltq_dma_channel dma;
0086     struct sk_buff *skb[LTQ_DESC_NUM];
0087 };
0088 
0089 struct ltq_etop_priv {
0090     struct net_device *netdev;
0091     struct platform_device *pdev;
0092     struct ltq_eth_data *pldata;
0093     struct resource *res;
0094 
0095     struct mii_bus *mii_bus;
0096 
0097     struct ltq_etop_chan ch[MAX_DMA_CHAN];
0098     int tx_free[MAX_DMA_CHAN >> 1];
0099 
0100     int tx_burst_len;
0101     int rx_burst_len;
0102 
0103     spinlock_t lock;
0104 };
0105 
0106 static int
0107 ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
0108 {
0109     struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
0110 
0111     ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
0112     if (!ch->skb[ch->dma.desc])
0113         return -ENOMEM;
0114     ch->dma.desc_base[ch->dma.desc].addr =
0115         dma_map_single(&priv->pdev->dev, ch->skb[ch->dma.desc]->data,
0116                    MAX_DMA_DATA_LEN, DMA_FROM_DEVICE);
0117     ch->dma.desc_base[ch->dma.desc].addr =
0118         CPHYSADDR(ch->skb[ch->dma.desc]->data);
0119     ch->dma.desc_base[ch->dma.desc].ctl =
0120         LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
0121         MAX_DMA_DATA_LEN;
0122     skb_reserve(ch->skb[ch->dma.desc], NET_IP_ALIGN);
0123     return 0;
0124 }
0125 
0126 static void
0127 ltq_etop_hw_receive(struct ltq_etop_chan *ch)
0128 {
0129     struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
0130     struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
0131     struct sk_buff *skb = ch->skb[ch->dma.desc];
0132     int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - MAX_DMA_CRC_LEN;
0133     unsigned long flags;
0134 
0135     spin_lock_irqsave(&priv->lock, flags);
0136     if (ltq_etop_alloc_skb(ch)) {
0137         netdev_err(ch->netdev,
0138                "failed to allocate new rx buffer, stopping DMA\n");
0139         ltq_dma_close(&ch->dma);
0140     }
0141     ch->dma.desc++;
0142     ch->dma.desc %= LTQ_DESC_NUM;
0143     spin_unlock_irqrestore(&priv->lock, flags);
0144 
0145     skb_put(skb, len);
0146     skb->protocol = eth_type_trans(skb, ch->netdev);
0147     netif_receive_skb(skb);
0148 }
0149 
0150 static int
0151 ltq_etop_poll_rx(struct napi_struct *napi, int budget)
0152 {
0153     struct ltq_etop_chan *ch = container_of(napi,
0154                 struct ltq_etop_chan, napi);
0155     int work_done = 0;
0156 
0157     while (work_done < budget) {
0158         struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
0159 
0160         if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) != LTQ_DMA_C)
0161             break;
0162         ltq_etop_hw_receive(ch);
0163         work_done++;
0164     }
0165     if (work_done < budget) {
0166         napi_complete_done(&ch->napi, work_done);
0167         ltq_dma_ack_irq(&ch->dma);
0168     }
0169     return work_done;
0170 }
0171 
0172 static int
0173 ltq_etop_poll_tx(struct napi_struct *napi, int budget)
0174 {
0175     struct ltq_etop_chan *ch =
0176         container_of(napi, struct ltq_etop_chan, napi);
0177     struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
0178     struct netdev_queue *txq =
0179         netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
0180     unsigned long flags;
0181 
0182     spin_lock_irqsave(&priv->lock, flags);
0183     while ((ch->dma.desc_base[ch->tx_free].ctl &
0184             (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
0185         dev_kfree_skb_any(ch->skb[ch->tx_free]);
0186         ch->skb[ch->tx_free] = NULL;
0187         memset(&ch->dma.desc_base[ch->tx_free], 0,
0188                sizeof(struct ltq_dma_desc));
0189         ch->tx_free++;
0190         ch->tx_free %= LTQ_DESC_NUM;
0191     }
0192     spin_unlock_irqrestore(&priv->lock, flags);
0193 
0194     if (netif_tx_queue_stopped(txq))
0195         netif_tx_start_queue(txq);
0196     napi_complete(&ch->napi);
0197     ltq_dma_ack_irq(&ch->dma);
0198     return 1;
0199 }
0200 
0201 static irqreturn_t
0202 ltq_etop_dma_irq(int irq, void *_priv)
0203 {
0204     struct ltq_etop_priv *priv = _priv;
0205     int ch = irq - LTQ_DMA_CH0_INT;
0206 
0207     napi_schedule(&priv->ch[ch].napi);
0208     return IRQ_HANDLED;
0209 }
0210 
0211 static void
0212 ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
0213 {
0214     struct ltq_etop_priv *priv = netdev_priv(dev);
0215 
0216     ltq_dma_free(&ch->dma);
0217     if (ch->dma.irq)
0218         free_irq(ch->dma.irq, priv);
0219     if (IS_RX(ch->idx)) {
0220         int desc;
0221 
0222         for (desc = 0; desc < LTQ_DESC_NUM; desc++)
0223             dev_kfree_skb_any(ch->skb[ch->dma.desc]);
0224     }
0225 }
0226 
0227 static void
0228 ltq_etop_hw_exit(struct net_device *dev)
0229 {
0230     struct ltq_etop_priv *priv = netdev_priv(dev);
0231     int i;
0232 
0233     ltq_pmu_disable(PMU_PPE);
0234     for (i = 0; i < MAX_DMA_CHAN; i++)
0235         if (IS_TX(i) || IS_RX(i))
0236             ltq_etop_free_channel(dev, &priv->ch[i]);
0237 }
0238 
0239 static int
0240 ltq_etop_hw_init(struct net_device *dev)
0241 {
0242     struct ltq_etop_priv *priv = netdev_priv(dev);
0243     int i;
0244     int err;
0245 
0246     ltq_pmu_enable(PMU_PPE);
0247 
0248     switch (priv->pldata->mii_mode) {
0249     case PHY_INTERFACE_MODE_RMII:
0250         ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_REVERSE,
0251                   LTQ_ETOP_CFG);
0252         break;
0253 
0254     case PHY_INTERFACE_MODE_MII:
0255         ltq_etop_w32_mask(ETOP_MII_MASK, ETOP_MII_NORMAL,
0256                   LTQ_ETOP_CFG);
0257         break;
0258 
0259     default:
0260         netdev_err(dev, "unknown mii mode %d\n",
0261                priv->pldata->mii_mode);
0262         return -ENOTSUPP;
0263     }
0264 
0265     /* enable crc generation */
0266     ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
0267 
0268     ltq_dma_init_port(DMA_PORT_ETOP, priv->tx_burst_len, priv->rx_burst_len);
0269 
0270     for (i = 0; i < MAX_DMA_CHAN; i++) {
0271         int irq = LTQ_DMA_CH0_INT + i;
0272         struct ltq_etop_chan *ch = &priv->ch[i];
0273 
0274         ch->dma.nr = i;
0275         ch->idx = ch->dma.nr;
0276         ch->dma.dev = &priv->pdev->dev;
0277 
0278         if (IS_TX(i)) {
0279             ltq_dma_alloc_tx(&ch->dma);
0280             err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_tx", priv);
0281             if (err) {
0282                 netdev_err(dev,
0283                        "Unable to get Tx DMA IRQ %d\n",
0284                        irq);
0285                 return err;
0286             }
0287         } else if (IS_RX(i)) {
0288             ltq_dma_alloc_rx(&ch->dma);
0289             for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
0290                     ch->dma.desc++)
0291                 if (ltq_etop_alloc_skb(ch))
0292                     return -ENOMEM;
0293             ch->dma.desc = 0;
0294             err = request_irq(irq, ltq_etop_dma_irq, 0, "etop_rx", priv);
0295             if (err) {
0296                 netdev_err(dev,
0297                        "Unable to get Rx DMA IRQ %d\n",
0298                        irq);
0299                 return err;
0300             }
0301         }
0302         ch->dma.irq = irq;
0303     }
0304     return 0;
0305 }
0306 
0307 static void
0308 ltq_etop_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
0309 {
0310     strscpy(info->driver, "Lantiq ETOP", sizeof(info->driver));
0311     strscpy(info->bus_info, "internal", sizeof(info->bus_info));
0312     strscpy(info->version, DRV_VERSION, sizeof(info->version));
0313 }
0314 
0315 static const struct ethtool_ops ltq_etop_ethtool_ops = {
0316     .get_drvinfo = ltq_etop_get_drvinfo,
0317     .nway_reset = phy_ethtool_nway_reset,
0318     .get_link_ksettings = phy_ethtool_get_link_ksettings,
0319     .set_link_ksettings = phy_ethtool_set_link_ksettings,
0320 };
0321 
0322 static int
0323 ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
0324 {
0325     u32 val = MDIO_REQUEST |
0326         ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
0327         ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET) |
0328         phy_data;
0329 
0330     while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
0331         ;
0332     ltq_etop_w32(val, LTQ_ETOP_MDIO);
0333     return 0;
0334 }
0335 
0336 static int
0337 ltq_etop_mdio_rd(struct mii_bus *bus, int phy_addr, int phy_reg)
0338 {
0339     u32 val = MDIO_REQUEST | MDIO_READ |
0340         ((phy_addr & MDIO_ADDR_MASK) << MDIO_ADDR_OFFSET) |
0341         ((phy_reg & MDIO_REG_MASK) << MDIO_REG_OFFSET);
0342 
0343     while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
0344         ;
0345     ltq_etop_w32(val, LTQ_ETOP_MDIO);
0346     while (ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_REQUEST)
0347         ;
0348     val = ltq_etop_r32(LTQ_ETOP_MDIO) & MDIO_VAL_MASK;
0349     return val;
0350 }
0351 
0352 static void
0353 ltq_etop_mdio_link(struct net_device *dev)
0354 {
0355     /* nothing to do  */
0356 }
0357 
0358 static int
0359 ltq_etop_mdio_probe(struct net_device *dev)
0360 {
0361     struct ltq_etop_priv *priv = netdev_priv(dev);
0362     struct phy_device *phydev;
0363 
0364     phydev = phy_find_first(priv->mii_bus);
0365 
0366     if (!phydev) {
0367         netdev_err(dev, "no PHY found\n");
0368         return -ENODEV;
0369     }
0370 
0371     phydev = phy_connect(dev, phydev_name(phydev),
0372                  &ltq_etop_mdio_link, priv->pldata->mii_mode);
0373 
0374     if (IS_ERR(phydev)) {
0375         netdev_err(dev, "Could not attach to PHY\n");
0376         return PTR_ERR(phydev);
0377     }
0378 
0379     phy_set_max_speed(phydev, SPEED_100);
0380 
0381     phy_attached_info(phydev);
0382 
0383     return 0;
0384 }
0385 
0386 static int
0387 ltq_etop_mdio_init(struct net_device *dev)
0388 {
0389     struct ltq_etop_priv *priv = netdev_priv(dev);
0390     int err;
0391 
0392     priv->mii_bus = mdiobus_alloc();
0393     if (!priv->mii_bus) {
0394         netdev_err(dev, "failed to allocate mii bus\n");
0395         err = -ENOMEM;
0396         goto err_out;
0397     }
0398 
0399     priv->mii_bus->priv = dev;
0400     priv->mii_bus->read = ltq_etop_mdio_rd;
0401     priv->mii_bus->write = ltq_etop_mdio_wr;
0402     priv->mii_bus->name = "ltq_mii";
0403     snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
0404          priv->pdev->name, priv->pdev->id);
0405     if (mdiobus_register(priv->mii_bus)) {
0406         err = -ENXIO;
0407         goto err_out_free_mdiobus;
0408     }
0409 
0410     if (ltq_etop_mdio_probe(dev)) {
0411         err = -ENXIO;
0412         goto err_out_unregister_bus;
0413     }
0414     return 0;
0415 
0416 err_out_unregister_bus:
0417     mdiobus_unregister(priv->mii_bus);
0418 err_out_free_mdiobus:
0419     mdiobus_free(priv->mii_bus);
0420 err_out:
0421     return err;
0422 }
0423 
0424 static void
0425 ltq_etop_mdio_cleanup(struct net_device *dev)
0426 {
0427     struct ltq_etop_priv *priv = netdev_priv(dev);
0428 
0429     phy_disconnect(dev->phydev);
0430     mdiobus_unregister(priv->mii_bus);
0431     mdiobus_free(priv->mii_bus);
0432 }
0433 
0434 static int
0435 ltq_etop_open(struct net_device *dev)
0436 {
0437     struct ltq_etop_priv *priv = netdev_priv(dev);
0438     int i;
0439 
0440     for (i = 0; i < MAX_DMA_CHAN; i++) {
0441         struct ltq_etop_chan *ch = &priv->ch[i];
0442 
0443         if (!IS_TX(i) && (!IS_RX(i)))
0444             continue;
0445         ltq_dma_open(&ch->dma);
0446         ltq_dma_enable_irq(&ch->dma);
0447         napi_enable(&ch->napi);
0448     }
0449     phy_start(dev->phydev);
0450     netif_tx_start_all_queues(dev);
0451     return 0;
0452 }
0453 
0454 static int
0455 ltq_etop_stop(struct net_device *dev)
0456 {
0457     struct ltq_etop_priv *priv = netdev_priv(dev);
0458     int i;
0459 
0460     netif_tx_stop_all_queues(dev);
0461     phy_stop(dev->phydev);
0462     for (i = 0; i < MAX_DMA_CHAN; i++) {
0463         struct ltq_etop_chan *ch = &priv->ch[i];
0464 
0465         if (!IS_RX(i) && !IS_TX(i))
0466             continue;
0467         napi_disable(&ch->napi);
0468         ltq_dma_close(&ch->dma);
0469     }
0470     return 0;
0471 }
0472 
0473 static int
0474 ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
0475 {
0476     int queue = skb_get_queue_mapping(skb);
0477     struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
0478     struct ltq_etop_priv *priv = netdev_priv(dev);
0479     struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
0480     struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
0481     int len;
0482     unsigned long flags;
0483     u32 byte_offset;
0484 
0485     len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
0486 
0487     if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
0488         dev_kfree_skb_any(skb);
0489         netdev_err(dev, "tx ring full\n");
0490         netif_tx_stop_queue(txq);
0491         return NETDEV_TX_BUSY;
0492     }
0493 
0494     /* dma needs to start on a burst length value aligned address */
0495     byte_offset = CPHYSADDR(skb->data) % (priv->tx_burst_len * 4);
0496     ch->skb[ch->dma.desc] = skb;
0497 
0498     netif_trans_update(dev);
0499 
0500     spin_lock_irqsave(&priv->lock, flags);
0501     desc->addr = ((unsigned int)dma_map_single(&priv->pdev->dev, skb->data, len,
0502                         DMA_TO_DEVICE)) - byte_offset;
0503     /* Make sure the address is written before we give it to HW */
0504     wmb();
0505     desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
0506         LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
0507     ch->dma.desc++;
0508     ch->dma.desc %= LTQ_DESC_NUM;
0509     spin_unlock_irqrestore(&priv->lock, flags);
0510 
0511     if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
0512         netif_tx_stop_queue(txq);
0513 
0514     return NETDEV_TX_OK;
0515 }
0516 
0517 static int
0518 ltq_etop_change_mtu(struct net_device *dev, int new_mtu)
0519 {
0520     struct ltq_etop_priv *priv = netdev_priv(dev);
0521     unsigned long flags;
0522 
0523     dev->mtu = new_mtu;
0524 
0525     spin_lock_irqsave(&priv->lock, flags);
0526     ltq_etop_w32((ETOP_PLEN_UNDER << 16) | new_mtu, LTQ_ETOP_IGPLEN);
0527     spin_unlock_irqrestore(&priv->lock, flags);
0528 
0529     return 0;
0530 }
0531 
0532 static int
0533 ltq_etop_set_mac_address(struct net_device *dev, void *p)
0534 {
0535     int ret = eth_mac_addr(dev, p);
0536 
0537     if (!ret) {
0538         struct ltq_etop_priv *priv = netdev_priv(dev);
0539         unsigned long flags;
0540 
0541         /* store the mac for the unicast filter */
0542         spin_lock_irqsave(&priv->lock, flags);
0543         ltq_etop_w32(*((u32 *)dev->dev_addr), LTQ_ETOP_MAC_DA0);
0544         ltq_etop_w32(*((u16 *)&dev->dev_addr[4]) << 16,
0545                  LTQ_ETOP_MAC_DA1);
0546         spin_unlock_irqrestore(&priv->lock, flags);
0547     }
0548     return ret;
0549 }
0550 
0551 static void
0552 ltq_etop_set_multicast_list(struct net_device *dev)
0553 {
0554     struct ltq_etop_priv *priv = netdev_priv(dev);
0555     unsigned long flags;
0556 
0557     /* ensure that the unicast filter is not enabled in promiscious mode */
0558     spin_lock_irqsave(&priv->lock, flags);
0559     if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI))
0560         ltq_etop_w32_mask(ETOP_FTCU, 0, LTQ_ETOP_ENETS0);
0561     else
0562         ltq_etop_w32_mask(0, ETOP_FTCU, LTQ_ETOP_ENETS0);
0563     spin_unlock_irqrestore(&priv->lock, flags);
0564 }
0565 
0566 static int
0567 ltq_etop_init(struct net_device *dev)
0568 {
0569     struct ltq_etop_priv *priv = netdev_priv(dev);
0570     struct sockaddr mac;
0571     int err;
0572     bool random_mac = false;
0573 
0574     dev->watchdog_timeo = 10 * HZ;
0575     err = ltq_etop_hw_init(dev);
0576     if (err)
0577         goto err_hw;
0578     ltq_etop_change_mtu(dev, 1500);
0579 
0580     memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
0581     if (!is_valid_ether_addr(mac.sa_data)) {
0582         pr_warn("etop: invalid MAC, using random\n");
0583         eth_random_addr(mac.sa_data);
0584         random_mac = true;
0585     }
0586 
0587     err = ltq_etop_set_mac_address(dev, &mac);
0588     if (err)
0589         goto err_netdev;
0590 
0591     /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
0592     if (random_mac)
0593         dev->addr_assign_type = NET_ADDR_RANDOM;
0594 
0595     ltq_etop_set_multicast_list(dev);
0596     err = ltq_etop_mdio_init(dev);
0597     if (err)
0598         goto err_netdev;
0599     return 0;
0600 
0601 err_netdev:
0602     unregister_netdev(dev);
0603     free_netdev(dev);
0604 err_hw:
0605     ltq_etop_hw_exit(dev);
0606     return err;
0607 }
0608 
0609 static void
0610 ltq_etop_tx_timeout(struct net_device *dev, unsigned int txqueue)
0611 {
0612     int err;
0613 
0614     ltq_etop_hw_exit(dev);
0615     err = ltq_etop_hw_init(dev);
0616     if (err)
0617         goto err_hw;
0618     netif_trans_update(dev);
0619     netif_wake_queue(dev);
0620     return;
0621 
0622 err_hw:
0623     ltq_etop_hw_exit(dev);
0624     netdev_err(dev, "failed to restart etop after TX timeout\n");
0625 }
0626 
0627 static const struct net_device_ops ltq_eth_netdev_ops = {
0628     .ndo_open = ltq_etop_open,
0629     .ndo_stop = ltq_etop_stop,
0630     .ndo_start_xmit = ltq_etop_tx,
0631     .ndo_change_mtu = ltq_etop_change_mtu,
0632     .ndo_eth_ioctl = phy_do_ioctl,
0633     .ndo_set_mac_address = ltq_etop_set_mac_address,
0634     .ndo_validate_addr = eth_validate_addr,
0635     .ndo_set_rx_mode = ltq_etop_set_multicast_list,
0636     .ndo_select_queue = dev_pick_tx_zero,
0637     .ndo_init = ltq_etop_init,
0638     .ndo_tx_timeout = ltq_etop_tx_timeout,
0639 };
0640 
0641 static int __init
0642 ltq_etop_probe(struct platform_device *pdev)
0643 {
0644     struct net_device *dev;
0645     struct ltq_etop_priv *priv;
0646     struct resource *res;
0647     int err;
0648     int i;
0649 
0650     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0651     if (!res) {
0652         dev_err(&pdev->dev, "failed to get etop resource\n");
0653         err = -ENOENT;
0654         goto err_out;
0655     }
0656 
0657     res = devm_request_mem_region(&pdev->dev, res->start,
0658                       resource_size(res), dev_name(&pdev->dev));
0659     if (!res) {
0660         dev_err(&pdev->dev, "failed to request etop resource\n");
0661         err = -EBUSY;
0662         goto err_out;
0663     }
0664 
0665     ltq_etop_membase = devm_ioremap(&pdev->dev, res->start,
0666                     resource_size(res));
0667     if (!ltq_etop_membase) {
0668         dev_err(&pdev->dev, "failed to remap etop engine %d\n",
0669             pdev->id);
0670         err = -ENOMEM;
0671         goto err_out;
0672     }
0673 
0674     dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
0675     if (!dev) {
0676         err = -ENOMEM;
0677         goto err_out;
0678     }
0679     strcpy(dev->name, "eth%d");
0680     dev->netdev_ops = &ltq_eth_netdev_ops;
0681     dev->ethtool_ops = &ltq_etop_ethtool_ops;
0682     priv = netdev_priv(dev);
0683     priv->res = res;
0684     priv->pdev = pdev;
0685     priv->pldata = dev_get_platdata(&pdev->dev);
0686     priv->netdev = dev;
0687     spin_lock_init(&priv->lock);
0688     SET_NETDEV_DEV(dev, &pdev->dev);
0689 
0690     err = device_property_read_u32(&pdev->dev, "lantiq,tx-burst-length", &priv->tx_burst_len);
0691     if (err < 0) {
0692         dev_err(&pdev->dev, "unable to read tx-burst-length property\n");
0693         goto err_free;
0694     }
0695 
0696     err = device_property_read_u32(&pdev->dev, "lantiq,rx-burst-length", &priv->rx_burst_len);
0697     if (err < 0) {
0698         dev_err(&pdev->dev, "unable to read rx-burst-length property\n");
0699         goto err_free;
0700     }
0701 
0702     for (i = 0; i < MAX_DMA_CHAN; i++) {
0703         if (IS_TX(i))
0704             netif_napi_add_weight(dev, &priv->ch[i].napi,
0705                           ltq_etop_poll_tx, 8);
0706         else if (IS_RX(i))
0707             netif_napi_add_weight(dev, &priv->ch[i].napi,
0708                           ltq_etop_poll_rx, 32);
0709         priv->ch[i].netdev = dev;
0710     }
0711 
0712     err = register_netdev(dev);
0713     if (err)
0714         goto err_free;
0715 
0716     platform_set_drvdata(pdev, dev);
0717     return 0;
0718 
0719 err_free:
0720     free_netdev(dev);
0721 err_out:
0722     return err;
0723 }
0724 
0725 static int
0726 ltq_etop_remove(struct platform_device *pdev)
0727 {
0728     struct net_device *dev = platform_get_drvdata(pdev);
0729 
0730     if (dev) {
0731         netif_tx_stop_all_queues(dev);
0732         ltq_etop_hw_exit(dev);
0733         ltq_etop_mdio_cleanup(dev);
0734         unregister_netdev(dev);
0735     }
0736     return 0;
0737 }
0738 
0739 static struct platform_driver ltq_mii_driver = {
0740     .remove = ltq_etop_remove,
0741     .driver = {
0742         .name = "ltq_etop",
0743     },
0744 };
0745 
0746 static int __init
0747 init_ltq_etop(void)
0748 {
0749     int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
0750 
0751     if (ret)
0752         pr_err("ltq_etop: Error registering platform driver!");
0753     return ret;
0754 }
0755 
0756 static void __exit
0757 exit_ltq_etop(void)
0758 {
0759     platform_driver_unregister(&ltq_mii_driver);
0760 }
0761 
0762 module_init(init_ltq_etop);
0763 module_exit(exit_ltq_etop);
0764 
0765 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
0766 MODULE_DESCRIPTION("Lantiq SoC ETOP");
0767 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!