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0001 /*
0002  *  Driver for the IDT RC32434 (Korina) on-chip ethernet controller.
0003  *
0004  *  Copyright 2004 IDT Inc. (rischelp@idt.com)
0005  *  Copyright 2006 Felix Fietkau <nbd@openwrt.org>
0006  *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
0007  *  Copyright 2017 Roman Yeryomin <roman@advem.lv>
0008  *
0009  *  This program is free software; you can redistribute  it and/or modify it
0010  *  under  the terms of  the GNU General  Public License as published by the
0011  *  Free Software Foundation;  either version 2 of the  License, or (at your
0012  *  option) any later version.
0013  *
0014  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
0015  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
0016  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
0017  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
0018  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
0019  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
0020  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
0021  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
0022  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
0023  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
0024  *
0025  *  You should have received a copy of the  GNU General Public License along
0026  *  with this program; if not, write  to the Free Software Foundation, Inc.,
0027  *  675 Mass Ave, Cambridge, MA 02139, USA.
0028  *
0029  *  Writing to a DMA status register:
0030  *
0031  *  When writing to the status register, you should mask the bit you have
0032  *  been testing the status register with. Both Tx and Rx DMA registers
0033  *  should stick to this procedure.
0034  */
0035 
0036 #include <linux/module.h>
0037 #include <linux/kernel.h>
0038 #include <linux/moduleparam.h>
0039 #include <linux/sched.h>
0040 #include <linux/ctype.h>
0041 #include <linux/types.h>
0042 #include <linux/interrupt.h>
0043 #include <linux/ioport.h>
0044 #include <linux/iopoll.h>
0045 #include <linux/in.h>
0046 #include <linux/of_device.h>
0047 #include <linux/of_net.h>
0048 #include <linux/slab.h>
0049 #include <linux/string.h>
0050 #include <linux/delay.h>
0051 #include <linux/netdevice.h>
0052 #include <linux/etherdevice.h>
0053 #include <linux/skbuff.h>
0054 #include <linux/errno.h>
0055 #include <linux/platform_device.h>
0056 #include <linux/mii.h>
0057 #include <linux/ethtool.h>
0058 #include <linux/crc32.h>
0059 #include <linux/pgtable.h>
0060 #include <linux/clk.h>
0061 
0062 #define DRV_NAME    "korina"
0063 #define DRV_VERSION "0.20"
0064 #define DRV_RELDATE "15Sep2017"
0065 
0066 struct eth_regs {
0067     u32 ethintfc;
0068     u32 ethfifott;
0069     u32 etharc;
0070     u32 ethhash0;
0071     u32 ethhash1;
0072     u32 ethu0[4];       /* Reserved. */
0073     u32 ethpfs;
0074     u32 ethmcp;
0075     u32 eth_u1[10];     /* Reserved. */
0076     u32 ethspare;
0077     u32 eth_u2[42];     /* Reserved. */
0078     u32 ethsal0;
0079     u32 ethsah0;
0080     u32 ethsal1;
0081     u32 ethsah1;
0082     u32 ethsal2;
0083     u32 ethsah2;
0084     u32 ethsal3;
0085     u32 ethsah3;
0086     u32 ethrbc;
0087     u32 ethrpc;
0088     u32 ethrupc;
0089     u32 ethrfc;
0090     u32 ethtbc;
0091     u32 ethgpf;
0092     u32 eth_u9[50];     /* Reserved. */
0093     u32 ethmac1;
0094     u32 ethmac2;
0095     u32 ethipgt;
0096     u32 ethipgr;
0097     u32 ethclrt;
0098     u32 ethmaxf;
0099     u32 eth_u10;        /* Reserved. */
0100     u32 ethmtest;
0101     u32 miimcfg;
0102     u32 miimcmd;
0103     u32 miimaddr;
0104     u32 miimwtd;
0105     u32 miimrdd;
0106     u32 miimind;
0107     u32 eth_u11;        /* Reserved. */
0108     u32 eth_u12;        /* Reserved. */
0109     u32 ethcfsa0;
0110     u32 ethcfsa1;
0111     u32 ethcfsa2;
0112 };
0113 
0114 /* Ethernet interrupt registers */
0115 #define ETH_INT_FC_EN       BIT(0)
0116 #define ETH_INT_FC_ITS      BIT(1)
0117 #define ETH_INT_FC_RIP      BIT(2)
0118 #define ETH_INT_FC_JAM      BIT(3)
0119 #define ETH_INT_FC_OVR      BIT(4)
0120 #define ETH_INT_FC_UND      BIT(5)
0121 #define ETH_INT_FC_IOC      0x000000c0
0122 
0123 /* Ethernet FIFO registers */
0124 #define ETH_FIFI_TT_TTH_BIT 0
0125 #define ETH_FIFO_TT_TTH     0x0000007f
0126 
0127 /* Ethernet ARC/multicast registers */
0128 #define ETH_ARC_PRO     BIT(0)
0129 #define ETH_ARC_AM      BIT(1)
0130 #define ETH_ARC_AFM     BIT(2)
0131 #define ETH_ARC_AB      BIT(3)
0132 
0133 /* Ethernet SAL registers */
0134 #define ETH_SAL_BYTE_5      0x000000ff
0135 #define ETH_SAL_BYTE_4      0x0000ff00
0136 #define ETH_SAL_BYTE_3      0x00ff0000
0137 #define ETH_SAL_BYTE_2      0xff000000
0138 
0139 /* Ethernet SAH registers */
0140 #define ETH_SAH_BYTE1       0x000000ff
0141 #define ETH_SAH_BYTE0       0x0000ff00
0142 
0143 /* Ethernet GPF register */
0144 #define ETH_GPF_PTV     0x0000ffff
0145 
0146 /* Ethernet PFG register */
0147 #define ETH_PFS_PFD     BIT(0)
0148 
0149 /* Ethernet CFSA[0-3] registers */
0150 #define ETH_CFSA0_CFSA4     0x000000ff
0151 #define ETH_CFSA0_CFSA5     0x0000ff00
0152 #define ETH_CFSA1_CFSA2     0x000000ff
0153 #define ETH_CFSA1_CFSA3     0x0000ff00
0154 #define ETH_CFSA1_CFSA0     0x000000ff
0155 #define ETH_CFSA1_CFSA1     0x0000ff00
0156 
0157 /* Ethernet MAC1 registers */
0158 #define ETH_MAC1_RE     BIT(0)
0159 #define ETH_MAC1_PAF        BIT(1)
0160 #define ETH_MAC1_RFC        BIT(2)
0161 #define ETH_MAC1_TFC        BIT(3)
0162 #define ETH_MAC1_LB     BIT(4)
0163 #define ETH_MAC1_MR     BIT(31)
0164 
0165 /* Ethernet MAC2 registers */
0166 #define ETH_MAC2_FD     BIT(0)
0167 #define ETH_MAC2_FLC        BIT(1)
0168 #define ETH_MAC2_HFE        BIT(2)
0169 #define ETH_MAC2_DC     BIT(3)
0170 #define ETH_MAC2_CEN        BIT(4)
0171 #define ETH_MAC2_PE     BIT(5)
0172 #define ETH_MAC2_VPE        BIT(6)
0173 #define ETH_MAC2_APE        BIT(7)
0174 #define ETH_MAC2_PPE        BIT(8)
0175 #define ETH_MAC2_LPE        BIT(9)
0176 #define ETH_MAC2_NB     BIT(12)
0177 #define ETH_MAC2_BP     BIT(13)
0178 #define ETH_MAC2_ED     BIT(14)
0179 
0180 /* Ethernet IPGT register */
0181 #define ETH_IPGT        0x0000007f
0182 
0183 /* Ethernet IPGR registers */
0184 #define ETH_IPGR_IPGR2      0x0000007f
0185 #define ETH_IPGR_IPGR1      0x00007f00
0186 
0187 /* Ethernet CLRT registers */
0188 #define ETH_CLRT_MAX_RET    0x0000000f
0189 #define ETH_CLRT_COL_WIN    0x00003f00
0190 
0191 /* Ethernet MAXF register */
0192 #define ETH_MAXF        0x0000ffff
0193 
0194 /* Ethernet test registers */
0195 #define ETH_TEST_REG        BIT(2)
0196 #define ETH_MCP_DIV     0x000000ff
0197 
0198 /* MII registers */
0199 #define ETH_MII_CFG_RSVD    0x0000000c
0200 #define ETH_MII_CMD_RD      BIT(0)
0201 #define ETH_MII_CMD_SCN     BIT(1)
0202 #define ETH_MII_REG_ADDR    0x0000001f
0203 #define ETH_MII_PHY_ADDR    0x00001f00
0204 #define ETH_MII_WTD_DATA    0x0000ffff
0205 #define ETH_MII_RDD_DATA    0x0000ffff
0206 #define ETH_MII_IND_BSY     BIT(0)
0207 #define ETH_MII_IND_SCN     BIT(1)
0208 #define ETH_MII_IND_NV      BIT(2)
0209 
0210 /* Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors. */
0211 #define ETH_RX_FD       BIT(0)
0212 #define ETH_RX_LD       BIT(1)
0213 #define ETH_RX_ROK      BIT(2)
0214 #define ETH_RX_FM       BIT(3)
0215 #define ETH_RX_MP       BIT(4)
0216 #define ETH_RX_BP       BIT(5)
0217 #define ETH_RX_VLT      BIT(6)
0218 #define ETH_RX_CF       BIT(7)
0219 #define ETH_RX_OVR      BIT(8)
0220 #define ETH_RX_CRC      BIT(9)
0221 #define ETH_RX_CV       BIT(10)
0222 #define ETH_RX_DB       BIT(11)
0223 #define ETH_RX_LE       BIT(12)
0224 #define ETH_RX_LOR      BIT(13)
0225 #define ETH_RX_CES      BIT(14)
0226 #define ETH_RX_LEN_BIT      16
0227 #define ETH_RX_LEN      0xffff0000
0228 
0229 #define ETH_TX_FD       BIT(0)
0230 #define ETH_TX_LD       BIT(1)
0231 #define ETH_TX_OEN      BIT(2)
0232 #define ETH_TX_PEN      BIT(3)
0233 #define ETH_TX_CEN      BIT(4)
0234 #define ETH_TX_HEN      BIT(5)
0235 #define ETH_TX_TOK      BIT(6)
0236 #define ETH_TX_MP       BIT(7)
0237 #define ETH_TX_BP       BIT(8)
0238 #define ETH_TX_UND      BIT(9)
0239 #define ETH_TX_OF       BIT(10)
0240 #define ETH_TX_ED       BIT(11)
0241 #define ETH_TX_EC       BIT(12)
0242 #define ETH_TX_LC       BIT(13)
0243 #define ETH_TX_TD       BIT(14)
0244 #define ETH_TX_CRC      BIT(15)
0245 #define ETH_TX_LE       BIT(16)
0246 #define ETH_TX_CC       0x001E0000
0247 
0248 /* DMA descriptor (in physical memory). */
0249 struct dma_desc {
0250     u32 control;            /* Control. use DMAD_* */
0251     u32 ca;             /* Current Address. */
0252     u32 devcs;          /* Device control and status. */
0253     u32 link;           /* Next descriptor in chain. */
0254 };
0255 
0256 #define DMA_DESC_COUNT_BIT      0
0257 #define DMA_DESC_COUNT_MSK      0x0003ffff
0258 #define DMA_DESC_DS_BIT         20
0259 #define DMA_DESC_DS_MSK         0x00300000
0260 
0261 #define DMA_DESC_DEV_CMD_BIT        22
0262 #define DMA_DESC_DEV_CMD_MSK        0x01c00000
0263 
0264 /* DMA descriptors interrupts */
0265 #define DMA_DESC_COF            BIT(25) /* Chain on finished */
0266 #define DMA_DESC_COD            BIT(26) /* Chain on done */
0267 #define DMA_DESC_IOF            BIT(27) /* Interrupt on finished */
0268 #define DMA_DESC_IOD            BIT(28) /* Interrupt on done */
0269 #define DMA_DESC_TERM           BIT(29) /* Terminated */
0270 #define DMA_DESC_DONE           BIT(30) /* Done */
0271 #define DMA_DESC_FINI           BIT(31) /* Finished */
0272 
0273 /* DMA register (within Internal Register Map).  */
0274 struct dma_reg {
0275     u32 dmac;       /* Control. */
0276     u32 dmas;       /* Status. */
0277     u32 dmasm;      /* Mask. */
0278     u32 dmadptr;        /* Descriptor pointer. */
0279     u32 dmandptr;       /* Next descriptor pointer. */
0280 };
0281 
0282 /* DMA channels specific registers */
0283 #define DMA_CHAN_RUN_BIT        BIT(0)
0284 #define DMA_CHAN_DONE_BIT       BIT(1)
0285 #define DMA_CHAN_MODE_BIT       BIT(2)
0286 #define DMA_CHAN_MODE_MSK       0x0000000c
0287 #define  DMA_CHAN_MODE_AUTO     0
0288 #define  DMA_CHAN_MODE_BURST        1
0289 #define  DMA_CHAN_MODE_XFRT     2
0290 #define  DMA_CHAN_MODE_RSVD     3
0291 #define DMA_CHAN_ACT_BIT        BIT(4)
0292 
0293 /* DMA status registers */
0294 #define DMA_STAT_FINI           BIT(0)
0295 #define DMA_STAT_DONE           BIT(1)
0296 #define DMA_STAT_CHAIN          BIT(2)
0297 #define DMA_STAT_ERR            BIT(3)
0298 #define DMA_STAT_HALT           BIT(4)
0299 
0300 #define STATION_ADDRESS_HIGH(dev) (((dev)->dev_addr[0] << 8) | \
0301                    ((dev)->dev_addr[1]))
0302 #define STATION_ADDRESS_LOW(dev)  (((dev)->dev_addr[2] << 24) | \
0303                    ((dev)->dev_addr[3] << 16) | \
0304                    ((dev)->dev_addr[4] << 8)  | \
0305                    ((dev)->dev_addr[5]))
0306 
0307 #define MII_CLOCK   1250000 /* no more than 2.5MHz */
0308 
0309 /* the following must be powers of two */
0310 #define KORINA_NUM_RDS  64  /* number of receive descriptors */
0311 #define KORINA_NUM_TDS  64  /* number of transmit descriptors */
0312 
0313 /* KORINA_RBSIZE is the hardware's default maximum receive
0314  * frame size in bytes. Having this hardcoded means that there
0315  * is no support for MTU sizes greater than 1500. */
0316 #define KORINA_RBSIZE   1536 /* size of one resource buffer = Ether MTU */
0317 #define KORINA_RDS_MASK (KORINA_NUM_RDS - 1)
0318 #define KORINA_TDS_MASK (KORINA_NUM_TDS - 1)
0319 #define RD_RING_SIZE    (KORINA_NUM_RDS * sizeof(struct dma_desc))
0320 #define TD_RING_SIZE    (KORINA_NUM_TDS * sizeof(struct dma_desc))
0321 
0322 #define TX_TIMEOUT  (6000 * HZ / 1000)
0323 
0324 enum chain_status {
0325     desc_filled,
0326     desc_is_empty
0327 };
0328 
0329 #define DMA_COUNT(count)    ((count) & DMA_DESC_COUNT_MSK)
0330 #define IS_DMA_FINISHED(X)  (((X) & (DMA_DESC_FINI)) != 0)
0331 #define IS_DMA_DONE(X)      (((X) & (DMA_DESC_DONE)) != 0)
0332 #define RCVPKT_LENGTH(X)    (((X) & ETH_RX_LEN) >> ETH_RX_LEN_BIT)
0333 
0334 /* Information that need to be kept for each board. */
0335 struct korina_private {
0336     struct eth_regs __iomem *eth_regs;
0337     struct dma_reg __iomem *rx_dma_regs;
0338     struct dma_reg __iomem *tx_dma_regs;
0339     struct dma_desc *td_ring; /* transmit descriptor ring */
0340     struct dma_desc *rd_ring; /* receive descriptor ring  */
0341     dma_addr_t td_dma;
0342     dma_addr_t rd_dma;
0343 
0344     struct sk_buff *tx_skb[KORINA_NUM_TDS];
0345     struct sk_buff *rx_skb[KORINA_NUM_RDS];
0346 
0347     dma_addr_t rx_skb_dma[KORINA_NUM_RDS];
0348     dma_addr_t tx_skb_dma[KORINA_NUM_TDS];
0349 
0350     int rx_next_done;
0351     int rx_chain_head;
0352     int rx_chain_tail;
0353     enum chain_status rx_chain_status;
0354 
0355     int tx_next_done;
0356     int tx_chain_head;
0357     int tx_chain_tail;
0358     enum chain_status tx_chain_status;
0359     int tx_count;
0360     int tx_full;
0361 
0362     int rx_irq;
0363     int tx_irq;
0364 
0365     spinlock_t lock;    /* NIC xmit lock */
0366 
0367     int dma_halt_cnt;
0368     int dma_run_cnt;
0369     struct napi_struct napi;
0370     struct timer_list media_check_timer;
0371     struct mii_if_info mii_if;
0372     struct work_struct restart_task;
0373     struct net_device *dev;
0374     struct device *dmadev;
0375     int mii_clock_freq;
0376 };
0377 
0378 static dma_addr_t korina_tx_dma(struct korina_private *lp, int idx)
0379 {
0380     return lp->td_dma + (idx * sizeof(struct dma_desc));
0381 }
0382 
0383 static dma_addr_t korina_rx_dma(struct korina_private *lp, int idx)
0384 {
0385     return lp->rd_dma + (idx * sizeof(struct dma_desc));
0386 }
0387 
0388 static inline void korina_abort_dma(struct net_device *dev,
0389                     struct dma_reg *ch)
0390 {
0391     if (readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
0392         writel(0x10, &ch->dmac);
0393 
0394         while (!(readl(&ch->dmas) & DMA_STAT_HALT))
0395             netif_trans_update(dev);
0396 
0397         writel(0, &ch->dmas);
0398     }
0399 
0400     writel(0, &ch->dmadptr);
0401     writel(0, &ch->dmandptr);
0402 }
0403 
0404 static void korina_abort_tx(struct net_device *dev)
0405 {
0406     struct korina_private *lp = netdev_priv(dev);
0407 
0408     korina_abort_dma(dev, lp->tx_dma_regs);
0409 }
0410 
0411 static void korina_abort_rx(struct net_device *dev)
0412 {
0413     struct korina_private *lp = netdev_priv(dev);
0414 
0415     korina_abort_dma(dev, lp->rx_dma_regs);
0416 }
0417 
0418 /* transmit packet */
0419 static int korina_send_packet(struct sk_buff *skb, struct net_device *dev)
0420 {
0421     struct korina_private *lp = netdev_priv(dev);
0422     u32 chain_prev, chain_next;
0423     unsigned long flags;
0424     struct dma_desc *td;
0425     dma_addr_t ca;
0426     u32 length;
0427     int idx;
0428 
0429     spin_lock_irqsave(&lp->lock, flags);
0430 
0431     idx = lp->tx_chain_tail;
0432     td = &lp->td_ring[idx];
0433 
0434     /* stop queue when full, drop pkts if queue already full */
0435     if (lp->tx_count >= (KORINA_NUM_TDS - 2)) {
0436         lp->tx_full = 1;
0437 
0438         if (lp->tx_count == (KORINA_NUM_TDS - 2))
0439             netif_stop_queue(dev);
0440         else
0441             goto drop_packet;
0442     }
0443 
0444     lp->tx_count++;
0445 
0446     lp->tx_skb[idx] = skb;
0447 
0448     length = skb->len;
0449 
0450     /* Setup the transmit descriptor. */
0451     ca = dma_map_single(lp->dmadev, skb->data, length, DMA_TO_DEVICE);
0452     if (dma_mapping_error(lp->dmadev, ca))
0453         goto drop_packet;
0454 
0455     lp->tx_skb_dma[idx] = ca;
0456     td->ca = ca;
0457 
0458     chain_prev = (idx - 1) & KORINA_TDS_MASK;
0459     chain_next = (idx + 1) & KORINA_TDS_MASK;
0460 
0461     if (readl(&(lp->tx_dma_regs->dmandptr)) == 0) {
0462         if (lp->tx_chain_status == desc_is_empty) {
0463             /* Update tail */
0464             td->control = DMA_COUNT(length) |
0465                     DMA_DESC_COF | DMA_DESC_IOF;
0466             /* Move tail */
0467             lp->tx_chain_tail = chain_next;
0468             /* Write to NDPTR */
0469             writel(korina_tx_dma(lp, lp->tx_chain_head),
0470                    &lp->tx_dma_regs->dmandptr);
0471             /* Move head to tail */
0472             lp->tx_chain_head = lp->tx_chain_tail;
0473         } else {
0474             /* Update tail */
0475             td->control = DMA_COUNT(length) |
0476                     DMA_DESC_COF | DMA_DESC_IOF;
0477             /* Link to prev */
0478             lp->td_ring[chain_prev].control &=
0479                     ~DMA_DESC_COF;
0480             /* Link to prev */
0481             lp->td_ring[chain_prev].link = korina_tx_dma(lp, idx);
0482             /* Move tail */
0483             lp->tx_chain_tail = chain_next;
0484             /* Write to NDPTR */
0485             writel(korina_tx_dma(lp, lp->tx_chain_head),
0486                    &lp->tx_dma_regs->dmandptr);
0487             /* Move head to tail */
0488             lp->tx_chain_head = lp->tx_chain_tail;
0489             lp->tx_chain_status = desc_is_empty;
0490         }
0491     } else {
0492         if (lp->tx_chain_status == desc_is_empty) {
0493             /* Update tail */
0494             td->control = DMA_COUNT(length) |
0495                     DMA_DESC_COF | DMA_DESC_IOF;
0496             /* Move tail */
0497             lp->tx_chain_tail = chain_next;
0498             lp->tx_chain_status = desc_filled;
0499         } else {
0500             /* Update tail */
0501             td->control = DMA_COUNT(length) |
0502                     DMA_DESC_COF | DMA_DESC_IOF;
0503             lp->td_ring[chain_prev].control &=
0504                     ~DMA_DESC_COF;
0505             lp->td_ring[chain_prev].link = korina_tx_dma(lp, idx);
0506             lp->tx_chain_tail = chain_next;
0507         }
0508     }
0509 
0510     netif_trans_update(dev);
0511     spin_unlock_irqrestore(&lp->lock, flags);
0512 
0513     return NETDEV_TX_OK;
0514 
0515 drop_packet:
0516     dev->stats.tx_dropped++;
0517     dev_kfree_skb_any(skb);
0518     spin_unlock_irqrestore(&lp->lock, flags);
0519 
0520     return NETDEV_TX_OK;
0521 }
0522 
0523 static int korina_mdio_wait(struct korina_private *lp)
0524 {
0525     u32 value;
0526 
0527     return readl_poll_timeout_atomic(&lp->eth_regs->miimind,
0528                      value, value & ETH_MII_IND_BSY,
0529                      1, 1000);
0530 }
0531 
0532 static int korina_mdio_read(struct net_device *dev, int phy, int reg)
0533 {
0534     struct korina_private *lp = netdev_priv(dev);
0535     int ret;
0536 
0537     ret = korina_mdio_wait(lp);
0538     if (ret < 0)
0539         return ret;
0540 
0541     writel(phy << 8 | reg, &lp->eth_regs->miimaddr);
0542     writel(1, &lp->eth_regs->miimcmd);
0543 
0544     ret = korina_mdio_wait(lp);
0545     if (ret < 0)
0546         return ret;
0547 
0548     if (readl(&lp->eth_regs->miimind) & ETH_MII_IND_NV)
0549         return -EINVAL;
0550 
0551     ret = readl(&lp->eth_regs->miimrdd);
0552     writel(0, &lp->eth_regs->miimcmd);
0553     return ret;
0554 }
0555 
0556 static void korina_mdio_write(struct net_device *dev, int phy, int reg, int val)
0557 {
0558     struct korina_private *lp = netdev_priv(dev);
0559 
0560     if (korina_mdio_wait(lp))
0561         return;
0562 
0563     writel(0, &lp->eth_regs->miimcmd);
0564     writel(phy << 8 | reg, &lp->eth_regs->miimaddr);
0565     writel(val, &lp->eth_regs->miimwtd);
0566 }
0567 
0568 /* Ethernet Rx DMA interrupt */
0569 static irqreturn_t korina_rx_dma_interrupt(int irq, void *dev_id)
0570 {
0571     struct net_device *dev = dev_id;
0572     struct korina_private *lp = netdev_priv(dev);
0573     u32 dmas, dmasm;
0574     irqreturn_t retval;
0575 
0576     dmas = readl(&lp->rx_dma_regs->dmas);
0577     if (dmas & (DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR)) {
0578         dmasm = readl(&lp->rx_dma_regs->dmasm);
0579         writel(dmasm | (DMA_STAT_DONE |
0580                 DMA_STAT_HALT | DMA_STAT_ERR),
0581                 &lp->rx_dma_regs->dmasm);
0582 
0583         napi_schedule(&lp->napi);
0584 
0585         if (dmas & DMA_STAT_ERR)
0586             printk(KERN_ERR "%s: DMA error\n", dev->name);
0587 
0588         retval = IRQ_HANDLED;
0589     } else
0590         retval = IRQ_NONE;
0591 
0592     return retval;
0593 }
0594 
0595 static int korina_rx(struct net_device *dev, int limit)
0596 {
0597     struct korina_private *lp = netdev_priv(dev);
0598     struct dma_desc *rd = &lp->rd_ring[lp->rx_next_done];
0599     struct sk_buff *skb, *skb_new;
0600     u32 devcs, pkt_len, dmas;
0601     dma_addr_t ca;
0602     int count;
0603 
0604     for (count = 0; count < limit; count++) {
0605         skb = lp->rx_skb[lp->rx_next_done];
0606         skb_new = NULL;
0607 
0608         devcs = rd->devcs;
0609 
0610         if ((KORINA_RBSIZE - (u32)DMA_COUNT(rd->control)) == 0)
0611             break;
0612 
0613         /* check that this is a whole packet
0614          * WARNING: DMA_FD bit incorrectly set
0615          * in Rc32434 (errata ref #077) */
0616         if (!(devcs & ETH_RX_LD))
0617             goto next;
0618 
0619         if (!(devcs & ETH_RX_ROK)) {
0620             /* Update statistics counters */
0621             dev->stats.rx_errors++;
0622             dev->stats.rx_dropped++;
0623             if (devcs & ETH_RX_CRC)
0624                 dev->stats.rx_crc_errors++;
0625             if (devcs & ETH_RX_LE)
0626                 dev->stats.rx_length_errors++;
0627             if (devcs & ETH_RX_OVR)
0628                 dev->stats.rx_fifo_errors++;
0629             if (devcs & ETH_RX_CV)
0630                 dev->stats.rx_frame_errors++;
0631             if (devcs & ETH_RX_CES)
0632                 dev->stats.rx_frame_errors++;
0633 
0634             goto next;
0635         }
0636 
0637         /* Malloc up new buffer. */
0638         skb_new = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
0639         if (!skb_new)
0640             break;
0641 
0642         ca = dma_map_single(lp->dmadev, skb_new->data, KORINA_RBSIZE,
0643                     DMA_FROM_DEVICE);
0644         if (dma_mapping_error(lp->dmadev, ca)) {
0645             dev_kfree_skb_any(skb_new);
0646             break;
0647         }
0648 
0649         pkt_len = RCVPKT_LENGTH(devcs);
0650         dma_unmap_single(lp->dmadev, lp->rx_skb_dma[lp->rx_next_done],
0651                  pkt_len, DMA_FROM_DEVICE);
0652 
0653         /* Do not count the CRC */
0654         skb_put(skb, pkt_len - 4);
0655         skb->protocol = eth_type_trans(skb, dev);
0656 
0657         /* Pass the packet to upper layers */
0658         napi_gro_receive(&lp->napi, skb);
0659         dev->stats.rx_packets++;
0660         dev->stats.rx_bytes += pkt_len;
0661 
0662         /* Update the mcast stats */
0663         if (devcs & ETH_RX_MP)
0664             dev->stats.multicast++;
0665 
0666         lp->rx_skb[lp->rx_next_done] = skb_new;
0667         lp->rx_skb_dma[lp->rx_next_done] = ca;
0668 
0669 next:
0670         rd->devcs = 0;
0671 
0672         /* Restore descriptor's curr_addr */
0673         rd->ca = lp->rx_skb_dma[lp->rx_next_done];
0674 
0675         rd->control = DMA_COUNT(KORINA_RBSIZE) |
0676             DMA_DESC_COD | DMA_DESC_IOD;
0677         lp->rd_ring[(lp->rx_next_done - 1) &
0678             KORINA_RDS_MASK].control &=
0679             ~DMA_DESC_COD;
0680 
0681         lp->rx_next_done = (lp->rx_next_done + 1) & KORINA_RDS_MASK;
0682         rd = &lp->rd_ring[lp->rx_next_done];
0683         writel((u32)~DMA_STAT_DONE, &lp->rx_dma_regs->dmas);
0684     }
0685 
0686     dmas = readl(&lp->rx_dma_regs->dmas);
0687 
0688     if (dmas & DMA_STAT_HALT) {
0689         writel((u32)~(DMA_STAT_HALT | DMA_STAT_ERR),
0690                &lp->rx_dma_regs->dmas);
0691 
0692         lp->dma_halt_cnt++;
0693         rd->devcs = 0;
0694         rd->ca = lp->rx_skb_dma[lp->rx_next_done];
0695         writel(korina_rx_dma(lp, rd - lp->rd_ring),
0696                &lp->rx_dma_regs->dmandptr);
0697     }
0698 
0699     return count;
0700 }
0701 
0702 static int korina_poll(struct napi_struct *napi, int budget)
0703 {
0704     struct korina_private *lp =
0705         container_of(napi, struct korina_private, napi);
0706     struct net_device *dev = lp->dev;
0707     int work_done;
0708 
0709     work_done = korina_rx(dev, budget);
0710     if (work_done < budget) {
0711         napi_complete_done(napi, work_done);
0712 
0713         writel(readl(&lp->rx_dma_regs->dmasm) &
0714             ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
0715             &lp->rx_dma_regs->dmasm);
0716     }
0717     return work_done;
0718 }
0719 
0720 /*
0721  * Set or clear the multicast filter for this adaptor.
0722  */
0723 static void korina_multicast_list(struct net_device *dev)
0724 {
0725     struct korina_private *lp = netdev_priv(dev);
0726     unsigned long flags;
0727     struct netdev_hw_addr *ha;
0728     u32 recognise = ETH_ARC_AB; /* always accept broadcasts */
0729 
0730     /* Set promiscuous mode */
0731     if (dev->flags & IFF_PROMISC)
0732         recognise |= ETH_ARC_PRO;
0733 
0734     else if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 4))
0735         /* All multicast and broadcast */
0736         recognise |= ETH_ARC_AM;
0737 
0738     /* Build the hash table */
0739     if (netdev_mc_count(dev) > 4) {
0740         u16 hash_table[4] = { 0 };
0741         u32 crc;
0742 
0743         netdev_for_each_mc_addr(ha, dev) {
0744             crc = ether_crc_le(6, ha->addr);
0745             crc >>= 26;
0746             hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
0747         }
0748         /* Accept filtered multicast */
0749         recognise |= ETH_ARC_AFM;
0750 
0751         /* Fill the MAC hash tables with their values */
0752         writel((u32)(hash_table[1] << 16 | hash_table[0]),
0753                     &lp->eth_regs->ethhash0);
0754         writel((u32)(hash_table[3] << 16 | hash_table[2]),
0755                     &lp->eth_regs->ethhash1);
0756     }
0757 
0758     spin_lock_irqsave(&lp->lock, flags);
0759     writel(recognise, &lp->eth_regs->etharc);
0760     spin_unlock_irqrestore(&lp->lock, flags);
0761 }
0762 
0763 static void korina_tx(struct net_device *dev)
0764 {
0765     struct korina_private *lp = netdev_priv(dev);
0766     struct dma_desc *td = &lp->td_ring[lp->tx_next_done];
0767     u32 devcs;
0768     u32 dmas;
0769 
0770     spin_lock(&lp->lock);
0771 
0772     /* Process all desc that are done */
0773     while (IS_DMA_FINISHED(td->control)) {
0774         if (lp->tx_full == 1) {
0775             netif_wake_queue(dev);
0776             lp->tx_full = 0;
0777         }
0778 
0779         devcs = lp->td_ring[lp->tx_next_done].devcs;
0780         if ((devcs & (ETH_TX_FD | ETH_TX_LD)) !=
0781                 (ETH_TX_FD | ETH_TX_LD)) {
0782             dev->stats.tx_errors++;
0783             dev->stats.tx_dropped++;
0784 
0785             /* Should never happen */
0786             printk(KERN_ERR "%s: split tx ignored\n",
0787                             dev->name);
0788         } else if (devcs & ETH_TX_TOK) {
0789             dev->stats.tx_packets++;
0790             dev->stats.tx_bytes +=
0791                     lp->tx_skb[lp->tx_next_done]->len;
0792         } else {
0793             dev->stats.tx_errors++;
0794             dev->stats.tx_dropped++;
0795 
0796             /* Underflow */
0797             if (devcs & ETH_TX_UND)
0798                 dev->stats.tx_fifo_errors++;
0799 
0800             /* Oversized frame */
0801             if (devcs & ETH_TX_OF)
0802                 dev->stats.tx_aborted_errors++;
0803 
0804             /* Excessive deferrals */
0805             if (devcs & ETH_TX_ED)
0806                 dev->stats.tx_carrier_errors++;
0807 
0808             /* Collisions: medium busy */
0809             if (devcs & ETH_TX_EC)
0810                 dev->stats.collisions++;
0811 
0812             /* Late collision */
0813             if (devcs & ETH_TX_LC)
0814                 dev->stats.tx_window_errors++;
0815         }
0816 
0817         /* We must always free the original skb */
0818         if (lp->tx_skb[lp->tx_next_done]) {
0819             dma_unmap_single(lp->dmadev,
0820                      lp->tx_skb_dma[lp->tx_next_done],
0821                      lp->tx_skb[lp->tx_next_done]->len,
0822                      DMA_TO_DEVICE);
0823             dev_kfree_skb_any(lp->tx_skb[lp->tx_next_done]);
0824             lp->tx_skb[lp->tx_next_done] = NULL;
0825         }
0826 
0827         lp->td_ring[lp->tx_next_done].control = DMA_DESC_IOF;
0828         lp->td_ring[lp->tx_next_done].devcs = ETH_TX_FD | ETH_TX_LD;
0829         lp->td_ring[lp->tx_next_done].link = 0;
0830         lp->td_ring[lp->tx_next_done].ca = 0;
0831         lp->tx_count--;
0832 
0833         /* Go on to next transmission */
0834         lp->tx_next_done = (lp->tx_next_done + 1) & KORINA_TDS_MASK;
0835         td = &lp->td_ring[lp->tx_next_done];
0836 
0837     }
0838 
0839     /* Clear the DMA status register */
0840     dmas = readl(&lp->tx_dma_regs->dmas);
0841     writel(~dmas, &lp->tx_dma_regs->dmas);
0842 
0843     writel(readl(&lp->tx_dma_regs->dmasm) &
0844             ~(DMA_STAT_FINI | DMA_STAT_ERR),
0845             &lp->tx_dma_regs->dmasm);
0846 
0847     spin_unlock(&lp->lock);
0848 }
0849 
0850 static irqreturn_t
0851 korina_tx_dma_interrupt(int irq, void *dev_id)
0852 {
0853     struct net_device *dev = dev_id;
0854     struct korina_private *lp = netdev_priv(dev);
0855     u32 dmas, dmasm;
0856     irqreturn_t retval;
0857 
0858     dmas = readl(&lp->tx_dma_regs->dmas);
0859 
0860     if (dmas & (DMA_STAT_FINI | DMA_STAT_ERR)) {
0861         dmasm = readl(&lp->tx_dma_regs->dmasm);
0862         writel(dmasm | (DMA_STAT_FINI | DMA_STAT_ERR),
0863                 &lp->tx_dma_regs->dmasm);
0864 
0865         korina_tx(dev);
0866 
0867         if (lp->tx_chain_status == desc_filled &&
0868             (readl(&(lp->tx_dma_regs->dmandptr)) == 0)) {
0869             writel(korina_tx_dma(lp, lp->tx_chain_head),
0870                    &lp->tx_dma_regs->dmandptr);
0871             lp->tx_chain_status = desc_is_empty;
0872             lp->tx_chain_head = lp->tx_chain_tail;
0873             netif_trans_update(dev);
0874         }
0875         if (dmas & DMA_STAT_ERR)
0876             printk(KERN_ERR "%s: DMA error\n", dev->name);
0877 
0878         retval = IRQ_HANDLED;
0879     } else
0880         retval = IRQ_NONE;
0881 
0882     return retval;
0883 }
0884 
0885 
0886 static void korina_check_media(struct net_device *dev, unsigned int init_media)
0887 {
0888     struct korina_private *lp = netdev_priv(dev);
0889 
0890     mii_check_media(&lp->mii_if, 1, init_media);
0891 
0892     if (lp->mii_if.full_duplex)
0893         writel(readl(&lp->eth_regs->ethmac2) | ETH_MAC2_FD,
0894                         &lp->eth_regs->ethmac2);
0895     else
0896         writel(readl(&lp->eth_regs->ethmac2) & ~ETH_MAC2_FD,
0897                         &lp->eth_regs->ethmac2);
0898 }
0899 
0900 static void korina_poll_media(struct timer_list *t)
0901 {
0902     struct korina_private *lp = from_timer(lp, t, media_check_timer);
0903     struct net_device *dev = lp->dev;
0904 
0905     korina_check_media(dev, 0);
0906     mod_timer(&lp->media_check_timer, jiffies + HZ);
0907 }
0908 
0909 static void korina_set_carrier(struct mii_if_info *mii)
0910 {
0911     if (mii->force_media) {
0912         /* autoneg is off: Link is always assumed to be up */
0913         if (!netif_carrier_ok(mii->dev))
0914             netif_carrier_on(mii->dev);
0915     } else  /* Let MMI library update carrier status */
0916         korina_check_media(mii->dev, 0);
0917 }
0918 
0919 static int korina_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
0920 {
0921     struct korina_private *lp = netdev_priv(dev);
0922     struct mii_ioctl_data *data = if_mii(rq);
0923     int rc;
0924 
0925     if (!netif_running(dev))
0926         return -EINVAL;
0927     spin_lock_irq(&lp->lock);
0928     rc = generic_mii_ioctl(&lp->mii_if, data, cmd, NULL);
0929     spin_unlock_irq(&lp->lock);
0930     korina_set_carrier(&lp->mii_if);
0931 
0932     return rc;
0933 }
0934 
0935 /* ethtool helpers */
0936 static void netdev_get_drvinfo(struct net_device *dev,
0937                 struct ethtool_drvinfo *info)
0938 {
0939     struct korina_private *lp = netdev_priv(dev);
0940 
0941     strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
0942     strlcpy(info->version, DRV_VERSION, sizeof(info->version));
0943     strlcpy(info->bus_info, lp->dev->name, sizeof(info->bus_info));
0944 }
0945 
0946 static int netdev_get_link_ksettings(struct net_device *dev,
0947                      struct ethtool_link_ksettings *cmd)
0948 {
0949     struct korina_private *lp = netdev_priv(dev);
0950 
0951     spin_lock_irq(&lp->lock);
0952     mii_ethtool_get_link_ksettings(&lp->mii_if, cmd);
0953     spin_unlock_irq(&lp->lock);
0954 
0955     return 0;
0956 }
0957 
0958 static int netdev_set_link_ksettings(struct net_device *dev,
0959                      const struct ethtool_link_ksettings *cmd)
0960 {
0961     struct korina_private *lp = netdev_priv(dev);
0962     int rc;
0963 
0964     spin_lock_irq(&lp->lock);
0965     rc = mii_ethtool_set_link_ksettings(&lp->mii_if, cmd);
0966     spin_unlock_irq(&lp->lock);
0967     korina_set_carrier(&lp->mii_if);
0968 
0969     return rc;
0970 }
0971 
0972 static u32 netdev_get_link(struct net_device *dev)
0973 {
0974     struct korina_private *lp = netdev_priv(dev);
0975 
0976     return mii_link_ok(&lp->mii_if);
0977 }
0978 
0979 static const struct ethtool_ops netdev_ethtool_ops = {
0980     .get_drvinfo        = netdev_get_drvinfo,
0981     .get_link       = netdev_get_link,
0982     .get_link_ksettings = netdev_get_link_ksettings,
0983     .set_link_ksettings = netdev_set_link_ksettings,
0984 };
0985 
0986 static int korina_alloc_ring(struct net_device *dev)
0987 {
0988     struct korina_private *lp = netdev_priv(dev);
0989     struct sk_buff *skb;
0990     dma_addr_t ca;
0991     int i;
0992 
0993     /* Initialize the transmit descriptors */
0994     for (i = 0; i < KORINA_NUM_TDS; i++) {
0995         lp->td_ring[i].control = DMA_DESC_IOF;
0996         lp->td_ring[i].devcs = ETH_TX_FD | ETH_TX_LD;
0997         lp->td_ring[i].ca = 0;
0998         lp->td_ring[i].link = 0;
0999     }
1000     lp->tx_next_done = lp->tx_chain_head = lp->tx_chain_tail =
1001             lp->tx_full = lp->tx_count = 0;
1002     lp->tx_chain_status = desc_is_empty;
1003 
1004     /* Initialize the receive descriptors */
1005     for (i = 0; i < KORINA_NUM_RDS; i++) {
1006         skb = netdev_alloc_skb_ip_align(dev, KORINA_RBSIZE);
1007         if (!skb)
1008             return -ENOMEM;
1009         lp->rx_skb[i] = skb;
1010         lp->rd_ring[i].control = DMA_DESC_IOD |
1011                 DMA_COUNT(KORINA_RBSIZE);
1012         lp->rd_ring[i].devcs = 0;
1013         ca = dma_map_single(lp->dmadev, skb->data, KORINA_RBSIZE,
1014                     DMA_FROM_DEVICE);
1015         if (dma_mapping_error(lp->dmadev, ca))
1016             return -ENOMEM;
1017         lp->rd_ring[i].ca = ca;
1018         lp->rx_skb_dma[i] = ca;
1019         lp->rd_ring[i].link = korina_rx_dma(lp, i + 1);
1020     }
1021 
1022     /* loop back receive descriptors, so the last
1023      * descriptor points to the first one */
1024     lp->rd_ring[i - 1].link = lp->rd_dma;
1025     lp->rd_ring[i - 1].control |= DMA_DESC_COD;
1026 
1027     lp->rx_next_done  = 0;
1028     lp->rx_chain_head = 0;
1029     lp->rx_chain_tail = 0;
1030     lp->rx_chain_status = desc_is_empty;
1031 
1032     return 0;
1033 }
1034 
1035 static void korina_free_ring(struct net_device *dev)
1036 {
1037     struct korina_private *lp = netdev_priv(dev);
1038     int i;
1039 
1040     for (i = 0; i < KORINA_NUM_RDS; i++) {
1041         lp->rd_ring[i].control = 0;
1042         if (lp->rx_skb[i]) {
1043             dma_unmap_single(lp->dmadev, lp->rx_skb_dma[i],
1044                      KORINA_RBSIZE, DMA_FROM_DEVICE);
1045             dev_kfree_skb_any(lp->rx_skb[i]);
1046             lp->rx_skb[i] = NULL;
1047         }
1048     }
1049 
1050     for (i = 0; i < KORINA_NUM_TDS; i++) {
1051         lp->td_ring[i].control = 0;
1052         if (lp->tx_skb[i]) {
1053             dma_unmap_single(lp->dmadev, lp->tx_skb_dma[i],
1054                      lp->tx_skb[i]->len, DMA_TO_DEVICE);
1055             dev_kfree_skb_any(lp->tx_skb[i]);
1056             lp->tx_skb[i] = NULL;
1057         }
1058     }
1059 }
1060 
1061 /*
1062  * Initialize the RC32434 ethernet controller.
1063  */
1064 static int korina_init(struct net_device *dev)
1065 {
1066     struct korina_private *lp = netdev_priv(dev);
1067 
1068     /* Disable DMA */
1069     korina_abort_tx(dev);
1070     korina_abort_rx(dev);
1071 
1072     /* reset ethernet logic */
1073     writel(0, &lp->eth_regs->ethintfc);
1074     while ((readl(&lp->eth_regs->ethintfc) & ETH_INT_FC_RIP))
1075         netif_trans_update(dev);
1076 
1077     /* Enable Ethernet Interface */
1078     writel(ETH_INT_FC_EN, &lp->eth_regs->ethintfc);
1079 
1080     /* Allocate rings */
1081     if (korina_alloc_ring(dev)) {
1082         printk(KERN_ERR "%s: descriptor allocation failed\n", dev->name);
1083         korina_free_ring(dev);
1084         return -ENOMEM;
1085     }
1086 
1087     writel(0, &lp->rx_dma_regs->dmas);
1088     /* Start Rx DMA */
1089     writel(0, &lp->rx_dma_regs->dmandptr);
1090     writel(korina_rx_dma(lp, 0), &lp->rx_dma_regs->dmadptr);
1091 
1092     writel(readl(&lp->tx_dma_regs->dmasm) &
1093             ~(DMA_STAT_FINI | DMA_STAT_ERR),
1094             &lp->tx_dma_regs->dmasm);
1095     writel(readl(&lp->rx_dma_regs->dmasm) &
1096             ~(DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR),
1097             &lp->rx_dma_regs->dmasm);
1098 
1099     /* Accept only packets destined for this Ethernet device address */
1100     writel(ETH_ARC_AB, &lp->eth_regs->etharc);
1101 
1102     /* Set all Ether station address registers to their initial values */
1103     writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal0);
1104     writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah0);
1105 
1106     writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal1);
1107     writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah1);
1108 
1109     writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal2);
1110     writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah2);
1111 
1112     writel(STATION_ADDRESS_LOW(dev), &lp->eth_regs->ethsal3);
1113     writel(STATION_ADDRESS_HIGH(dev), &lp->eth_regs->ethsah3);
1114 
1115 
1116     /* Frame Length Checking, Pad Enable, CRC Enable, Full Duplex set */
1117     writel(ETH_MAC2_PE | ETH_MAC2_CEN | ETH_MAC2_FD,
1118             &lp->eth_regs->ethmac2);
1119 
1120     /* Back to back inter-packet-gap */
1121     writel(0x15, &lp->eth_regs->ethipgt);
1122     /* Non - Back to back inter-packet-gap */
1123     writel(0x12, &lp->eth_regs->ethipgr);
1124 
1125     /* Management Clock Prescaler Divisor
1126      * Clock independent setting */
1127     writel(((lp->mii_clock_freq) / MII_CLOCK + 1) & ~1,
1128            &lp->eth_regs->ethmcp);
1129     writel(0, &lp->eth_regs->miimcfg);
1130 
1131     /* don't transmit until fifo contains 48b */
1132     writel(48, &lp->eth_regs->ethfifott);
1133 
1134     writel(ETH_MAC1_RE, &lp->eth_regs->ethmac1);
1135 
1136     korina_check_media(dev, 1);
1137 
1138     napi_enable(&lp->napi);
1139     netif_start_queue(dev);
1140 
1141     return 0;
1142 }
1143 
1144 /*
1145  * Restart the RC32434 ethernet controller.
1146  */
1147 static void korina_restart_task(struct work_struct *work)
1148 {
1149     struct korina_private *lp = container_of(work,
1150             struct korina_private, restart_task);
1151     struct net_device *dev = lp->dev;
1152 
1153     /*
1154      * Disable interrupts
1155      */
1156     disable_irq(lp->rx_irq);
1157     disable_irq(lp->tx_irq);
1158 
1159     writel(readl(&lp->tx_dma_regs->dmasm) |
1160                 DMA_STAT_FINI | DMA_STAT_ERR,
1161                 &lp->tx_dma_regs->dmasm);
1162     writel(readl(&lp->rx_dma_regs->dmasm) |
1163                 DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR,
1164                 &lp->rx_dma_regs->dmasm);
1165 
1166     napi_disable(&lp->napi);
1167 
1168     korina_free_ring(dev);
1169 
1170     if (korina_init(dev) < 0) {
1171         printk(KERN_ERR "%s: cannot restart device\n", dev->name);
1172         return;
1173     }
1174     korina_multicast_list(dev);
1175 
1176     enable_irq(lp->tx_irq);
1177     enable_irq(lp->rx_irq);
1178 }
1179 
1180 static void korina_tx_timeout(struct net_device *dev, unsigned int txqueue)
1181 {
1182     struct korina_private *lp = netdev_priv(dev);
1183 
1184     schedule_work(&lp->restart_task);
1185 }
1186 
1187 #ifdef CONFIG_NET_POLL_CONTROLLER
1188 static void korina_poll_controller(struct net_device *dev)
1189 {
1190     disable_irq(dev->irq);
1191     korina_tx_dma_interrupt(dev->irq, dev);
1192     enable_irq(dev->irq);
1193 }
1194 #endif
1195 
1196 static int korina_open(struct net_device *dev)
1197 {
1198     struct korina_private *lp = netdev_priv(dev);
1199     int ret;
1200 
1201     /* Initialize */
1202     ret = korina_init(dev);
1203     if (ret < 0) {
1204         printk(KERN_ERR "%s: cannot open device\n", dev->name);
1205         goto out;
1206     }
1207 
1208     /* Install the interrupt handler
1209      * that handles the Done Finished */
1210     ret = request_irq(lp->rx_irq, korina_rx_dma_interrupt,
1211             0, "Korina ethernet Rx", dev);
1212     if (ret < 0) {
1213         printk(KERN_ERR "%s: unable to get Rx DMA IRQ %d\n",
1214             dev->name, lp->rx_irq);
1215         goto err_release;
1216     }
1217     ret = request_irq(lp->tx_irq, korina_tx_dma_interrupt,
1218             0, "Korina ethernet Tx", dev);
1219     if (ret < 0) {
1220         printk(KERN_ERR "%s: unable to get Tx DMA IRQ %d\n",
1221             dev->name, lp->tx_irq);
1222         goto err_free_rx_irq;
1223     }
1224 
1225     mod_timer(&lp->media_check_timer, jiffies + 1);
1226 out:
1227     return ret;
1228 
1229 err_free_rx_irq:
1230     free_irq(lp->rx_irq, dev);
1231 err_release:
1232     korina_free_ring(dev);
1233     goto out;
1234 }
1235 
1236 static int korina_close(struct net_device *dev)
1237 {
1238     struct korina_private *lp = netdev_priv(dev);
1239     u32 tmp;
1240 
1241     del_timer(&lp->media_check_timer);
1242 
1243     /* Disable interrupts */
1244     disable_irq(lp->rx_irq);
1245     disable_irq(lp->tx_irq);
1246 
1247     korina_abort_tx(dev);
1248     tmp = readl(&lp->tx_dma_regs->dmasm);
1249     tmp = tmp | DMA_STAT_FINI | DMA_STAT_ERR;
1250     writel(tmp, &lp->tx_dma_regs->dmasm);
1251 
1252     korina_abort_rx(dev);
1253     tmp = readl(&lp->rx_dma_regs->dmasm);
1254     tmp = tmp | DMA_STAT_DONE | DMA_STAT_HALT | DMA_STAT_ERR;
1255     writel(tmp, &lp->rx_dma_regs->dmasm);
1256 
1257     napi_disable(&lp->napi);
1258 
1259     cancel_work_sync(&lp->restart_task);
1260 
1261     korina_free_ring(dev);
1262 
1263     free_irq(lp->rx_irq, dev);
1264     free_irq(lp->tx_irq, dev);
1265 
1266     return 0;
1267 }
1268 
1269 static const struct net_device_ops korina_netdev_ops = {
1270     .ndo_open       = korina_open,
1271     .ndo_stop       = korina_close,
1272     .ndo_start_xmit     = korina_send_packet,
1273     .ndo_set_rx_mode    = korina_multicast_list,
1274     .ndo_tx_timeout     = korina_tx_timeout,
1275     .ndo_eth_ioctl      = korina_ioctl,
1276     .ndo_validate_addr  = eth_validate_addr,
1277     .ndo_set_mac_address    = eth_mac_addr,
1278 #ifdef CONFIG_NET_POLL_CONTROLLER
1279     .ndo_poll_controller    = korina_poll_controller,
1280 #endif
1281 };
1282 
1283 static int korina_probe(struct platform_device *pdev)
1284 {
1285     u8 *mac_addr = dev_get_platdata(&pdev->dev);
1286     struct korina_private *lp;
1287     struct net_device *dev;
1288     struct clk *clk;
1289     void __iomem *p;
1290     int rc;
1291 
1292     dev = devm_alloc_etherdev(&pdev->dev, sizeof(struct korina_private));
1293     if (!dev)
1294         return -ENOMEM;
1295 
1296     SET_NETDEV_DEV(dev, &pdev->dev);
1297     lp = netdev_priv(dev);
1298 
1299     if (mac_addr)
1300         eth_hw_addr_set(dev, mac_addr);
1301     else if (of_get_ethdev_address(pdev->dev.of_node, dev) < 0)
1302         eth_hw_addr_random(dev);
1303 
1304     clk = devm_clk_get_optional(&pdev->dev, "mdioclk");
1305     if (IS_ERR(clk))
1306         return PTR_ERR(clk);
1307     if (clk) {
1308         clk_prepare_enable(clk);
1309         lp->mii_clock_freq = clk_get_rate(clk);
1310     } else {
1311         lp->mii_clock_freq = 200000000; /* max possible input clk */
1312     }
1313 
1314     lp->rx_irq = platform_get_irq_byname(pdev, "rx");
1315     lp->tx_irq = platform_get_irq_byname(pdev, "tx");
1316 
1317     p = devm_platform_ioremap_resource_byname(pdev, "emac");
1318     if (IS_ERR(p)) {
1319         printk(KERN_ERR DRV_NAME ": cannot remap registers\n");
1320         return PTR_ERR(p);
1321     }
1322     lp->eth_regs = p;
1323 
1324     p = devm_platform_ioremap_resource_byname(pdev, "dma_rx");
1325     if (IS_ERR(p)) {
1326         printk(KERN_ERR DRV_NAME ": cannot remap Rx DMA registers\n");
1327         return PTR_ERR(p);
1328     }
1329     lp->rx_dma_regs = p;
1330 
1331     p = devm_platform_ioremap_resource_byname(pdev, "dma_tx");
1332     if (IS_ERR(p)) {
1333         printk(KERN_ERR DRV_NAME ": cannot remap Tx DMA registers\n");
1334         return PTR_ERR(p);
1335     }
1336     lp->tx_dma_regs = p;
1337 
1338     lp->td_ring = dmam_alloc_coherent(&pdev->dev, TD_RING_SIZE,
1339                       &lp->td_dma, GFP_KERNEL);
1340     if (!lp->td_ring)
1341         return -ENOMEM;
1342 
1343     lp->rd_ring = dmam_alloc_coherent(&pdev->dev, RD_RING_SIZE,
1344                       &lp->rd_dma, GFP_KERNEL);
1345     if (!lp->rd_ring)
1346         return -ENOMEM;
1347 
1348     spin_lock_init(&lp->lock);
1349     /* just use the rx dma irq */
1350     dev->irq = lp->rx_irq;
1351     lp->dev = dev;
1352     lp->dmadev = &pdev->dev;
1353 
1354     dev->netdev_ops = &korina_netdev_ops;
1355     dev->ethtool_ops = &netdev_ethtool_ops;
1356     dev->watchdog_timeo = TX_TIMEOUT;
1357     netif_napi_add(dev, &lp->napi, korina_poll, NAPI_POLL_WEIGHT);
1358 
1359     lp->mii_if.dev = dev;
1360     lp->mii_if.mdio_read = korina_mdio_read;
1361     lp->mii_if.mdio_write = korina_mdio_write;
1362     lp->mii_if.phy_id = 1;
1363     lp->mii_if.phy_id_mask = 0x1f;
1364     lp->mii_if.reg_num_mask = 0x1f;
1365 
1366     platform_set_drvdata(pdev, dev);
1367 
1368     rc = register_netdev(dev);
1369     if (rc < 0) {
1370         printk(KERN_ERR DRV_NAME
1371             ": cannot register net device: %d\n", rc);
1372         return rc;
1373     }
1374     timer_setup(&lp->media_check_timer, korina_poll_media, 0);
1375 
1376     INIT_WORK(&lp->restart_task, korina_restart_task);
1377 
1378     printk(KERN_INFO "%s: " DRV_NAME "-" DRV_VERSION " " DRV_RELDATE "\n",
1379             dev->name);
1380     return rc;
1381 }
1382 
1383 static int korina_remove(struct platform_device *pdev)
1384 {
1385     struct net_device *dev = platform_get_drvdata(pdev);
1386 
1387     unregister_netdev(dev);
1388 
1389     return 0;
1390 }
1391 
1392 #ifdef CONFIG_OF
1393 static const struct of_device_id korina_match[] = {
1394     {
1395         .compatible = "idt,3243x-emac",
1396     },
1397     { }
1398 };
1399 MODULE_DEVICE_TABLE(of, korina_match);
1400 #endif
1401 
1402 static struct platform_driver korina_driver = {
1403     .driver = {
1404         .name = "korina",
1405         .of_match_table = of_match_ptr(korina_match),
1406     },
1407     .probe = korina_probe,
1408     .remove = korina_remove,
1409 };
1410 
1411 module_platform_driver(korina_driver);
1412 
1413 MODULE_AUTHOR("Philip Rischel <rischelp@idt.com>");
1414 MODULE_AUTHOR("Felix Fietkau <nbd@openwrt.org>");
1415 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
1416 MODULE_AUTHOR("Roman Yeryomin <roman@advem.lv>");
1417 MODULE_DESCRIPTION("IDT RC32434 (Korina) Ethernet driver");
1418 MODULE_LICENSE("GPL");
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