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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
0004  *
0005  * Copyright 2008 JMicron Technology Corporation
0006  * https://www.jmicron.com/
0007  * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
0008  *
0009  * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
0010  */
0011 
0012 #ifndef __JME_H_INCLUDED__
0013 #define __JME_H_INCLUDED__
0014 #include <linux/interrupt.h>
0015 
0016 #define DRV_NAME    "jme"
0017 #define DRV_VERSION "1.0.8"
0018 
0019 #define PCI_DEVICE_ID_JMICRON_JMC250    0x0250
0020 #define PCI_DEVICE_ID_JMICRON_JMC260    0x0260
0021 
0022 /*
0023  * Message related definitions
0024  */
0025 #define JME_DEF_MSG_ENABLE \
0026     (NETIF_MSG_PROBE | \
0027     NETIF_MSG_LINK | \
0028     NETIF_MSG_RX_ERR | \
0029     NETIF_MSG_TX_ERR | \
0030     NETIF_MSG_HW)
0031 
0032 #ifdef TX_DEBUG
0033 #define tx_dbg(priv, fmt, args...)                  \
0034     printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
0035 #else
0036 #define tx_dbg(priv, fmt, args...)                  \
0037 do {                                    \
0038     if (0)                              \
0039         printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
0040 } while (0)
0041 #endif
0042 
0043 /*
0044  * Extra PCI Configuration space interface
0045  */
0046 #define PCI_DCSR_MRRS       0x59
0047 #define PCI_DCSR_MRRS_MASK  0x70
0048 
0049 enum pci_dcsr_mrrs_vals {
0050     MRRS_128B   = 0x00,
0051     MRRS_256B   = 0x10,
0052     MRRS_512B   = 0x20,
0053     MRRS_1024B  = 0x30,
0054     MRRS_2048B  = 0x40,
0055     MRRS_4096B  = 0x50,
0056 };
0057 
0058 #define PCI_SPI         0xB0
0059 
0060 enum pci_spi_bits {
0061     SPI_EN      = 0x10,
0062     SPI_MISO    = 0x08,
0063     SPI_MOSI    = 0x04,
0064     SPI_SCLK    = 0x02,
0065     SPI_CS      = 0x01,
0066 };
0067 
0068 struct jme_spi_op {
0069     void __user *uwbuf;
0070     void __user *urbuf;
0071     __u8    wn; /* Number of write actions */
0072     __u8    rn; /* Number of read actions */
0073     __u8    bitn;   /* Number of bits per action */
0074     __u8    spd;    /* The maxim acceptable speed of controller, in MHz.*/
0075     __u8    mode;   /* CPOL, CPHA, and Duplex mode of SPI */
0076 
0077     /* Internal use only */
0078     u8  *kwbuf;
0079     u8  *krbuf;
0080     u8  sr;
0081     u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
0082 };
0083 
0084 enum jme_spi_op_bits {
0085     SPI_MODE_CPHA   = 0x01,
0086     SPI_MODE_CPOL   = 0x02,
0087     SPI_MODE_DUP    = 0x80,
0088 };
0089 
0090 #define HALF_US 500 /* 500 ns */
0091 
0092 #define PCI_PRIV_PE1        0xE4
0093 
0094 enum pci_priv_pe1_bit_masks {
0095     PE1_ASPMSUPRT   = 0x00000003, /*
0096                        * RW:
0097                        * Aspm_support[1:0]
0098                        * (R/W Port of 5C[11:10])
0099                        */
0100     PE1_MULTIFUN    = 0x00000004, /* RW: Multi_fun_bit */
0101     PE1_RDYDMA  = 0x00000008, /* RO: ~link.rdy_for_dma */
0102     PE1_ASPMOPTL    = 0x00000030, /* RW: link.rx10s_option[1:0] */
0103     PE1_ASPMOPTH    = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
0104     PE1_GPREG0  = 0x0000FF00, /*
0105                        * SRW:
0106                        * Cfg_gp_reg0
0107                        * [7:6] phy_giga BG control
0108                        * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
0109                        * [4:0] Reserved
0110                        */
0111     PE1_GPREG0_PBG  = 0x0000C000, /* phy_giga BG control */
0112     PE1_GPREG1  = 0x00FF0000, /* RW: Cfg_gp_reg1 */
0113     PE1_REVID   = 0xFF000000, /* RO: Rev ID */
0114 };
0115 
0116 enum pci_priv_pe1_values {
0117     PE1_GPREG0_ENBG     = 0x00000000, /* en BG */
0118     PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
0119     PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
0120     PE1_GPREG0_PDPCIEIDDQ   = 0x0000C000, /* giga_PD + pcie_iddq */
0121 };
0122 
0123 /*
0124  * Dynamic(adaptive)/Static PCC values
0125  */
0126 enum dynamic_pcc_values {
0127     PCC_OFF     = 0,
0128     PCC_P1      = 1,
0129     PCC_P2      = 2,
0130     PCC_P3      = 3,
0131 
0132     PCC_OFF_TO  = 0,
0133     PCC_P1_TO   = 1,
0134     PCC_P2_TO   = 64,
0135     PCC_P3_TO   = 128,
0136 
0137     PCC_OFF_CNT = 0,
0138     PCC_P1_CNT  = 1,
0139     PCC_P2_CNT  = 16,
0140     PCC_P3_CNT  = 32,
0141 };
0142 struct dynpcc_info {
0143     unsigned long   last_bytes;
0144     unsigned long   last_pkts;
0145     unsigned long   intr_cnt;
0146     unsigned char   cur;
0147     unsigned char   attempt;
0148     unsigned char   cnt;
0149 };
0150 #define PCC_INTERVAL_US 100000
0151 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
0152 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
0153 #define PCC_P2_THRESHOLD 800
0154 #define PCC_INTR_THRESHOLD 800
0155 #define PCC_TX_TO 1000
0156 #define PCC_TX_CNT 8
0157 
0158 /*
0159  * TX/RX Descriptors
0160  *
0161  * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
0162  */
0163 #define RING_DESC_ALIGN     16  /* Descriptor alignment */
0164 #define TX_DESC_SIZE        16
0165 #define TX_RING_NR      8
0166 #define TX_RING_ALLOC_SIZE(s)   ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
0167 
0168 struct txdesc {
0169     union {
0170         __u8    all[16];
0171         __le32  dw[4];
0172         struct {
0173             /* DW0 */
0174             __le16  vlan;
0175             __u8    rsv1;
0176             __u8    flags;
0177 
0178             /* DW1 */
0179             __le16  datalen;
0180             __le16  mss;
0181 
0182             /* DW2 */
0183             __le16  pktsize;
0184             __le16  rsv2;
0185 
0186             /* DW3 */
0187             __le32  bufaddr;
0188         } desc1;
0189         struct {
0190             /* DW0 */
0191             __le16  rsv1;
0192             __u8    rsv2;
0193             __u8    flags;
0194 
0195             /* DW1 */
0196             __le16  datalen;
0197             __le16  rsv3;
0198 
0199             /* DW2 */
0200             __le32  bufaddrh;
0201 
0202             /* DW3 */
0203             __le32  bufaddrl;
0204         } desc2;
0205         struct {
0206             /* DW0 */
0207             __u8    ehdrsz;
0208             __u8    rsv1;
0209             __u8    rsv2;
0210             __u8    flags;
0211 
0212             /* DW1 */
0213             __le16  trycnt;
0214             __le16  segcnt;
0215 
0216             /* DW2 */
0217             __le16  pktsz;
0218             __le16  rsv3;
0219 
0220             /* DW3 */
0221             __le32  bufaddrl;
0222         } descwb;
0223     };
0224 };
0225 
0226 enum jme_txdesc_flags_bits {
0227     TXFLAG_OWN  = 0x80,
0228     TXFLAG_INT  = 0x40,
0229     TXFLAG_64BIT    = 0x20,
0230     TXFLAG_TCPCS    = 0x10,
0231     TXFLAG_UDPCS    = 0x08,
0232     TXFLAG_IPCS = 0x04,
0233     TXFLAG_LSEN = 0x02,
0234     TXFLAG_TAGON    = 0x01,
0235 };
0236 
0237 #define TXDESC_MSS_SHIFT    2
0238 enum jme_txwbdesc_flags_bits {
0239     TXWBFLAG_OWN    = 0x80,
0240     TXWBFLAG_INT    = 0x40,
0241     TXWBFLAG_TMOUT  = 0x20,
0242     TXWBFLAG_TRYOUT = 0x10,
0243     TXWBFLAG_COL    = 0x08,
0244 
0245     TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
0246               TXWBFLAG_TRYOUT |
0247               TXWBFLAG_COL,
0248 };
0249 
0250 #define RX_DESC_SIZE        16
0251 #define RX_RING_NR      4
0252 #define RX_RING_ALLOC_SIZE(s)   ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
0253 #define RX_BUF_DMA_ALIGN    8
0254 #define RX_PREPAD_SIZE      10
0255 #define ETH_CRC_LEN     2
0256 #define RX_VLANHDR_LEN      2
0257 #define RX_EXTRA_LEN        (RX_PREPAD_SIZE + \
0258                 ETH_HLEN + \
0259                 ETH_CRC_LEN + \
0260                 RX_VLANHDR_LEN + \
0261                 RX_BUF_DMA_ALIGN)
0262 
0263 struct rxdesc {
0264     union {
0265         __u8    all[16];
0266         __le32  dw[4];
0267         struct {
0268             /* DW0 */
0269             __le16  rsv2;
0270             __u8    rsv1;
0271             __u8    flags;
0272 
0273             /* DW1 */
0274             __le16  datalen;
0275             __le16  wbcpl;
0276 
0277             /* DW2 */
0278             __le32  bufaddrh;
0279 
0280             /* DW3 */
0281             __le32  bufaddrl;
0282         } desc1;
0283         struct {
0284             /* DW0 */
0285             __le16  vlan;
0286             __le16  flags;
0287 
0288             /* DW1 */
0289             __le16  framesize;
0290             __u8    errstat;
0291             __u8    desccnt;
0292 
0293             /* DW2 */
0294             __le32  rsshash;
0295 
0296             /* DW3 */
0297             __u8    hashfun;
0298             __u8    hashtype;
0299             __le16  resrv;
0300         } descwb;
0301     };
0302 };
0303 
0304 enum jme_rxdesc_flags_bits {
0305     RXFLAG_OWN  = 0x80,
0306     RXFLAG_INT  = 0x40,
0307     RXFLAG_64BIT    = 0x20,
0308 };
0309 
0310 enum jme_rxwbdesc_flags_bits {
0311     RXWBFLAG_OWN        = 0x8000,
0312     RXWBFLAG_INT        = 0x4000,
0313     RXWBFLAG_MF     = 0x2000,
0314     RXWBFLAG_64BIT      = 0x2000,
0315     RXWBFLAG_TCPON      = 0x1000,
0316     RXWBFLAG_UDPON      = 0x0800,
0317     RXWBFLAG_IPCS       = 0x0400,
0318     RXWBFLAG_TCPCS      = 0x0200,
0319     RXWBFLAG_UDPCS      = 0x0100,
0320     RXWBFLAG_TAGON      = 0x0080,
0321     RXWBFLAG_IPV4       = 0x0040,
0322     RXWBFLAG_IPV6       = 0x0020,
0323     RXWBFLAG_PAUSE      = 0x0010,
0324     RXWBFLAG_MAGIC      = 0x0008,
0325     RXWBFLAG_WAKEUP     = 0x0004,
0326     RXWBFLAG_DEST       = 0x0003,
0327     RXWBFLAG_DEST_UNI   = 0x0001,
0328     RXWBFLAG_DEST_MUL   = 0x0002,
0329     RXWBFLAG_DEST_BRO   = 0x0003,
0330 };
0331 
0332 enum jme_rxwbdesc_desccnt_mask {
0333     RXWBDCNT_WBCPL  = 0x80,
0334     RXWBDCNT_DCNT   = 0x7F,
0335 };
0336 
0337 enum jme_rxwbdesc_errstat_bits {
0338     RXWBERR_LIMIT   = 0x80,
0339     RXWBERR_MIIER   = 0x40,
0340     RXWBERR_NIBON   = 0x20,
0341     RXWBERR_COLON   = 0x10,
0342     RXWBERR_ABORT   = 0x08,
0343     RXWBERR_SHORT   = 0x04,
0344     RXWBERR_OVERUN  = 0x02,
0345     RXWBERR_CRCERR  = 0x01,
0346     RXWBERR_ALLERR  = 0xFF,
0347 };
0348 
0349 /*
0350  * Buffer information corresponding to ring descriptors.
0351  */
0352 struct jme_buffer_info {
0353     struct sk_buff *skb;
0354     dma_addr_t mapping;
0355     int len;
0356     int nr_desc;
0357     unsigned long start_xmit;
0358 };
0359 
0360 /*
0361  * The structure holding buffer information and ring descriptors all together.
0362  */
0363 struct jme_ring {
0364     void *alloc;        /* pointer to allocated memory */
0365     void *desc;     /* pointer to ring memory  */
0366     dma_addr_t dmaalloc;    /* phys address of ring alloc */
0367     dma_addr_t dma;     /* phys address for ring dma */
0368 
0369     /* Buffer information corresponding to each descriptor */
0370     struct jme_buffer_info *bufinf;
0371 
0372     int next_to_use;
0373     atomic_t next_to_clean;
0374     atomic_t nr_free;
0375 };
0376 
0377 #define NET_STAT(priv) (priv->dev->stats)
0378 #define NETDEV_GET_STATS(netdev, fun_ptr)
0379 #define DECLARE_NET_DEVICE_STATS
0380 
0381 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
0382 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
0383 #define JME_NAPI_WEIGHT(w) int w
0384 #define JME_NAPI_WEIGHT_VAL(w) w
0385 #define JME_NAPI_WEIGHT_SET(w, r)
0386 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
0387 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
0388 #define JME_NAPI_DISABLE(priv) \
0389     if (!napi_disable_pending(&priv->napi)) \
0390         napi_disable(&priv->napi);
0391 #define JME_RX_SCHEDULE_PREP(priv) \
0392     napi_schedule_prep(&priv->napi)
0393 #define JME_RX_SCHEDULE(priv) \
0394     __napi_schedule(&priv->napi);
0395 
0396 /*
0397  * Jmac Adapter Private data
0398  */
0399 struct jme_adapter {
0400     struct pci_dev          *pdev;
0401     struct net_device       *dev;
0402     void __iomem            *regs;
0403     struct mii_if_info  mii_if;
0404     struct jme_ring     rxring[RX_RING_NR];
0405     struct jme_ring     txring[TX_RING_NR];
0406     spinlock_t      phy_lock;
0407     spinlock_t      macaddr_lock;
0408     spinlock_t      rxmcs_lock;
0409     struct tasklet_struct   rxempty_task;
0410     struct tasklet_struct   rxclean_task;
0411     struct tasklet_struct   txclean_task;
0412     struct work_struct  linkch_task;
0413     struct tasklet_struct   pcc_task;
0414     unsigned long       flags;
0415     u32         reg_txcs;
0416     u32         reg_txpfc;
0417     u32         reg_rxcs;
0418     u32         reg_rxmcs;
0419     u32         reg_ghc;
0420     u32         reg_pmcs;
0421     u32         reg_gpreg1;
0422     u32         phylink;
0423     u32         tx_ring_size;
0424     u32         tx_ring_mask;
0425     u32         tx_wake_threshold;
0426     u32         rx_ring_size;
0427     u32         rx_ring_mask;
0428     u8          mrrs;
0429     unsigned int        fpgaver;
0430     u8          chiprev;
0431     u8          chip_main_rev;
0432     u8          chip_sub_rev;
0433     u8          pcirev;
0434     u32         msg_enable;
0435     struct ethtool_link_ksettings old_cmd;
0436     unsigned int        old_mtu;
0437     struct dynpcc_info  dpi;
0438     atomic_t        intr_sem;
0439     atomic_t        link_changing;
0440     atomic_t        tx_cleaning;
0441     atomic_t        rx_cleaning;
0442     atomic_t        rx_empty;
0443     int         (*jme_rx)(struct sk_buff *skb);
0444     DECLARE_NAPI_STRUCT
0445     DECLARE_NET_DEVICE_STATS
0446 };
0447 
0448 enum jme_flags_bits {
0449     JME_FLAG_MSI        = 1,
0450     JME_FLAG_SSET       = 2,
0451     JME_FLAG_POLL       = 5,
0452     JME_FLAG_SHUTDOWN   = 6,
0453 };
0454 
0455 #define TX_TIMEOUT      (5 * HZ)
0456 #define JME_REG_LEN     0x500
0457 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
0458 
0459 static inline struct jme_adapter*
0460 jme_napi_priv(struct napi_struct *napi)
0461 {
0462     struct jme_adapter *jme;
0463     jme = container_of(napi, struct jme_adapter, napi);
0464     return jme;
0465 }
0466 
0467 /*
0468  * MMaped I/O Resters
0469  */
0470 enum jme_iomap_offsets {
0471     JME_MAC     = 0x0000,
0472     JME_PHY     = 0x0400,
0473     JME_MISC    = 0x0800,
0474     JME_RSS     = 0x0C00,
0475 };
0476 
0477 enum jme_iomap_lens {
0478     JME_MAC_LEN = 0x80,
0479     JME_PHY_LEN = 0x58,
0480     JME_MISC_LEN    = 0x98,
0481     JME_RSS_LEN = 0xFF,
0482 };
0483 
0484 enum jme_iomap_regs {
0485     JME_TXCS    = JME_MAC | 0x00, /* Transmit Control and Status */
0486     JME_TXDBA_LO    = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
0487     JME_TXDBA_HI    = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
0488     JME_TXQDC   = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
0489     JME_TXNDA   = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
0490     JME_TXMCS   = JME_MAC | 0x14, /* Transmit MAC Control Status */
0491     JME_TXPFC   = JME_MAC | 0x18, /* Transmit Pause Frame Control */
0492     JME_TXTRHD  = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
0493 
0494     JME_RXCS    = JME_MAC | 0x20, /* Receive Control and Status */
0495     JME_RXDBA_LO    = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
0496     JME_RXDBA_HI    = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
0497     JME_RXQDC   = JME_MAC | 0x2C, /* Receive Queue Desc Count */
0498     JME_RXNDA   = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
0499     JME_RXMCS   = JME_MAC | 0x34, /* Receive MAC Control Status */
0500     JME_RXUMA_LO    = JME_MAC | 0x38, /* Receive Unicast MAC Address */
0501     JME_RXUMA_HI    = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
0502     JME_RXMCHT_LO   = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
0503     JME_RXMCHT_HI   = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
0504     JME_WFODP   = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
0505     JME_WFOI    = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
0506 
0507     JME_SMI     = JME_MAC | 0x50, /* Station Management Interface */
0508     JME_GHC     = JME_MAC | 0x54, /* Global Host Control */
0509     JME_PMCS    = JME_MAC | 0x60, /* Power Management Control/Stat */
0510 
0511 
0512     JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
0513     JME_PHY_CS  = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
0514     JME_PHY_LINK    = JME_PHY | 0x30, /* PHY Link Status Register */
0515     JME_SMBCSR  = JME_PHY | 0x40, /* SMB Control and Status */
0516     JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
0517 
0518 
0519     JME_TMCSR   = JME_MISC | 0x00, /* Timer Control/Status Register */
0520     JME_GPREG0  = JME_MISC | 0x08, /* General purpose REG-0 */
0521     JME_GPREG1  = JME_MISC | 0x0C, /* General purpose REG-1 */
0522     JME_IEVE    = JME_MISC | 0x20, /* Interrupt Event Status */
0523     JME_IREQ    = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
0524     JME_IENS    = JME_MISC | 0x28, /* Intr Enable - Setting Port */
0525     JME_IENC    = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
0526     JME_PCCRX0  = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
0527     JME_PCCTX   = JME_MISC | 0x40, /* PCC Control for TX Queues */
0528     JME_CHIPMODE    = JME_MISC | 0x44, /* Identify FPGA Version */
0529     JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
0530     JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
0531     JME_TIMER1  = JME_MISC | 0x70, /* Timer1 */
0532     JME_TIMER2  = JME_MISC | 0x74, /* Timer2 */
0533     JME_APMC    = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
0534     JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
0535 };
0536 
0537 /*
0538  * TX Control/Status Bits
0539  */
0540 enum jme_txcs_bits {
0541     TXCS_QUEUE7S    = 0x00008000,
0542     TXCS_QUEUE6S    = 0x00004000,
0543     TXCS_QUEUE5S    = 0x00002000,
0544     TXCS_QUEUE4S    = 0x00001000,
0545     TXCS_QUEUE3S    = 0x00000800,
0546     TXCS_QUEUE2S    = 0x00000400,
0547     TXCS_QUEUE1S    = 0x00000200,
0548     TXCS_QUEUE0S    = 0x00000100,
0549     TXCS_FIFOTH = 0x000000C0,
0550     TXCS_DMASIZE    = 0x00000030,
0551     TXCS_BURST  = 0x00000004,
0552     TXCS_ENABLE = 0x00000001,
0553 };
0554 
0555 enum jme_txcs_value {
0556     TXCS_FIFOTH_16QW    = 0x000000C0,
0557     TXCS_FIFOTH_12QW    = 0x00000080,
0558     TXCS_FIFOTH_8QW     = 0x00000040,
0559     TXCS_FIFOTH_4QW     = 0x00000000,
0560 
0561     TXCS_DMASIZE_64B    = 0x00000000,
0562     TXCS_DMASIZE_128B   = 0x00000010,
0563     TXCS_DMASIZE_256B   = 0x00000020,
0564     TXCS_DMASIZE_512B   = 0x00000030,
0565 
0566     TXCS_SELECT_QUEUE0  = 0x00000000,
0567     TXCS_SELECT_QUEUE1  = 0x00010000,
0568     TXCS_SELECT_QUEUE2  = 0x00020000,
0569     TXCS_SELECT_QUEUE3  = 0x00030000,
0570     TXCS_SELECT_QUEUE4  = 0x00040000,
0571     TXCS_SELECT_QUEUE5  = 0x00050000,
0572     TXCS_SELECT_QUEUE6  = 0x00060000,
0573     TXCS_SELECT_QUEUE7  = 0x00070000,
0574 
0575     TXCS_DEFAULT        = TXCS_FIFOTH_4QW |
0576                   TXCS_BURST,
0577 };
0578 
0579 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
0580 
0581 /*
0582  * TX MAC Control/Status Bits
0583  */
0584 enum jme_txmcs_bit_masks {
0585     TXMCS_IFG2      = 0xC0000000,
0586     TXMCS_IFG1      = 0x30000000,
0587     TXMCS_TTHOLD        = 0x00000300,
0588     TXMCS_FBURST        = 0x00000080,
0589     TXMCS_CARRIEREXT    = 0x00000040,
0590     TXMCS_DEFER     = 0x00000020,
0591     TXMCS_BACKOFF       = 0x00000010,
0592     TXMCS_CARRIERSENSE  = 0x00000008,
0593     TXMCS_COLLISION     = 0x00000004,
0594     TXMCS_CRC       = 0x00000002,
0595     TXMCS_PADDING       = 0x00000001,
0596 };
0597 
0598 enum jme_txmcs_values {
0599     TXMCS_IFG2_6_4      = 0x00000000,
0600     TXMCS_IFG2_8_5      = 0x40000000,
0601     TXMCS_IFG2_10_6     = 0x80000000,
0602     TXMCS_IFG2_12_7     = 0xC0000000,
0603 
0604     TXMCS_IFG1_8_4      = 0x00000000,
0605     TXMCS_IFG1_12_6     = 0x10000000,
0606     TXMCS_IFG1_16_8     = 0x20000000,
0607     TXMCS_IFG1_20_10    = 0x30000000,
0608 
0609     TXMCS_TTHOLD_1_8    = 0x00000000,
0610     TXMCS_TTHOLD_1_4    = 0x00000100,
0611     TXMCS_TTHOLD_1_2    = 0x00000200,
0612     TXMCS_TTHOLD_FULL   = 0x00000300,
0613 
0614     TXMCS_DEFAULT       = TXMCS_IFG2_8_5 |
0615                   TXMCS_IFG1_16_8 |
0616                   TXMCS_TTHOLD_FULL |
0617                   TXMCS_DEFER |
0618                   TXMCS_CRC |
0619                   TXMCS_PADDING,
0620 };
0621 
0622 enum jme_txpfc_bits_masks {
0623     TXPFC_VLAN_TAG      = 0xFFFF0000,
0624     TXPFC_VLAN_EN       = 0x00008000,
0625     TXPFC_PF_EN     = 0x00000001,
0626 };
0627 
0628 enum jme_txtrhd_bits_masks {
0629     TXTRHD_TXPEN        = 0x80000000,
0630     TXTRHD_TXP      = 0x7FFFFF00,
0631     TXTRHD_TXREN        = 0x00000080,
0632     TXTRHD_TXRL     = 0x0000007F,
0633 };
0634 
0635 enum jme_txtrhd_shifts {
0636     TXTRHD_TXP_SHIFT    = 8,
0637     TXTRHD_TXRL_SHIFT   = 0,
0638 };
0639 
0640 enum jme_txtrhd_values {
0641     TXTRHD_FULLDUPLEX   = 0x00000000,
0642     TXTRHD_HALFDUPLEX   = TXTRHD_TXPEN |
0643                   ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
0644                   TXTRHD_TXREN |
0645                   ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
0646 };
0647 
0648 /*
0649  * RX Control/Status Bits
0650  */
0651 enum jme_rxcs_bit_masks {
0652     /* FIFO full threshold for transmitting Tx Pause Packet */
0653     RXCS_FIFOTHTP   = 0x30000000,
0654     /* FIFO threshold for processing next packet */
0655     RXCS_FIFOTHNP   = 0x0C000000,
0656     RXCS_DMAREQSZ   = 0x03000000, /* DMA Request Size */
0657     RXCS_QUEUESEL   = 0x00030000, /* Queue selection */
0658     RXCS_RETRYGAP   = 0x0000F000, /* RX Desc full retry gap */
0659     RXCS_RETRYCNT   = 0x00000F00, /* RX Desc full retry counter */
0660     RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
0661     RXCS_MAGIC  = 0x00000020, /* Enable receive magic packet */
0662     RXCS_SHORT  = 0x00000010, /* Enable receive short packet */
0663     RXCS_ABORT  = 0x00000008, /* Enable receive errorr packet */
0664     RXCS_QST    = 0x00000004, /* Receive queue start */
0665     RXCS_SUSPEND    = 0x00000002,
0666     RXCS_ENABLE = 0x00000001,
0667 };
0668 
0669 enum jme_rxcs_values {
0670     RXCS_FIFOTHTP_16T   = 0x00000000,
0671     RXCS_FIFOTHTP_32T   = 0x10000000,
0672     RXCS_FIFOTHTP_64T   = 0x20000000,
0673     RXCS_FIFOTHTP_128T  = 0x30000000,
0674 
0675     RXCS_FIFOTHNP_16QW  = 0x00000000,
0676     RXCS_FIFOTHNP_32QW  = 0x04000000,
0677     RXCS_FIFOTHNP_64QW  = 0x08000000,
0678     RXCS_FIFOTHNP_128QW = 0x0C000000,
0679 
0680     RXCS_DMAREQSZ_16B   = 0x00000000,
0681     RXCS_DMAREQSZ_32B   = 0x01000000,
0682     RXCS_DMAREQSZ_64B   = 0x02000000,
0683     RXCS_DMAREQSZ_128B  = 0x03000000,
0684 
0685     RXCS_QUEUESEL_Q0    = 0x00000000,
0686     RXCS_QUEUESEL_Q1    = 0x00010000,
0687     RXCS_QUEUESEL_Q2    = 0x00020000,
0688     RXCS_QUEUESEL_Q3    = 0x00030000,
0689 
0690     RXCS_RETRYGAP_256ns = 0x00000000,
0691     RXCS_RETRYGAP_512ns = 0x00001000,
0692     RXCS_RETRYGAP_1024ns    = 0x00002000,
0693     RXCS_RETRYGAP_2048ns    = 0x00003000,
0694     RXCS_RETRYGAP_4096ns    = 0x00004000,
0695     RXCS_RETRYGAP_8192ns    = 0x00005000,
0696     RXCS_RETRYGAP_16384ns   = 0x00006000,
0697     RXCS_RETRYGAP_32768ns   = 0x00007000,
0698 
0699     RXCS_RETRYCNT_0     = 0x00000000,
0700     RXCS_RETRYCNT_4     = 0x00000100,
0701     RXCS_RETRYCNT_8     = 0x00000200,
0702     RXCS_RETRYCNT_12    = 0x00000300,
0703     RXCS_RETRYCNT_16    = 0x00000400,
0704     RXCS_RETRYCNT_20    = 0x00000500,
0705     RXCS_RETRYCNT_24    = 0x00000600,
0706     RXCS_RETRYCNT_28    = 0x00000700,
0707     RXCS_RETRYCNT_32    = 0x00000800,
0708     RXCS_RETRYCNT_36    = 0x00000900,
0709     RXCS_RETRYCNT_40    = 0x00000A00,
0710     RXCS_RETRYCNT_44    = 0x00000B00,
0711     RXCS_RETRYCNT_48    = 0x00000C00,
0712     RXCS_RETRYCNT_52    = 0x00000D00,
0713     RXCS_RETRYCNT_56    = 0x00000E00,
0714     RXCS_RETRYCNT_60    = 0x00000F00,
0715 
0716     RXCS_DEFAULT        = RXCS_FIFOTHTP_128T |
0717                   RXCS_FIFOTHNP_16QW |
0718                   RXCS_DMAREQSZ_128B |
0719                   RXCS_RETRYGAP_256ns |
0720                   RXCS_RETRYCNT_32,
0721 };
0722 
0723 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
0724 
0725 /*
0726  * RX MAC Control/Status Bits
0727  */
0728 enum jme_rxmcs_bits {
0729     RXMCS_ALLFRAME      = 0x00000800,
0730     RXMCS_BRDFRAME      = 0x00000400,
0731     RXMCS_MULFRAME      = 0x00000200,
0732     RXMCS_UNIFRAME      = 0x00000100,
0733     RXMCS_ALLMULFRAME   = 0x00000080,
0734     RXMCS_MULFILTERED   = 0x00000040,
0735     RXMCS_RXCOLLDEC     = 0x00000020,
0736     RXMCS_FLOWCTRL      = 0x00000008,
0737     RXMCS_VTAGRM        = 0x00000004,
0738     RXMCS_PREPAD        = 0x00000002,
0739     RXMCS_CHECKSUM      = 0x00000001,
0740 
0741     RXMCS_DEFAULT       = RXMCS_VTAGRM |
0742                   RXMCS_PREPAD |
0743                   RXMCS_FLOWCTRL |
0744                   RXMCS_CHECKSUM,
0745 };
0746 
0747 /*  Extern PHY common register 2    */
0748 
0749 #define PHY_GAD_TEST_MODE_1         0x00002000
0750 #define PHY_GAD_TEST_MODE_MSK           0x0000E000
0751 #define JM_PHY_SPEC_REG_READ            0x00004000
0752 #define JM_PHY_SPEC_REG_WRITE           0x00008000
0753 #define PHY_CALIBRATION_DELAY           20
0754 #define JM_PHY_SPEC_ADDR_REG            0x1E
0755 #define JM_PHY_SPEC_DATA_REG            0x1F
0756 
0757 #define JM_PHY_EXT_COMM_0_REG           0x30
0758 #define JM_PHY_EXT_COMM_1_REG           0x31
0759 #define JM_PHY_EXT_COMM_2_REG           0x32
0760 #define JM_PHY_EXT_COMM_2_CALI_ENABLE       0x01
0761 #define JM_PHY_EXT_COMM_2_CALI_MODE_0       0x02
0762 #define JM_PHY_EXT_COMM_2_CALI_LATCH        0x10
0763 #define PCI_PRIV_SHARE_NICCTRL          0xF5
0764 #define JME_FLAG_PHYEA_ENABLE           0x2
0765 
0766 /*
0767  * Wakeup Frame setup interface registers
0768  */
0769 #define WAKEUP_FRAME_NR 8
0770 #define WAKEUP_FRAME_MASK_DWNR  4
0771 
0772 enum jme_wfoi_bit_masks {
0773     WFOI_MASK_SEL       = 0x00000070,
0774     WFOI_CRC_SEL        = 0x00000008,
0775     WFOI_FRAME_SEL      = 0x00000007,
0776 };
0777 
0778 enum jme_wfoi_shifts {
0779     WFOI_MASK_SHIFT     = 4,
0780 };
0781 
0782 /*
0783  * SMI Related definitions
0784  */
0785 enum jme_smi_bit_mask {
0786     SMI_DATA_MASK       = 0xFFFF0000,
0787     SMI_REG_ADDR_MASK   = 0x0000F800,
0788     SMI_PHY_ADDR_MASK   = 0x000007C0,
0789     SMI_OP_WRITE        = 0x00000020,
0790     /* Set to 1, after req done it'll be cleared to 0 */
0791     SMI_OP_REQ      = 0x00000010,
0792     SMI_OP_MDIO     = 0x00000008, /* Software assess In/Out */
0793     SMI_OP_MDOE     = 0x00000004, /* Software Output Enable */
0794     SMI_OP_MDC      = 0x00000002, /* Software CLK Control */
0795     SMI_OP_MDEN     = 0x00000001, /* Software access Enable */
0796 };
0797 
0798 enum jme_smi_bit_shift {
0799     SMI_DATA_SHIFT      = 16,
0800     SMI_REG_ADDR_SHIFT  = 11,
0801     SMI_PHY_ADDR_SHIFT  = 6,
0802 };
0803 
0804 static inline u32 smi_reg_addr(int x)
0805 {
0806     return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
0807 }
0808 
0809 static inline u32 smi_phy_addr(int x)
0810 {
0811     return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
0812 }
0813 
0814 #define JME_PHY_TIMEOUT 100 /* 100 msec */
0815 #define JME_PHY_REG_NR 32
0816 
0817 /*
0818  * Global Host Control
0819  */
0820 enum jme_ghc_bit_mask {
0821     GHC_SWRST       = 0x40000000,
0822     GHC_TO_CLK_SRC      = 0x00C00000,
0823     GHC_TXMAC_CLK_SRC   = 0x00300000,
0824     GHC_DPX         = 0x00000040,
0825     GHC_SPEED       = 0x00000030,
0826     GHC_LINK_POLL       = 0x00000001,
0827 };
0828 
0829 enum jme_ghc_speed_val {
0830     GHC_SPEED_10M       = 0x00000010,
0831     GHC_SPEED_100M      = 0x00000020,
0832     GHC_SPEED_1000M     = 0x00000030,
0833 };
0834 
0835 enum jme_ghc_to_clk {
0836     GHC_TO_CLK_OFF      = 0x00000000,
0837     GHC_TO_CLK_GPHY     = 0x00400000,
0838     GHC_TO_CLK_PCIE     = 0x00800000,
0839     GHC_TO_CLK_INVALID  = 0x00C00000,
0840 };
0841 
0842 enum jme_ghc_txmac_clk {
0843     GHC_TXMAC_CLK_OFF   = 0x00000000,
0844     GHC_TXMAC_CLK_GPHY  = 0x00100000,
0845     GHC_TXMAC_CLK_PCIE  = 0x00200000,
0846     GHC_TXMAC_CLK_INVALID   = 0x00300000,
0847 };
0848 
0849 /*
0850  * Power management control and status register
0851  */
0852 enum jme_pmcs_bit_masks {
0853     PMCS_STMASK = 0xFFFF0000,
0854     PMCS_WF7DET = 0x80000000,
0855     PMCS_WF6DET = 0x40000000,
0856     PMCS_WF5DET = 0x20000000,
0857     PMCS_WF4DET = 0x10000000,
0858     PMCS_WF3DET = 0x08000000,
0859     PMCS_WF2DET = 0x04000000,
0860     PMCS_WF1DET = 0x02000000,
0861     PMCS_WF0DET = 0x01000000,
0862     PMCS_LFDET  = 0x00040000,
0863     PMCS_LRDET  = 0x00020000,
0864     PMCS_MFDET  = 0x00010000,
0865     PMCS_ENMASK = 0x0000FFFF,
0866     PMCS_WF7EN  = 0x00008000,
0867     PMCS_WF6EN  = 0x00004000,
0868     PMCS_WF5EN  = 0x00002000,
0869     PMCS_WF4EN  = 0x00001000,
0870     PMCS_WF3EN  = 0x00000800,
0871     PMCS_WF2EN  = 0x00000400,
0872     PMCS_WF1EN  = 0x00000200,
0873     PMCS_WF0EN  = 0x00000100,
0874     PMCS_LFEN   = 0x00000004,
0875     PMCS_LREN   = 0x00000002,
0876     PMCS_MFEN   = 0x00000001,
0877 };
0878 
0879 /*
0880  * New PHY Power Control Register
0881  */
0882 enum jme_phy_pwr_bit_masks {
0883     PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
0884     PHY_PWR_DWN1SW  = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
0885     PHY_PWR_DWN2    = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
0886     PHY_PWR_CLKSEL  = 0x08000000, /*
0887                        * XTL_OUT Clock select
0888                        * (an internal free-running clock)
0889                        * 0: xtl_out = phy_giga.A_XTL25_O
0890                        * 1: xtl_out = phy_giga.PD_OSC
0891                        */
0892 };
0893 
0894 /*
0895  * Giga PHY Status Registers
0896  */
0897 enum jme_phy_link_bit_mask {
0898     PHY_LINK_SPEED_MASK     = 0x0000C000,
0899     PHY_LINK_DUPLEX         = 0x00002000,
0900     PHY_LINK_SPEEDDPU_RESOLVED  = 0x00000800,
0901     PHY_LINK_UP         = 0x00000400,
0902     PHY_LINK_AUTONEG_COMPLETE   = 0x00000200,
0903     PHY_LINK_MDI_STAT       = 0x00000040,
0904 };
0905 
0906 enum jme_phy_link_speed_val {
0907     PHY_LINK_SPEED_10M      = 0x00000000,
0908     PHY_LINK_SPEED_100M     = 0x00004000,
0909     PHY_LINK_SPEED_1000M        = 0x00008000,
0910 };
0911 
0912 #define JME_SPDRSV_TIMEOUT  500 /* 500 us */
0913 
0914 /*
0915  * SMB Control and Status
0916  */
0917 enum jme_smbcsr_bit_mask {
0918     SMBCSR_CNACK    = 0x00020000,
0919     SMBCSR_RELOAD   = 0x00010000,
0920     SMBCSR_EEPROMD  = 0x00000020,
0921     SMBCSR_INITDONE = 0x00000010,
0922     SMBCSR_BUSY = 0x0000000F,
0923 };
0924 
0925 enum jme_smbintf_bit_mask {
0926     SMBINTF_HWDATR  = 0xFF000000,
0927     SMBINTF_HWDATW  = 0x00FF0000,
0928     SMBINTF_HWADDR  = 0x0000FF00,
0929     SMBINTF_HWRWN   = 0x00000020,
0930     SMBINTF_HWCMD   = 0x00000010,
0931     SMBINTF_FASTM   = 0x00000008,
0932     SMBINTF_GPIOSCL = 0x00000004,
0933     SMBINTF_GPIOSDA = 0x00000002,
0934     SMBINTF_GPIOEN  = 0x00000001,
0935 };
0936 
0937 enum jme_smbintf_vals {
0938     SMBINTF_HWRWN_READ  = 0x00000020,
0939     SMBINTF_HWRWN_WRITE = 0x00000000,
0940 };
0941 
0942 enum jme_smbintf_shifts {
0943     SMBINTF_HWDATR_SHIFT    = 24,
0944     SMBINTF_HWDATW_SHIFT    = 16,
0945     SMBINTF_HWADDR_SHIFT    = 8,
0946 };
0947 
0948 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
0949 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
0950 #define JME_SMB_LEN 256
0951 #define JME_EEPROM_MAGIC 0x250
0952 
0953 /*
0954  * Timer Control/Status Register
0955  */
0956 enum jme_tmcsr_bit_masks {
0957     TMCSR_SWIT  = 0x80000000,
0958     TMCSR_EN    = 0x01000000,
0959     TMCSR_CNT   = 0x00FFFFFF,
0960 };
0961 
0962 /*
0963  * General Purpose REG-0
0964  */
0965 enum jme_gpreg0_masks {
0966     GPREG0_DISSH        = 0xFF000000,
0967     GPREG0_PCIRLMT      = 0x00300000,
0968     GPREG0_PCCNOMUTCLR  = 0x00040000,
0969     GPREG0_LNKINTPOLL   = 0x00001000,
0970     GPREG0_PCCTMR       = 0x00000300,
0971     GPREG0_PHYADDR      = 0x0000001F,
0972 };
0973 
0974 enum jme_gpreg0_vals {
0975     GPREG0_DISSH_DW7    = 0x80000000,
0976     GPREG0_DISSH_DW6    = 0x40000000,
0977     GPREG0_DISSH_DW5    = 0x20000000,
0978     GPREG0_DISSH_DW4    = 0x10000000,
0979     GPREG0_DISSH_DW3    = 0x08000000,
0980     GPREG0_DISSH_DW2    = 0x04000000,
0981     GPREG0_DISSH_DW1    = 0x02000000,
0982     GPREG0_DISSH_DW0    = 0x01000000,
0983     GPREG0_DISSH_ALL    = 0xFF000000,
0984 
0985     GPREG0_PCIRLMT_8    = 0x00000000,
0986     GPREG0_PCIRLMT_6    = 0x00100000,
0987     GPREG0_PCIRLMT_5    = 0x00200000,
0988     GPREG0_PCIRLMT_4    = 0x00300000,
0989 
0990     GPREG0_PCCTMR_16ns  = 0x00000000,
0991     GPREG0_PCCTMR_256ns = 0x00000100,
0992     GPREG0_PCCTMR_1us   = 0x00000200,
0993     GPREG0_PCCTMR_1ms   = 0x00000300,
0994 
0995     GPREG0_PHYADDR_1    = 0x00000001,
0996 
0997     GPREG0_DEFAULT      = GPREG0_PCIRLMT_4 |
0998                   GPREG0_PCCTMR_1us |
0999                   GPREG0_PHYADDR_1,
1000 };
1001 
1002 /*
1003  * General Purpose REG-1
1004  */
1005 enum jme_gpreg1_bit_masks {
1006     GPREG1_RXCLKOFF     = 0x04000000,
1007     GPREG1_PCREQN       = 0x00020000,
1008     GPREG1_HALFMODEPATCH    = 0x00000040, /* For Chip revision 0x11 only */
1009     GPREG1_RSSPATCH     = 0x00000020, /* For Chip revision 0x11 only */
1010     GPREG1_INTRDELAYUNIT    = 0x00000018,
1011     GPREG1_INTRDELAYENABLE  = 0x00000007,
1012 };
1013 
1014 enum jme_gpreg1_vals {
1015     GPREG1_INTDLYUNIT_16NS  = 0x00000000,
1016     GPREG1_INTDLYUNIT_256NS = 0x00000008,
1017     GPREG1_INTDLYUNIT_1US   = 0x00000010,
1018     GPREG1_INTDLYUNIT_16US  = 0x00000018,
1019 
1020     GPREG1_INTDLYEN_1U  = 0x00000001,
1021     GPREG1_INTDLYEN_2U  = 0x00000002,
1022     GPREG1_INTDLYEN_3U  = 0x00000003,
1023     GPREG1_INTDLYEN_4U  = 0x00000004,
1024     GPREG1_INTDLYEN_5U  = 0x00000005,
1025     GPREG1_INTDLYEN_6U  = 0x00000006,
1026     GPREG1_INTDLYEN_7U  = 0x00000007,
1027 
1028     GPREG1_DEFAULT      = GPREG1_PCREQN,
1029 };
1030 
1031 /*
1032  * Interrupt Status Bits
1033  */
1034 enum jme_interrupt_bits {
1035     INTR_SWINTR = 0x80000000,
1036     INTR_TMINTR = 0x40000000,
1037     INTR_LINKCH = 0x20000000,
1038     INTR_PAUSERCV   = 0x10000000,
1039     INTR_MAGICRCV   = 0x08000000,
1040     INTR_WAKERCV    = 0x04000000,
1041     INTR_PCCRX0TO   = 0x02000000,
1042     INTR_PCCRX1TO   = 0x01000000,
1043     INTR_PCCRX2TO   = 0x00800000,
1044     INTR_PCCRX3TO   = 0x00400000,
1045     INTR_PCCTXTO    = 0x00200000,
1046     INTR_PCCRX0 = 0x00100000,
1047     INTR_PCCRX1 = 0x00080000,
1048     INTR_PCCRX2 = 0x00040000,
1049     INTR_PCCRX3 = 0x00020000,
1050     INTR_PCCTX  = 0x00010000,
1051     INTR_RX3EMP = 0x00008000,
1052     INTR_RX2EMP = 0x00004000,
1053     INTR_RX1EMP = 0x00002000,
1054     INTR_RX0EMP = 0x00001000,
1055     INTR_RX3    = 0x00000800,
1056     INTR_RX2    = 0x00000400,
1057     INTR_RX1    = 0x00000200,
1058     INTR_RX0    = 0x00000100,
1059     INTR_TX7    = 0x00000080,
1060     INTR_TX6    = 0x00000040,
1061     INTR_TX5    = 0x00000020,
1062     INTR_TX4    = 0x00000010,
1063     INTR_TX3    = 0x00000008,
1064     INTR_TX2    = 0x00000004,
1065     INTR_TX1    = 0x00000002,
1066     INTR_TX0    = 0x00000001,
1067 };
1068 
1069 static const u32 INTR_ENABLE = INTR_SWINTR |
1070                  INTR_TMINTR |
1071                  INTR_LINKCH |
1072                  INTR_PCCRX0TO |
1073                  INTR_PCCRX0 |
1074                  INTR_PCCTXTO |
1075                  INTR_PCCTX |
1076                  INTR_RX0EMP;
1077 
1078 /*
1079  * PCC Control Registers
1080  */
1081 enum jme_pccrx_masks {
1082     PCCRXTO_MASK    = 0xFFFF0000,
1083     PCCRX_MASK  = 0x0000FF00,
1084 };
1085 
1086 enum jme_pcctx_masks {
1087     PCCTXTO_MASK    = 0xFFFF0000,
1088     PCCTX_MASK  = 0x0000FF00,
1089     PCCTX_QS_MASK   = 0x000000FF,
1090 };
1091 
1092 enum jme_pccrx_shifts {
1093     PCCRXTO_SHIFT   = 16,
1094     PCCRX_SHIFT = 8,
1095 };
1096 
1097 enum jme_pcctx_shifts {
1098     PCCTXTO_SHIFT   = 16,
1099     PCCTX_SHIFT = 8,
1100 };
1101 
1102 enum jme_pcctx_bits {
1103     PCCTXQ0_EN  = 0x00000001,
1104     PCCTXQ1_EN  = 0x00000002,
1105     PCCTXQ2_EN  = 0x00000004,
1106     PCCTXQ3_EN  = 0x00000008,
1107     PCCTXQ4_EN  = 0x00000010,
1108     PCCTXQ5_EN  = 0x00000020,
1109     PCCTXQ6_EN  = 0x00000040,
1110     PCCTXQ7_EN  = 0x00000080,
1111 };
1112 
1113 /*
1114  * Chip Mode Register
1115  */
1116 enum jme_chipmode_bit_masks {
1117     CM_FPGAVER_MASK     = 0xFFFF0000,
1118     CM_CHIPREV_MASK     = 0x0000FF00,
1119     CM_CHIPMODE_MASK    = 0x0000000F,
1120 };
1121 
1122 enum jme_chipmode_shifts {
1123     CM_FPGAVER_SHIFT    = 16,
1124     CM_CHIPREV_SHIFT    = 8,
1125 };
1126 
1127 /*
1128  * Aggressive Power Mode Control
1129  */
1130 enum jme_apmc_bits {
1131     JME_APMC_PCIE_SD_EN = 0x40000000,
1132     JME_APMC_PSEUDO_HP_EN   = 0x20000000,
1133     JME_APMC_EPIEN      = 0x04000000,
1134     JME_APMC_EPIEN_CTRL = 0x03000000,
1135 };
1136 
1137 enum jme_apmc_values {
1138     JME_APMC_EPIEN_CTRL_EN  = 0x02000000,
1139     JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1140 };
1141 
1142 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1143 
1144 #ifdef REG_DEBUG
1145 static char *MAC_REG_NAME[] = {
1146     "JME_TXCS",      "JME_TXDBA_LO",  "JME_TXDBA_HI", "JME_TXQDC",
1147     "JME_TXNDA",     "JME_TXMCS",     "JME_TXPFC",    "JME_TXTRHD",
1148     "JME_RXCS",      "JME_RXDBA_LO",  "JME_RXDBA_HI", "JME_RXQDC",
1149     "JME_RXNDA",     "JME_RXMCS",     "JME_RXUMA_LO", "JME_RXUMA_HI",
1150     "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP",    "JME_WFOI",
1151     "JME_SMI",       "JME_GHC",       "UNKNOWN",      "UNKNOWN",
1152     "JME_PMCS"};
1153 
1154 static char *PE_REG_NAME[] = {
1155     "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1156     "UNKNOWN",      "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1157     "UNKNOWN",      "UNKNOWN",     "JME_PHY_CS", "UNKNOWN",
1158     "JME_PHY_LINK", "UNKNOWN",     "UNKNOWN",    "UNKNOWN",
1159     "JME_SMBCSR",   "JME_SMBINTF"};
1160 
1161 static char *MISC_REG_NAME[] = {
1162     "JME_TMCSR",  "JME_GPIO",     "JME_GPREG0",  "JME_GPREG1",
1163     "JME_IEVE",   "JME_IREQ",     "JME_IENS",    "JME_IENC",
1164     "JME_PCCRX0", "JME_PCCRX1",   "JME_PCCRX2",  "JME_PCCRX3",
1165     "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1166     "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1167     "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1168     "UNKNOWN",    "UNKNOWN",      "UNKNOWN",     "UNKNOWN",
1169     "JME_TIMER1", "JME_TIMER2",   "UNKNOWN",     "JME_APMC",
1170     "JME_PCCSRX0"};
1171 
1172 static inline void reg_dbg(const struct jme_adapter *jme,
1173         const char *msg, u32 val, u32 reg)
1174 {
1175     const char *regname;
1176     switch (reg & 0xF00) {
1177     case 0x000:
1178         regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1179         break;
1180     case 0x400:
1181         regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1182         break;
1183     case 0x800:
1184         regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1185         break;
1186     default:
1187         regname = PE_REG_NAME[0];
1188     }
1189     printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1190             msg, val, regname);
1191 }
1192 #else
1193 static inline void reg_dbg(const struct jme_adapter *jme,
1194         const char *msg, u32 val, u32 reg) {}
1195 #endif
1196 
1197 /*
1198  * Read/Write MMaped I/O Registers
1199  */
1200 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1201 {
1202     return readl(jme->regs + reg);
1203 }
1204 
1205 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1206 {
1207     reg_dbg(jme, "REG WRITE", val, reg);
1208     writel(val, jme->regs + reg);
1209     reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1210 }
1211 
1212 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1213 {
1214     /*
1215      * Read after write should cause flush
1216      */
1217     reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1218     writel(val, jme->regs + reg);
1219     readl(jme->regs + reg);
1220     reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1221 }
1222 
1223 /*
1224  * PHY Regs
1225  */
1226 enum jme_phy_reg17_bit_masks {
1227     PREG17_SPEED        = 0xC000,
1228     PREG17_DUPLEX       = 0x2000,
1229     PREG17_SPDRSV       = 0x0800,
1230     PREG17_LNKUP        = 0x0400,
1231     PREG17_MDI      = 0x0040,
1232 };
1233 
1234 enum jme_phy_reg17_vals {
1235     PREG17_SPEED_10M    = 0x0000,
1236     PREG17_SPEED_100M   = 0x4000,
1237     PREG17_SPEED_1000M  = 0x8000,
1238 };
1239 
1240 #define BMSR_ANCOMP               0x0020
1241 
1242 /*
1243  * Workaround
1244  */
1245 static inline int is_buggy250(unsigned short device, u8 chiprev)
1246 {
1247     return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1248 }
1249 
1250 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1251 {
1252     return chip_main_rev >= 5;
1253 }
1254 
1255 /*
1256  * Function prototypes
1257  */
1258 static int jme_set_link_ksettings(struct net_device *netdev,
1259                   const struct ethtool_link_ksettings *cmd);
1260 static void jme_set_unicastaddr(struct net_device *netdev);
1261 static void jme_set_multi(struct net_device *netdev);
1262 
1263 #endif
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