intel/ixgbevf/defines.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #ifndef _IXGBEVF_DEFINES_H_
0005 #define _IXGBEVF_DEFINES_H_
0006
0007 /* Device IDs */
0008 #define IXGBE_DEV_ID_82599_VF       0x10ED
0009 #define IXGBE_DEV_ID_X540_VF        0x1515
0010 #define IXGBE_DEV_ID_X550_VF        0x1565
0011 #define IXGBE_DEV_ID_X550EM_X_VF    0x15A8
0012 #define IXGBE_DEV_ID_X550EM_A_VF    0x15C5
0013
0014 #define IXGBE_DEV_ID_82599_VF_HV    0x152E
0015 #define IXGBE_DEV_ID_X540_VF_HV     0x1530
0016 #define IXGBE_DEV_ID_X550_VF_HV     0x1564
0017 #define IXGBE_DEV_ID_X550EM_X_VF_HV 0x15A9
0018
0019 #define IXGBE_VF_IRQ_CLEAR_MASK     7
0020 #define IXGBE_VF_MAX_TX_QUEUES      8
0021 #define IXGBE_VF_MAX_RX_QUEUES      8
0022
0023 /* DCB define */
0024 #define IXGBE_VF_MAX_TRAFFIC_CLASS  8
0025
0026 /* Link speed */
0027 typedef u32 ixgbe_link_speed;
0028 #define IXGBE_LINK_SPEED_1GB_FULL   0x0020
0029 #define IXGBE_LINK_SPEED_10GB_FULL  0x0080
0030 #define IXGBE_LINK_SPEED_100_FULL   0x0008
0031
0032 #define IXGBE_CTRL_RST      0x04000000 /* Reset (SW) */
0033 #define IXGBE_RXDCTL_ENABLE 0x02000000 /* Enable specific Rx Queue */
0034 #define IXGBE_TXDCTL_ENABLE 0x02000000 /* Enable specific Tx Queue */
0035 #define IXGBE_LINKS_UP      0x40000000
0036 #define IXGBE_LINKS_SPEED_82599     0x30000000
0037 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
0038 #define IXGBE_LINKS_SPEED_1G_82599  0x20000000
0039 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
0040
0041 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
0042 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE    8
0043 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE    8
0044 #define IXGBE_REQ_TX_BUFFER_GRANULARITY     1024
0045
0046 /* Interrupt Vector Allocation Registers */
0047 #define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid */
0048
0049 #define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
0050
0051 /* Receive Config masks */
0052 #define IXGBE_RXCTRL_RXEN   0x00000001  /* Enable Receiver */
0053 #define IXGBE_RXCTRL_DMBYPS 0x00000002  /* Descriptor Monitor Bypass */
0054 #define IXGBE_RXDCTL_ENABLE 0x02000000  /* Enable specific Rx Queue */
0055 #define IXGBE_RXDCTL_VME    0x40000000  /* VLAN mode enable */
0056 #define IXGBE_RXDCTL_RLPMLMASK  0x00003FFF  /* Only supported on the X540 */
0057 #define IXGBE_RXDCTL_RLPML_EN   0x00008000
0058
0059 /* DCA Control */
0060 #define IXGBE_DCA_TXCTRL_TX_WB_RO_EN BIT(11) /* Tx Desc writeback RO bit */
0061
0062 /* PSRTYPE bit definitions */
0063 #define IXGBE_PSRTYPE_TCPHDR    0x00000010
0064 #define IXGBE_PSRTYPE_UDPHDR    0x00000020
0065 #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
0066 #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
0067 #define IXGBE_PSRTYPE_L2HDR 0x00001000
0068
0069 /* SRRCTL bit definitions */
0070 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10     /* so many KBs */
0071 #define IXGBE_SRRCTL_RDMTS_SHIFT    22
0072 #define IXGBE_SRRCTL_RDMTS_MASK     0x01C00000
0073 #define IXGBE_SRRCTL_DROP_EN        0x10000000
0074 #define IXGBE_SRRCTL_BSIZEPKT_MASK  0x0000007F
0075 #define IXGBE_SRRCTL_BSIZEHDR_MASK  0x00003F00
0076 #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
0077 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
0078 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
0079 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
0080 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
0081 #define IXGBE_SRRCTL_DESCTYPE_MASK  0x0E000000
0082
0083 /* Receive Descriptor bit definitions */
0084 #define IXGBE_RXD_STAT_DD   0x01    /* Descriptor Done */
0085 #define IXGBE_RXD_STAT_EOP  0x02    /* End of Packet */
0086 #define IXGBE_RXD_STAT_FLM  0x04    /* FDir Match */
0087 #define IXGBE_RXD_STAT_VP   0x08    /* IEEE VLAN Packet */
0088 #define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */
0089 #define IXGBE_RXDADV_NEXTP_SHIFT    0x00000004
0090 #define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
0091 #define IXGBE_RXD_STAT_L4CS 0x20    /* L4 xsum calculated */
0092 #define IXGBE_RXD_STAT_IPCS 0x40    /* IP xsum calculated */
0093 #define IXGBE_RXD_STAT_PIF  0x80    /* passed in-exact filter */
0094 #define IXGBE_RXD_STAT_CRCV 0x100   /* Speculative CRC Valid */
0095 #define IXGBE_RXD_STAT_VEXT 0x200   /* 1st VLAN found */
0096 #define IXGBE_RXD_STAT_UDPV 0x400   /* Valid UDP checksum */
0097 #define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
0098 #define IXGBE_RXD_STAT_TS   0x10000 /* Time Stamp */
0099 #define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */
0100 #define IXGBE_RXD_STAT_LB   0x40000 /* Loopback Status */
0101 #define IXGBE_RXD_STAT_ACK  0x8000  /* ACK Packet indication */
0102 #define IXGBE_RXD_ERR_CE    0x01    /* CRC Error */
0103 #define IXGBE_RXD_ERR_LE    0x02    /* Length Error */
0104 #define IXGBE_RXD_ERR_PE    0x08    /* Packet Error */
0105 #define IXGBE_RXD_ERR_OSE   0x10    /* Oversize Error */
0106 #define IXGBE_RXD_ERR_USE   0x20    /* Undersize Error */
0107 #define IXGBE_RXD_ERR_TCPE  0x40    /* TCP/UDP Checksum Error */
0108 #define IXGBE_RXD_ERR_IPE   0x80    /* IP Checksum Error */
0109 #define IXGBE_RXDADV_ERR_MASK   0xFFF00000 /* RDESC.ERRORS mask */
0110 #define IXGBE_RXDADV_ERR_SHIFT  20         /* RDESC.ERRORS shift */
0111 #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
0112 #define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */
0113 #define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */
0114 #define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */
0115 #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
0116 #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
0117 #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
0118 #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
0119 #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
0120 #define IXGBE_RXD_PRI_MASK  0xE000  /* Priority is in upper 3 bits */
0121 #define IXGBE_RXD_PRI_SHIFT 13
0122 #define IXGBE_RXD_CFI_MASK  0x1000  /* CFI is bit 12 */
0123 #define IXGBE_RXD_CFI_SHIFT 12
0124
0125 #define IXGBE_RXDADV_STAT_DD        IXGBE_RXD_STAT_DD  /* Done */
0126 #define IXGBE_RXDADV_STAT_EOP       IXGBE_RXD_STAT_EOP /* End of Packet */
0127 #define IXGBE_RXDADV_STAT_FLM       IXGBE_RXD_STAT_FLM /* FDir Match */
0128 #define IXGBE_RXDADV_STAT_VP        IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
0129 #define IXGBE_RXDADV_STAT_MASK      0x000FFFFF /* Stat/NEXTP: bit 0-19 */
0130 #define IXGBE_RXDADV_STAT_FCEOFS    0x00000040 /* FCoE EOF/SOF Stat */
0131 #define IXGBE_RXDADV_STAT_FCSTAT    0x00000030 /* FCoE Pkt Stat */
0132 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
0133 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
0134 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
0135 #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
0136 #define IXGBE_RXDADV_STAT_SECP      0x00020000 /* IPsec/MACsec pkt found */
0137
0138 #define IXGBE_RXDADV_RSSTYPE_MASK   0x0000000F
0139 #define IXGBE_RXDADV_PKTTYPE_MASK   0x0000FFF0
0140 #define IXGBE_RXDADV_PKTTYPE_IPV4   0x00000010 /* IPv4 hdr present */
0141 #define IXGBE_RXDADV_PKTTYPE_IPV6   0x00000040 /* IPv6 hdr present */
0142 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
0143 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
0144 #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
0145 #define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0
0146 #define IXGBE_RXDADV_RSCCNT_MASK    0x001E0000
0147 #define IXGBE_RXDADV_RSCCNT_SHIFT   17
0148 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
0149 #define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000
0150 #define IXGBE_RXDADV_SPH        0x8000
0151
0152 /* RSS Hash results */
0153 #define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
0154 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP       0x00000001
0155 #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
0156 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP       0x00000003
0157 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX        0x00000004
0158 #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
0159 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX    0x00000006
0160 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP       0x00000007
0161 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP       0x00000008
0162 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX    0x00000009
0163
0164 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
0165                       IXGBE_RXD_ERR_CE |  \
0166                       IXGBE_RXD_ERR_LE |  \
0167                       IXGBE_RXD_ERR_PE |  \
0168                       IXGBE_RXD_ERR_OSE | \
0169                       IXGBE_RXD_ERR_USE)
0170
0171 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
0172                      IXGBE_RXDADV_ERR_CE |  \
0173                      IXGBE_RXDADV_ERR_LE |  \
0174                      IXGBE_RXDADV_ERR_PE |  \
0175                      IXGBE_RXDADV_ERR_OSE | \
0176                      IXGBE_RXDADV_ERR_USE)
0177
0178 #define IXGBE_TXD_POPTS_IXSM    0x01       /* Insert IP checksum */
0179 #define IXGBE_TXD_POPTS_TXSM    0x02       /* Insert TCP/UDP checksum */
0180 #define IXGBE_TXD_CMD_EOP   0x01000000 /* End of Packet */
0181 #define IXGBE_TXD_CMD_IFCS  0x02000000 /* Insert FCS (Ethernet CRC) */
0182 #define IXGBE_TXD_CMD_IC    0x04000000 /* Insert Checksum */
0183 #define IXGBE_TXD_CMD_RS    0x08000000 /* Report Status */
0184 #define IXGBE_TXD_CMD_DEXT  0x20000000 /* Descriptor ext (0 = legacy) */
0185 #define IXGBE_TXD_CMD_VLE   0x40000000 /* Add VLAN tag */
0186 #define IXGBE_TXD_STAT_DD   0x00000001 /* Descriptor Done */
0187 #define IXGBE_TXD_CMD       (IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS)
0188
0189 /* Transmit Descriptor - Advanced */
0190 union ixgbe_adv_tx_desc {
0191     struct {
0192         __le64 buffer_addr;      /* Address of descriptor's data buf */
0193         __le32 cmd_type_len;
0194         __le32 olinfo_status;
0195     } read;
0196     struct {
0197         __le64 rsvd;       /* Reserved */
0198         __le32 nxtseq_seed;
0199         __le32 status;
0200     } wb;
0201 };
0202
0203 /* Receive Descriptor - Advanced */
0204 union ixgbe_adv_rx_desc {
0205     struct {
0206         __le64 pkt_addr; /* Packet buffer address */
0207         __le64 hdr_addr; /* Header buffer address */
0208     } read;
0209     struct {
0210         struct {
0211             union {
0212                 __le32 data;
0213                 struct {
0214                     __le16 pkt_info; /* RSS, Pkt type */
0215                     __le16 hdr_info; /* Splithdr, hdrlen */
0216                 } hs_rss;
0217             } lo_dword;
0218             union {
0219                 __le32 rss; /* RSS Hash */
0220                 struct {
0221                     __le16 ip_id; /* IP id */
0222                     __le16 csum; /* Packet Checksum */
0223                 } csum_ip;
0224             } hi_dword;
0225         } lower;
0226         struct {
0227             __le32 status_error; /* ext status/error */
0228             __le16 length; /* Packet length */
0229             __le16 vlan; /* VLAN tag */
0230         } upper;
0231     } wb;  /* writeback */
0232 };
0233
0234 /* Context descriptors */
0235 struct ixgbe_adv_tx_context_desc {
0236     __le32 vlan_macip_lens;
0237     __le32 fceof_saidx;
0238     __le32 type_tucmd_mlhl;
0239     __le32 mss_l4len_idx;
0240 };
0241
0242 /* Adv Transmit Descriptor Config Masks */
0243 #define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
0244 #define IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */
0245 #define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
0246 #define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
0247 #define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
0248 #define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
0249 #define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
0250 #define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
0251 #define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
0252 #define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
0253 #define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400  /* IP Packet Type: 1=IPv4 */
0254 #define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000  /* IP Packet Type: 0=IPv6 */
0255 #define IXGBE_ADVTXD_TUCMD_L4T_UDP  0x00000000  /* L4 Packet TYPE of UDP */
0256 #define IXGBE_ADVTXD_TUCMD_L4T_TCP  0x00000800  /* L4 Packet TYPE of TCP */
0257 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000  /* L4 Packet TYPE of SCTP */
0258 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP   0x00002000 /* IPSec Type ESP */
0259 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000 /* ESP Encrypt Enable */
0260 #define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
0261 #define IXGBE_ADVTXD_CC     0x00000080 /* Check Context */
0262 #define IXGBE_ADVTXD_POPTS_SHIFT    8  /* Adv desc POPTS shift */
0263 #define IXGBE_ADVTXD_POPTS_IPSEC    0x00000400 /* IPSec offload request */
0264 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
0265                  IXGBE_ADVTXD_POPTS_SHIFT)
0266 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
0267                  IXGBE_ADVTXD_POPTS_SHIFT)
0268 #define IXGBE_ADVTXD_PAYLEN_SHIFT   14 /* Adv desc PAYLEN shift */
0269 #define IXGBE_ADVTXD_MACLEN_SHIFT   9  /* Adv ctxt desc mac len shift */
0270 #define IXGBE_ADVTXD_VLAN_SHIFT     16 /* Adv ctxt vlan tag shift */
0271 #define IXGBE_ADVTXD_L4LEN_SHIFT    8  /* Adv ctxt L4LEN shift */
0272 #define IXGBE_ADVTXD_MSS_SHIFT      16 /* Adv ctxt MSS shift */
0273
0274 /* Interrupt register bitmasks */
0275
0276 #define IXGBE_EITR_CNT_WDIS 0x80000000
0277 #define IXGBE_MAX_EITR      0x00000FF8
0278 #define IXGBE_MIN_EITR      8
0279
0280 /* Error Codes */
0281 #define IXGBE_ERR_INVALID_MAC_ADDR  -1
0282 #define IXGBE_ERR_RESET_FAILED      -2
0283 #define IXGBE_ERR_INVALID_ARGUMENT  -3
0284 #define IXGBE_ERR_CONFIG        -4
0285 #define IXGBE_ERR_MBX           -5
0286 #define IXGBE_ERR_TIMEOUT       -6
0287 #define IXGBE_ERR_PARAM         -7
0288
0289 /* Transmit Config masks */
0290 #define IXGBE_TXDCTL_ENABLE     0x02000000 /* Ena specific Tx Queue */
0291 #define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. wr-bk flushing */
0292 #define IXGBE_TXDCTL_WTHRESH_SHIFT  16     /* shift to WTHRESH bits */
0293
0294 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN    BIT(5)  /* Rx Desc enable */
0295 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN    BIT(6)  /* Rx Desc header ena */
0296 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN    BIT(7)  /* Rx Desc payload ena */
0297 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN    BIT(9)  /* Rx rd Desc Relax Order */
0298 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN    BIT(13) /* Rx wr data Relax Order */
0299 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN    BIT(15) /* Rx wr header RO */
0300
0301 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN    BIT(5)  /* DCA Tx Desc enable */
0302 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN    BIT(9)  /* Tx rd Desc Relax Order */
0303 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN    BIT(11) /* Tx Desc writeback RO bit */
0304 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN    BIT(13) /* Tx rd data Relax Order */
0305
0306 #endif /* _IXGBEVF_DEFINES_H_ */