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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003 
0004 #include <linux/pci.h>
0005 #include <linux/delay.h>
0006 #include <linux/sched.h>
0007 
0008 #include "ixgbe.h"
0009 #include "ixgbe_phy.h"
0010 #include "ixgbe_x540.h"
0011 
0012 #define IXGBE_X540_MAX_TX_QUEUES    128
0013 #define IXGBE_X540_MAX_RX_QUEUES    128
0014 #define IXGBE_X540_RAR_ENTRIES      128
0015 #define IXGBE_X540_MC_TBL_SIZE      128
0016 #define IXGBE_X540_VFT_TBL_SIZE     128
0017 #define IXGBE_X540_RX_PB_SIZE       384
0018 
0019 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw);
0020 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw);
0021 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw);
0022 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw);
0023 
0024 enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw)
0025 {
0026     return ixgbe_media_type_copper;
0027 }
0028 
0029 s32 ixgbe_get_invariants_X540(struct ixgbe_hw *hw)
0030 {
0031     struct ixgbe_mac_info *mac = &hw->mac;
0032     struct ixgbe_phy_info *phy = &hw->phy;
0033 
0034     /* set_phy_power was set by default to NULL */
0035     phy->ops.set_phy_power = ixgbe_set_copper_phy_power;
0036 
0037     mac->mcft_size = IXGBE_X540_MC_TBL_SIZE;
0038     mac->vft_size = IXGBE_X540_VFT_TBL_SIZE;
0039     mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES;
0040     mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE;
0041     mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES;
0042     mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES;
0043     mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
0044 
0045     return 0;
0046 }
0047 
0048 /**
0049  *  ixgbe_setup_mac_link_X540 - Set the auto advertised capabilitires
0050  *  @hw: pointer to hardware structure
0051  *  @speed: new link speed
0052  *  @autoneg_wait_to_complete: true when waiting for completion is needed
0053  **/
0054 s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, ixgbe_link_speed speed,
0055                   bool autoneg_wait_to_complete)
0056 {
0057     return hw->phy.ops.setup_link_speed(hw, speed,
0058                         autoneg_wait_to_complete);
0059 }
0060 
0061 /**
0062  *  ixgbe_reset_hw_X540 - Perform hardware reset
0063  *  @hw: pointer to hardware structure
0064  *
0065  *  Resets the hardware by resetting the transmit and receive units, masks
0066  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
0067  *  reset.
0068  **/
0069 s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw)
0070 {
0071     s32 status;
0072     u32 ctrl, i;
0073     u32 swfw_mask = hw->phy.phy_semaphore_mask;
0074 
0075     /* Call adapter stop to disable tx/rx and clear interrupts */
0076     status = hw->mac.ops.stop_adapter(hw);
0077     if (status)
0078         return status;
0079 
0080     /* flush pending Tx transactions */
0081     ixgbe_clear_tx_pending(hw);
0082 
0083 mac_reset_top:
0084     status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);
0085     if (status) {
0086         hw_dbg(hw, "semaphore failed with %d", status);
0087         return IXGBE_ERR_SWFW_SYNC;
0088     }
0089 
0090     ctrl = IXGBE_CTRL_RST;
0091     ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
0092     IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
0093     IXGBE_WRITE_FLUSH(hw);
0094     hw->mac.ops.release_swfw_sync(hw, swfw_mask);
0095     usleep_range(1000, 1200);
0096 
0097     /* Poll for reset bit to self-clear indicating reset is complete */
0098     for (i = 0; i < 10; i++) {
0099         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
0100         if (!(ctrl & IXGBE_CTRL_RST_MASK))
0101             break;
0102         udelay(1);
0103     }
0104 
0105     if (ctrl & IXGBE_CTRL_RST_MASK) {
0106         status = IXGBE_ERR_RESET_FAILED;
0107         hw_dbg(hw, "Reset polling failed to complete.\n");
0108     }
0109     msleep(100);
0110 
0111     /*
0112      * Double resets are required for recovery from certain error
0113      * conditions.  Between resets, it is necessary to stall to allow time
0114      * for any pending HW events to complete.
0115      */
0116     if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
0117         hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
0118         goto mac_reset_top;
0119     }
0120 
0121     /* Set the Rx packet buffer size. */
0122     IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);
0123 
0124     /* Store the permanent mac address */
0125     hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
0126 
0127     /*
0128      * Store MAC address from RAR0, clear receive address registers, and
0129      * clear the multicast table.  Also reset num_rar_entries to 128,
0130      * since we modify this value when programming the SAN MAC address.
0131      */
0132     hw->mac.num_rar_entries = IXGBE_X540_MAX_TX_QUEUES;
0133     hw->mac.ops.init_rx_addrs(hw);
0134 
0135     /* Store the permanent SAN mac address */
0136     hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
0137 
0138     /* Add the SAN MAC address to the RAR only if it's a valid address */
0139     if (is_valid_ether_addr(hw->mac.san_addr)) {
0140         /* Save the SAN MAC RAR index */
0141         hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
0142 
0143         hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index,
0144                     hw->mac.san_addr, 0, IXGBE_RAH_AV);
0145 
0146         /* clear VMDq pool/queue selection for this RAR */
0147         hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index,
0148                        IXGBE_CLEAR_VMDQ_ALL);
0149 
0150         /* Reserve the last RAR for the SAN MAC address */
0151         hw->mac.num_rar_entries--;
0152     }
0153 
0154     /* Store the alternative WWNN/WWPN prefix */
0155     hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
0156                    &hw->mac.wwpn_prefix);
0157 
0158     return status;
0159 }
0160 
0161 /**
0162  *  ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx
0163  *  @hw: pointer to hardware structure
0164  *
0165  *  Starts the hardware using the generic start_hw function
0166  *  and the generation start_hw function.
0167  *  Then performs revision-specific operations, if any.
0168  **/
0169 s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw)
0170 {
0171     s32 ret_val;
0172 
0173     ret_val = ixgbe_start_hw_generic(hw);
0174     if (ret_val)
0175         return ret_val;
0176 
0177     return ixgbe_start_hw_gen2(hw);
0178 }
0179 
0180 /**
0181  *  ixgbe_init_eeprom_params_X540 - Initialize EEPROM params
0182  *  @hw: pointer to hardware structure
0183  *
0184  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
0185  *  ixgbe_hw struct in order to set up EEPROM access.
0186  **/
0187 s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw)
0188 {
0189     struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
0190     u32 eec;
0191     u16 eeprom_size;
0192 
0193     if (eeprom->type == ixgbe_eeprom_uninitialized) {
0194         eeprom->semaphore_delay = 10;
0195         eeprom->type = ixgbe_flash;
0196 
0197         eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
0198         eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
0199                     IXGBE_EEC_SIZE_SHIFT);
0200         eeprom->word_size = BIT(eeprom_size +
0201                     IXGBE_EEPROM_WORD_SIZE_SHIFT);
0202 
0203         hw_dbg(hw, "Eeprom params: type = %d, size = %d\n",
0204                eeprom->type, eeprom->word_size);
0205     }
0206 
0207     return 0;
0208 }
0209 
0210 /**
0211  *  ixgbe_read_eerd_X540- Read EEPROM word using EERD
0212  *  @hw: pointer to hardware structure
0213  *  @offset: offset of  word in the EEPROM to read
0214  *  @data: word read from the EEPROM
0215  *
0216  *  Reads a 16 bit word from the EEPROM using the EERD register.
0217  **/
0218 static s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data)
0219 {
0220     s32 status;
0221 
0222     if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
0223         return IXGBE_ERR_SWFW_SYNC;
0224 
0225     status = ixgbe_read_eerd_generic(hw, offset, data);
0226 
0227     hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
0228     return status;
0229 }
0230 
0231 /**
0232  *  ixgbe_read_eerd_buffer_X540 - Read EEPROM word(s) using EERD
0233  *  @hw: pointer to hardware structure
0234  *  @offset: offset of  word in the EEPROM to read
0235  *  @words: number of words
0236  *  @data: word(s) read from the EEPROM
0237  *
0238  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
0239  **/
0240 static s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw,
0241                        u16 offset, u16 words, u16 *data)
0242 {
0243     s32 status;
0244 
0245     if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
0246         return IXGBE_ERR_SWFW_SYNC;
0247 
0248     status = ixgbe_read_eerd_buffer_generic(hw, offset, words, data);
0249 
0250     hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
0251     return status;
0252 }
0253 
0254 /**
0255  *  ixgbe_write_eewr_X540 - Write EEPROM word using EEWR
0256  *  @hw: pointer to hardware structure
0257  *  @offset: offset of  word in the EEPROM to write
0258  *  @data: word write to the EEPROM
0259  *
0260  *  Write a 16 bit word to the EEPROM using the EEWR register.
0261  **/
0262 static s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data)
0263 {
0264     s32 status;
0265 
0266     if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
0267         return IXGBE_ERR_SWFW_SYNC;
0268 
0269     status = ixgbe_write_eewr_generic(hw, offset, data);
0270 
0271     hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
0272     return status;
0273 }
0274 
0275 /**
0276  *  ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR
0277  *  @hw: pointer to hardware structure
0278  *  @offset: offset of  word in the EEPROM to write
0279  *  @words: number of words
0280  *  @data: word(s) write to the EEPROM
0281  *
0282  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
0283  **/
0284 static s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw,
0285                     u16 offset, u16 words, u16 *data)
0286 {
0287     s32 status;
0288 
0289     if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
0290         return IXGBE_ERR_SWFW_SYNC;
0291 
0292     status = ixgbe_write_eewr_buffer_generic(hw, offset, words, data);
0293 
0294     hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
0295     return status;
0296 }
0297 
0298 /**
0299  *  ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum
0300  *
0301  *  This function does not use synchronization for EERD and EEWR. It can
0302  *  be used internally by function which utilize ixgbe_acquire_swfw_sync_X540.
0303  *
0304  *  @hw: pointer to hardware structure
0305  **/
0306 static s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw)
0307 {
0308     u16 i;
0309     u16 j;
0310     u16 checksum = 0;
0311     u16 length = 0;
0312     u16 pointer = 0;
0313     u16 word = 0;
0314     u16 checksum_last_word = IXGBE_EEPROM_CHECKSUM;
0315     u16 ptr_start = IXGBE_PCIE_ANALOG_PTR;
0316 
0317     /*
0318      * Do not use hw->eeprom.ops.read because we do not want to take
0319      * the synchronization semaphores here. Instead use
0320      * ixgbe_read_eerd_generic
0321      */
0322 
0323     /* Include 0x0-0x3F in the checksum */
0324     for (i = 0; i < checksum_last_word; i++) {
0325         if (ixgbe_read_eerd_generic(hw, i, &word)) {
0326             hw_dbg(hw, "EEPROM read failed\n");
0327             return IXGBE_ERR_EEPROM;
0328         }
0329         checksum += word;
0330     }
0331 
0332     /*
0333      * Include all data from pointers 0x3, 0x6-0xE.  This excludes the
0334      * FW, PHY module, and PCIe Expansion/Option ROM pointers.
0335      */
0336     for (i = ptr_start; i < IXGBE_FW_PTR; i++) {
0337         if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR)
0338             continue;
0339 
0340         if (ixgbe_read_eerd_generic(hw, i, &pointer)) {
0341             hw_dbg(hw, "EEPROM read failed\n");
0342             break;
0343         }
0344 
0345         /* Skip pointer section if the pointer is invalid. */
0346         if (pointer == 0xFFFF || pointer == 0 ||
0347             pointer >= hw->eeprom.word_size)
0348             continue;
0349 
0350         if (ixgbe_read_eerd_generic(hw, pointer, &length)) {
0351             hw_dbg(hw, "EEPROM read failed\n");
0352             return IXGBE_ERR_EEPROM;
0353         }
0354 
0355         /* Skip pointer section if length is invalid. */
0356         if (length == 0xFFFF || length == 0 ||
0357             (pointer + length) >= hw->eeprom.word_size)
0358             continue;
0359 
0360         for (j = pointer + 1; j <= pointer + length; j++) {
0361             if (ixgbe_read_eerd_generic(hw, j, &word)) {
0362                 hw_dbg(hw, "EEPROM read failed\n");
0363                 return IXGBE_ERR_EEPROM;
0364             }
0365             checksum += word;
0366         }
0367     }
0368 
0369     checksum = (u16)IXGBE_EEPROM_SUM - checksum;
0370 
0371     return (s32)checksum;
0372 }
0373 
0374 /**
0375  *  ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum
0376  *  @hw: pointer to hardware structure
0377  *  @checksum_val: calculated checksum
0378  *
0379  *  Performs checksum calculation and validates the EEPROM checksum.  If the
0380  *  caller does not need checksum_val, the value can be NULL.
0381  **/
0382 static s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw,
0383                            u16 *checksum_val)
0384 {
0385     s32 status;
0386     u16 checksum;
0387     u16 read_checksum = 0;
0388 
0389     /* Read the first word from the EEPROM. If this times out or fails, do
0390      * not continue or we could be in for a very long wait while every
0391      * EEPROM read fails
0392      */
0393     status = hw->eeprom.ops.read(hw, 0, &checksum);
0394     if (status) {
0395         hw_dbg(hw, "EEPROM read failed\n");
0396         return status;
0397     }
0398 
0399     if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
0400         return IXGBE_ERR_SWFW_SYNC;
0401 
0402     status = hw->eeprom.ops.calc_checksum(hw);
0403     if (status < 0)
0404         goto out;
0405 
0406     checksum = (u16)(status & 0xffff);
0407 
0408     /* Do not use hw->eeprom.ops.read because we do not want to take
0409      * the synchronization semaphores twice here.
0410      */
0411     status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM,
0412                      &read_checksum);
0413     if (status)
0414         goto out;
0415 
0416     /* Verify read checksum from EEPROM is the same as
0417      * calculated checksum
0418      */
0419     if (read_checksum != checksum) {
0420         hw_dbg(hw, "Invalid EEPROM checksum");
0421         status = IXGBE_ERR_EEPROM_CHECKSUM;
0422     }
0423 
0424     /* If the user cares, return the calculated checksum */
0425     if (checksum_val)
0426         *checksum_val = checksum;
0427 
0428 out:
0429     hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
0430 
0431     return status;
0432 }
0433 
0434 /**
0435  * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash
0436  * @hw: pointer to hardware structure
0437  *
0438  * After writing EEPROM to shadow RAM using EEWR register, software calculates
0439  * checksum and updates the EEPROM and instructs the hardware to update
0440  * the flash.
0441  **/
0442 static s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw)
0443 {
0444     s32 status;
0445     u16 checksum;
0446 
0447     /* Read the first word from the EEPROM. If this times out or fails, do
0448      * not continue or we could be in for a very long wait while every
0449      * EEPROM read fails
0450      */
0451     status = hw->eeprom.ops.read(hw, 0, &checksum);
0452     if (status) {
0453         hw_dbg(hw, "EEPROM read failed\n");
0454         return status;
0455     }
0456 
0457     if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM))
0458         return  IXGBE_ERR_SWFW_SYNC;
0459 
0460     status = hw->eeprom.ops.calc_checksum(hw);
0461     if (status < 0)
0462         goto out;
0463 
0464     checksum = (u16)(status & 0xffff);
0465 
0466     /* Do not use hw->eeprom.ops.write because we do not want to
0467      * take the synchronization semaphores twice here.
0468      */
0469     status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum);
0470     if (status)
0471         goto out;
0472 
0473     status = ixgbe_update_flash_X540(hw);
0474 
0475 out:
0476     hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
0477     return status;
0478 }
0479 
0480 /**
0481  * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device
0482  * @hw: pointer to hardware structure
0483  *
0484  * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy
0485  * EEPROM from shadow RAM to the flash device.
0486  **/
0487 static s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw)
0488 {
0489     u32 flup;
0490     s32 status;
0491 
0492     status = ixgbe_poll_flash_update_done_X540(hw);
0493     if (status == IXGBE_ERR_EEPROM) {
0494         hw_dbg(hw, "Flash update time out\n");
0495         return status;
0496     }
0497 
0498     flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw)) | IXGBE_EEC_FLUP;
0499     IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
0500 
0501     status = ixgbe_poll_flash_update_done_X540(hw);
0502     if (status == 0)
0503         hw_dbg(hw, "Flash update complete\n");
0504     else
0505         hw_dbg(hw, "Flash update time out\n");
0506 
0507     if (hw->revision_id == 0) {
0508         flup = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
0509 
0510         if (flup & IXGBE_EEC_SEC1VAL) {
0511             flup |= IXGBE_EEC_FLUP;
0512             IXGBE_WRITE_REG(hw, IXGBE_EEC(hw), flup);
0513         }
0514 
0515         status = ixgbe_poll_flash_update_done_X540(hw);
0516         if (status == 0)
0517             hw_dbg(hw, "Flash update complete\n");
0518         else
0519             hw_dbg(hw, "Flash update time out\n");
0520     }
0521 
0522     return status;
0523 }
0524 
0525 /**
0526  * ixgbe_poll_flash_update_done_X540 - Poll flash update status
0527  * @hw: pointer to hardware structure
0528  *
0529  * Polls the FLUDONE (bit 26) of the EEC Register to determine when the
0530  * flash update is done.
0531  **/
0532 static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw)
0533 {
0534     u32 i;
0535     u32 reg;
0536 
0537     for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) {
0538         reg = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
0539         if (reg & IXGBE_EEC_FLUDONE)
0540             return 0;
0541         udelay(5);
0542     }
0543     return IXGBE_ERR_EEPROM;
0544 }
0545 
0546 /**
0547  * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore
0548  * @hw: pointer to hardware structure
0549  * @mask: Mask to specify which semaphore to acquire
0550  *
0551  * Acquires the SWFW semaphore thought the SW_FW_SYNC register for
0552  * the specified function (CSR, PHY0, PHY1, NVM, Flash)
0553  **/
0554 s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
0555 {
0556     u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK;
0557     u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK;
0558     u32 fwmask = swmask << 5;
0559     u32 timeout = 200;
0560     u32 hwmask = 0;
0561     u32 swfw_sync;
0562     u32 i;
0563 
0564     if (swmask & IXGBE_GSSR_EEP_SM)
0565         hwmask = IXGBE_GSSR_FLASH_SM;
0566 
0567     /* SW only mask does not have FW bit pair */
0568     if (mask & IXGBE_GSSR_SW_MNG_SM)
0569         swmask |= IXGBE_GSSR_SW_MNG_SM;
0570 
0571     swmask |= swi2c_mask;
0572     fwmask |= swi2c_mask << 2;
0573     for (i = 0; i < timeout; i++) {
0574         /* SW NVM semaphore bit is used for access to all
0575          * SW_FW_SYNC bits (not just NVM)
0576          */
0577         if (ixgbe_get_swfw_sync_semaphore(hw))
0578             return IXGBE_ERR_SWFW_SYNC;
0579 
0580         swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
0581         if (!(swfw_sync & (fwmask | swmask | hwmask))) {
0582             swfw_sync |= swmask;
0583             IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
0584             ixgbe_release_swfw_sync_semaphore(hw);
0585             usleep_range(5000, 6000);
0586             return 0;
0587         }
0588         /* Firmware currently using resource (fwmask), hardware
0589          * currently using resource (hwmask), or other software
0590          * thread currently using resource (swmask)
0591          */
0592         ixgbe_release_swfw_sync_semaphore(hw);
0593         usleep_range(5000, 10000);
0594     }
0595 
0596     /* If the resource is not released by the FW/HW the SW can assume that
0597      * the FW/HW malfunctions. In that case the SW should set the SW bit(s)
0598      * of the requested resource(s) while ignoring the corresponding FW/HW
0599      * bits in the SW_FW_SYNC register.
0600      */
0601     if (ixgbe_get_swfw_sync_semaphore(hw))
0602         return IXGBE_ERR_SWFW_SYNC;
0603     swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
0604     if (swfw_sync & (fwmask | hwmask)) {
0605         swfw_sync |= swmask;
0606         IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
0607         ixgbe_release_swfw_sync_semaphore(hw);
0608         usleep_range(5000, 6000);
0609         return 0;
0610     }
0611     /* If the resource is not released by other SW the SW can assume that
0612      * the other SW malfunctions. In that case the SW should clear all SW
0613      * flags that it does not own and then repeat the whole process once
0614      * again.
0615      */
0616     if (swfw_sync & swmask) {
0617         u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
0618                 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
0619                 IXGBE_GSSR_SW_MNG_SM;
0620 
0621         if (swi2c_mask)
0622             rmask |= IXGBE_GSSR_I2C_MASK;
0623         ixgbe_release_swfw_sync_X540(hw, rmask);
0624         ixgbe_release_swfw_sync_semaphore(hw);
0625         return IXGBE_ERR_SWFW_SYNC;
0626     }
0627     ixgbe_release_swfw_sync_semaphore(hw);
0628 
0629     return IXGBE_ERR_SWFW_SYNC;
0630 }
0631 
0632 /**
0633  * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore
0634  * @hw: pointer to hardware structure
0635  * @mask: Mask to specify which semaphore to release
0636  *
0637  * Releases the SWFW semaphore through the SW_FW_SYNC register
0638  * for the specified function (CSR, PHY0, PHY1, EVM, Flash)
0639  **/
0640 void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask)
0641 {
0642     u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM);
0643     u32 swfw_sync;
0644 
0645     if (mask & IXGBE_GSSR_I2C_MASK)
0646         swmask |= mask & IXGBE_GSSR_I2C_MASK;
0647     ixgbe_get_swfw_sync_semaphore(hw);
0648 
0649     swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
0650     swfw_sync &= ~swmask;
0651     IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swfw_sync);
0652 
0653     ixgbe_release_swfw_sync_semaphore(hw);
0654     usleep_range(5000, 6000);
0655 }
0656 
0657 /**
0658  * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore
0659  * @hw: pointer to hardware structure
0660  *
0661  * Sets the hardware semaphores so SW/FW can gain control of shared resources
0662  */
0663 static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw)
0664 {
0665     u32 timeout = 2000;
0666     u32 i;
0667     u32 swsm;
0668 
0669     /* Get SMBI software semaphore between device drivers first */
0670     for (i = 0; i < timeout; i++) {
0671         /* If the SMBI bit is 0 when we read it, then the bit will be
0672          * set and we have the semaphore
0673          */
0674         swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
0675         if (!(swsm & IXGBE_SWSM_SMBI))
0676             break;
0677         usleep_range(50, 100);
0678     }
0679 
0680     if (i == timeout) {
0681         hw_dbg(hw,
0682                "Software semaphore SMBI between device drivers not granted.\n");
0683         return IXGBE_ERR_EEPROM;
0684     }
0685 
0686     /* Now get the semaphore between SW/FW through the REGSMP bit */
0687     for (i = 0; i < timeout; i++) {
0688         swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
0689         if (!(swsm & IXGBE_SWFW_REGSMP))
0690             return 0;
0691 
0692         usleep_range(50, 100);
0693     }
0694 
0695     /* Release semaphores and return error if SW NVM semaphore
0696      * was not granted because we do not have access to the EEPROM
0697      */
0698     hw_dbg(hw, "REGSMP Software NVM semaphore not granted\n");
0699     ixgbe_release_swfw_sync_semaphore(hw);
0700     return IXGBE_ERR_EEPROM;
0701 }
0702 
0703 /**
0704  * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore
0705  * @hw: pointer to hardware structure
0706  *
0707  * This function clears hardware semaphore bits.
0708  **/
0709 static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw)
0710 {
0711      u32 swsm;
0712 
0713     /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */
0714 
0715     swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC(hw));
0716     swsm &= ~IXGBE_SWFW_REGSMP;
0717     IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC(hw), swsm);
0718 
0719     swsm = IXGBE_READ_REG(hw, IXGBE_SWSM(hw));
0720     swsm &= ~IXGBE_SWSM_SMBI;
0721     IXGBE_WRITE_REG(hw, IXGBE_SWSM(hw), swsm);
0722 
0723     IXGBE_WRITE_FLUSH(hw);
0724 }
0725 
0726 /**
0727  *  ixgbe_init_swfw_sync_X540 - Release hardware semaphore
0728  *  @hw: pointer to hardware structure
0729  *
0730  *  This function reset hardware semaphore bits for a semaphore that may
0731  *  have be left locked due to a catastrophic failure.
0732  **/
0733 void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw)
0734 {
0735     u32 rmask;
0736 
0737     /* First try to grab the semaphore but we don't need to bother
0738      * looking to see whether we got the lock or not since we do
0739      * the same thing regardless of whether we got the lock or not.
0740      * We got the lock - we release it.
0741      * We timeout trying to get the lock - we force its release.
0742      */
0743     ixgbe_get_swfw_sync_semaphore(hw);
0744     ixgbe_release_swfw_sync_semaphore(hw);
0745 
0746     /* Acquire and release all software resources. */
0747     rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM |
0748         IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM |
0749         IXGBE_GSSR_SW_MNG_SM | IXGBE_GSSR_I2C_MASK;
0750 
0751     ixgbe_acquire_swfw_sync_X540(hw, rmask);
0752     ixgbe_release_swfw_sync_X540(hw, rmask);
0753 }
0754 
0755 /**
0756  * ixgbe_blink_led_start_X540 - Blink LED based on index.
0757  * @hw: pointer to hardware structure
0758  * @index: led number to blink
0759  *
0760  * Devices that implement the version 2 interface:
0761  *   X540
0762  **/
0763 s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index)
0764 {
0765     u32 macc_reg;
0766     u32 ledctl_reg;
0767     ixgbe_link_speed speed;
0768     bool link_up;
0769 
0770     if (index > 3)
0771         return IXGBE_ERR_PARAM;
0772 
0773     /* Link should be up in order for the blink bit in the LED control
0774      * register to work. Force link and speed in the MAC if link is down.
0775      * This will be reversed when we stop the blinking.
0776      */
0777     hw->mac.ops.check_link(hw, &speed, &link_up, false);
0778     if (!link_up) {
0779         macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
0780         macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS;
0781         IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
0782     }
0783     /* Set the LED to LINK_UP + BLINK. */
0784     ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
0785     ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
0786     ledctl_reg |= IXGBE_LED_BLINK(index);
0787     IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
0788     IXGBE_WRITE_FLUSH(hw);
0789 
0790     return 0;
0791 }
0792 
0793 /**
0794  * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index.
0795  * @hw: pointer to hardware structure
0796  * @index: led number to stop blinking
0797  *
0798  * Devices that implement the version 2 interface:
0799  *   X540
0800  **/
0801 s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index)
0802 {
0803     u32 macc_reg;
0804     u32 ledctl_reg;
0805 
0806     if (index > 3)
0807         return IXGBE_ERR_PARAM;
0808 
0809     /* Restore the LED to its default value. */
0810     ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
0811     ledctl_reg &= ~IXGBE_LED_MODE_MASK(index);
0812     ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
0813     ledctl_reg &= ~IXGBE_LED_BLINK(index);
0814     IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg);
0815 
0816     /* Unforce link and speed in the MAC. */
0817     macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC);
0818     macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS);
0819     IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg);
0820     IXGBE_WRITE_FLUSH(hw);
0821 
0822     return 0;
0823 }
0824 static const struct ixgbe_mac_operations mac_ops_X540 = {
0825     .init_hw                = &ixgbe_init_hw_generic,
0826     .reset_hw               = &ixgbe_reset_hw_X540,
0827     .start_hw               = &ixgbe_start_hw_X540,
0828     .clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
0829     .get_media_type         = &ixgbe_get_media_type_X540,
0830     .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
0831     .get_mac_addr           = &ixgbe_get_mac_addr_generic,
0832     .get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
0833     .get_device_caps        = &ixgbe_get_device_caps_generic,
0834     .get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
0835     .stop_adapter           = &ixgbe_stop_adapter_generic,
0836     .get_bus_info           = &ixgbe_get_bus_info_generic,
0837     .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
0838     .read_analog_reg8       = NULL,
0839     .write_analog_reg8      = NULL,
0840     .setup_link             = &ixgbe_setup_mac_link_X540,
0841     .set_rxpba      = &ixgbe_set_rxpba_generic,
0842     .check_link             = &ixgbe_check_mac_link_generic,
0843     .get_link_capabilities  = &ixgbe_get_copper_link_capabilities_generic,
0844     .led_on                 = &ixgbe_led_on_generic,
0845     .led_off                = &ixgbe_led_off_generic,
0846     .init_led_link_act  = ixgbe_init_led_link_act_generic,
0847     .blink_led_start        = &ixgbe_blink_led_start_X540,
0848     .blink_led_stop         = &ixgbe_blink_led_stop_X540,
0849     .set_rar                = &ixgbe_set_rar_generic,
0850     .clear_rar              = &ixgbe_clear_rar_generic,
0851     .set_vmdq               = &ixgbe_set_vmdq_generic,
0852     .set_vmdq_san_mac   = &ixgbe_set_vmdq_san_mac_generic,
0853     .clear_vmdq             = &ixgbe_clear_vmdq_generic,
0854     .init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
0855     .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
0856     .enable_mc              = &ixgbe_enable_mc_generic,
0857     .disable_mc             = &ixgbe_disable_mc_generic,
0858     .clear_vfta             = &ixgbe_clear_vfta_generic,
0859     .set_vfta               = &ixgbe_set_vfta_generic,
0860     .fc_enable              = &ixgbe_fc_enable_generic,
0861     .setup_fc       = ixgbe_setup_fc_generic,
0862     .fc_autoneg     = ixgbe_fc_autoneg,
0863     .set_fw_drv_ver         = &ixgbe_set_fw_drv_ver_generic,
0864     .init_uta_tables        = &ixgbe_init_uta_tables_generic,
0865     .setup_sfp              = NULL,
0866     .set_mac_anti_spoofing  = &ixgbe_set_mac_anti_spoofing,
0867     .set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
0868     .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync_X540,
0869     .release_swfw_sync      = &ixgbe_release_swfw_sync_X540,
0870     .init_swfw_sync     = &ixgbe_init_swfw_sync_X540,
0871     .disable_rx_buff    = &ixgbe_disable_rx_buff_generic,
0872     .enable_rx_buff     = &ixgbe_enable_rx_buff_generic,
0873     .get_thermal_sensor_data = NULL,
0874     .init_thermal_sensor_thresh = NULL,
0875     .prot_autoc_read    = &prot_autoc_read_generic,
0876     .prot_autoc_write   = &prot_autoc_write_generic,
0877     .enable_rx      = &ixgbe_enable_rx_generic,
0878     .disable_rx     = &ixgbe_disable_rx_generic,
0879 };
0880 
0881 static const struct ixgbe_eeprom_operations eeprom_ops_X540 = {
0882     .init_params            = &ixgbe_init_eeprom_params_X540,
0883     .read                   = &ixgbe_read_eerd_X540,
0884     .read_buffer        = &ixgbe_read_eerd_buffer_X540,
0885     .write                  = &ixgbe_write_eewr_X540,
0886     .write_buffer       = &ixgbe_write_eewr_buffer_X540,
0887     .calc_checksum      = &ixgbe_calc_eeprom_checksum_X540,
0888     .validate_checksum      = &ixgbe_validate_eeprom_checksum_X540,
0889     .update_checksum        = &ixgbe_update_eeprom_checksum_X540,
0890 };
0891 
0892 static const struct ixgbe_phy_operations phy_ops_X540 = {
0893     .identify               = &ixgbe_identify_phy_generic,
0894     .identify_sfp           = &ixgbe_identify_sfp_module_generic,
0895     .init           = NULL,
0896     .reset                  = NULL,
0897     .read_reg               = &ixgbe_read_phy_reg_generic,
0898     .write_reg              = &ixgbe_write_phy_reg_generic,
0899     .setup_link             = &ixgbe_setup_phy_link_generic,
0900     .setup_link_speed       = &ixgbe_setup_phy_link_speed_generic,
0901     .read_i2c_byte          = &ixgbe_read_i2c_byte_generic,
0902     .write_i2c_byte         = &ixgbe_write_i2c_byte_generic,
0903     .read_i2c_sff8472   = &ixgbe_read_i2c_sff8472_generic,
0904     .read_i2c_eeprom        = &ixgbe_read_i2c_eeprom_generic,
0905     .write_i2c_eeprom       = &ixgbe_write_i2c_eeprom_generic,
0906     .check_overtemp         = &ixgbe_tn_check_overtemp,
0907     .set_phy_power          = &ixgbe_set_copper_phy_power,
0908 };
0909 
0910 static const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = {
0911     IXGBE_MVALS_INIT(X540)
0912 };
0913 
0914 const struct ixgbe_info ixgbe_X540_info = {
0915     .mac                    = ixgbe_mac_X540,
0916     .get_invariants         = &ixgbe_get_invariants_X540,
0917     .mac_ops                = &mac_ops_X540,
0918     .eeprom_ops             = &eeprom_ops_X540,
0919     .phy_ops                = &phy_ops_X540,
0920     .mbx_ops                = &mbx_ops_generic,
0921     .mvals          = ixgbe_mvals_X540,
0922 };
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