intel/ixgbe/ixgbe_ptp.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #include "ixgbe.h"
0005 #include <linux/ptp_classify.h>
0006 #include <linux/clocksource.h>
0007
0008 /*
0009  * The 82599 and the X540 do not have true 64bit nanosecond scale
0010  * counter registers. Instead, SYSTIME is defined by a fixed point
0011  * system which allows the user to define the scale counter increment
0012  * value at every level change of the oscillator driving the SYSTIME
0013  * value. For both devices the TIMINCA:IV field defines this
0014  * increment. On the X540 device, 31 bits are provided. However on the
0015  * 82599 only provides 24 bits. The time unit is determined by the
0016  * clock frequency of the oscillator in combination with the TIMINCA
0017  * register. When these devices link at 10Gb the oscillator has a
0018  * period of 6.4ns. In order to convert the scale counter into
0019  * nanoseconds the cyclecounter and timecounter structures are
0020  * used. The SYSTIME registers need to be converted to ns values by use
0021  * of only a right shift (division by power of 2). The following math
0022  * determines the largest incvalue that will fit into the available
0023  * bits in the TIMINCA register.
0024  *
0025  * PeriodWidth: Number of bits to store the clock period
0026  * MaxWidth: The maximum width value of the TIMINCA register
0027  * Period: The clock period for the oscillator
0028  * round(): discard the fractional portion of the calculation
0029  *
0030  * Period * [ 2 ^ ( MaxWidth - PeriodWidth ) ]
0031  *
0032  * For the X540, MaxWidth is 31 bits, and the base period is 6.4 ns
0033  * For the 82599, MaxWidth is 24 bits, and the base period is 6.4 ns
0034  *
0035  * The period also changes based on the link speed:
0036  * At 10Gb link or no link, the period remains the same.
0037  * At 1Gb link, the period is multiplied by 10. (64ns)
0038  * At 100Mb link, the period is multiplied by 100. (640ns)
0039  *
0040  * The calculated value allows us to right shift the SYSTIME register
0041  * value in order to quickly convert it into a nanosecond clock,
0042  * while allowing for the maximum possible adjustment value.
0043  *
0044  * These diagrams are only for the 10Gb link period
0045  *
0046  *           SYSTIMEH            SYSTIMEL
0047  *       +--------------+  +--------------+
0048  * X540  |      32      |  | 1 | 3 |  28  |
0049  *       *--------------+  +--------------+
0050  *        \________ 36 bits ______/  fract
0051  *
0052  *       +--------------+  +--------------+
0053  * 82599 |      32      |  | 8 | 3 |  21  |
0054  *       *--------------+  +--------------+
0055  *        \________ 43 bits ______/  fract
0056  *
0057  * The 36 bit X540 SYSTIME overflows every
0058  *   2^36 * 10^-9 / 60 = 1.14 minutes or 69 seconds
0059  *
0060  * The 43 bit 82599 SYSTIME overflows every
0061  *   2^43 * 10^-9 / 3600 = 2.4 hours
0062  */
0063 #define IXGBE_INCVAL_10GB 0x66666666
0064 #define IXGBE_INCVAL_1GB  0x40000000
0065 #define IXGBE_INCVAL_100  0x50000000
0066
0067 #define IXGBE_INCVAL_SHIFT_10GB  28
0068 #define IXGBE_INCVAL_SHIFT_1GB   24
0069 #define IXGBE_INCVAL_SHIFT_100   21
0070
0071 #define IXGBE_INCVAL_SHIFT_82599 7
0072 #define IXGBE_INCPER_SHIFT_82599 24
0073
0074 #define IXGBE_OVERFLOW_PERIOD    (HZ * 30)
0075 #define IXGBE_PTP_TX_TIMEOUT     (HZ)
0076
0077 /* We use our own definitions instead of NSEC_PER_SEC because we want to mark
0078  * the value as a ULL to force precision when bit shifting.
0079  */
0080 #define NS_PER_SEC      1000000000ULL
0081 #define NS_PER_HALF_SEC  500000000ULL
0082
0083 /* In contrast, the X550 controller has two registers, SYSTIMEH and SYSTIMEL
0084  * which contain measurements of seconds and nanoseconds respectively. This
0085  * matches the standard linux representation of time in the kernel. In addition,
0086  * the X550 also has a SYSTIMER register which represents residue, or
0087  * subnanosecond overflow adjustments. To control clock adjustment, the TIMINCA
0088  * register is used, but it is unlike the X540 and 82599 devices. TIMINCA
0089  * represents units of 2^-32 nanoseconds, and uses 31 bits for this, with the
0090  * high bit representing whether the adjustent is positive or negative. Every
0091  * clock cycle, the X550 will add 12.5 ns + TIMINCA which can result in a range
0092  * of 12 to 13 nanoseconds adjustment. Unlike the 82599 and X540 devices, the
0093  * X550's clock for purposes of SYSTIME generation is constant and not dependent
0094  * on the link speed.
0095  *
0096  *           SYSTIMEH           SYSTIMEL        SYSTIMER
0097  *       +--------------+  +--------------+  +-------------+
0098  * X550  |      32      |  |      32      |  |     32      |
0099  *       *--------------+  +--------------+  +-------------+
0100  *       \____seconds___/   \_nanoseconds_/  \__2^-32 ns__/
0101  *
0102  * This results in a full 96 bits to represent the clock, with 32 bits for
0103  * seconds, 32 bits for nanoseconds (largest value is 0d999999999 or just under
0104  * 1 second) and an additional 32 bits to measure sub nanosecond adjustments for
0105  * underflow of adjustments.
0106  *
0107  * The 32 bits of seconds for the X550 overflows every
0108  *   2^32 / ( 365.25 * 24 * 60 * 60 ) = ~136 years.
0109  *
0110  * In order to adjust the clock frequency for the X550, the TIMINCA register is
0111  * provided. This register represents a + or minus nearly 0.5 ns adjustment to
0112  * the base frequency. It is measured in 2^-32 ns units, with the high bit being
0113  * the sign bit. This register enables software to calculate frequency
0114  * adjustments and apply them directly to the clock rate.
0115  *
0116  * The math for converting scaled_ppm into TIMINCA values is fairly
0117  * straightforward.
0118  *
0119  *   TIMINCA value = ( Base_Frequency * scaled_ppm ) / 1000000ULL << 16
0120  *
0121  * To avoid overflow, we simply use mul_u64_u64_div_u64.
0122  *
0123  * This assumes that scaled_ppm is never high enough to create a value bigger
0124  * than TIMINCA's 31 bits can store. This is ensured by the stack, and is
0125  * measured in parts per billion. Calculating this value is also simple.
0126  *   Max ppb = ( Max Adjustment / Base Frequency ) / 1000000000ULL
0127  *
0128  * For the X550, the Max adjustment is +/- 0.5 ns, and the base frequency is
0129  * 12.5 nanoseconds. This means that the Max ppb is 39999999
0130  *   Note: We subtract one in order to ensure no overflow, because the TIMINCA
0131  *         register can only hold slightly under 0.5 nanoseconds.
0132  *
0133  * Because TIMINCA is measured in 2^-32 ns units, we have to convert 12.5 ns
0134  * into 2^-32 units, which is
0135  *
0136  *  12.5 * 2^32 = C80000000
0137  *
0138  * Some revisions of hardware have a faster base frequency than the registers
0139  * were defined for. To fix this, we use a timecounter structure with the
0140  * proper mult and shift to convert the cycles into nanoseconds of time.
0141  */
0142 #define IXGBE_X550_BASE_PERIOD 0xC80000000ULL
0143 #define INCVALUE_MASK   0x7FFFFFFF
0144 #define ISGN        0x80000000
0145
0146 /**
0147  * ixgbe_ptp_setup_sdp_X540
0148  * @adapter: private adapter structure
0149  *
0150  * this function enables or disables the clock out feature on SDP0 for
0151  * the X540 device. It will create a 1 second periodic output that can
0152  * be used as the PPS (via an interrupt).
0153  *
0154  * It calculates when the system time will be on an exact second, and then
0155  * aligns the start of the PPS signal to that value.
0156  *
0157  * This works by using the cycle counter shift and mult values in reverse, and
0158  * assumes that the values we're shifting will not overflow.
0159  */
0160 static void ixgbe_ptp_setup_sdp_X540(struct ixgbe_adapter *adapter)
0161 {
0162     struct cyclecounter *cc = &adapter->hw_cc;
0163     struct ixgbe_hw *hw = &adapter->hw;
0164     u32 esdp, tsauxc, clktiml, clktimh, trgttiml, trgttimh, rem;
0165     u64 ns = 0, clock_edge = 0, clock_period;
0166     unsigned long flags;
0167
0168     /* disable the pin first */
0169     IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
0170     IXGBE_WRITE_FLUSH(hw);
0171
0172     if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
0173         return;
0174
0175     esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
0176
0177     /* enable the SDP0 pin as output, and connected to the
0178      * native function for Timesync (ClockOut)
0179      */
0180     esdp |= IXGBE_ESDP_SDP0_DIR |
0181         IXGBE_ESDP_SDP0_NATIVE;
0182
0183     /* enable the Clock Out feature on SDP0, and allow
0184      * interrupts to occur when the pin changes
0185      */
0186     tsauxc = (IXGBE_TSAUXC_EN_CLK |
0187           IXGBE_TSAUXC_SYNCLK |
0188           IXGBE_TSAUXC_SDP0_INT);
0189
0190     /* Determine the clock time period to use. This assumes that the
0191      * cycle counter shift is small enough to avoid overflow.
0192      */
0193     clock_period = div_u64((NS_PER_HALF_SEC << cc->shift), cc->mult);
0194     clktiml = (u32)(clock_period);
0195     clktimh = (u32)(clock_period >> 32);
0196
0197     /* Read the current clock time, and save the cycle counter value */
0198     spin_lock_irqsave(&adapter->tmreg_lock, flags);
0199     ns = timecounter_read(&adapter->hw_tc);
0200     clock_edge = adapter->hw_tc.cycle_last;
0201     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
0202
0203     /* Figure out how many seconds to add in order to round up */
0204     div_u64_rem(ns, NS_PER_SEC, &rem);
0205
0206     /* Figure out how many nanoseconds to add to round the clock edge up
0207      * to the next full second
0208      */
0209     rem = (NS_PER_SEC - rem);
0210
0211     /* Adjust the clock edge to align with the next full second. */
0212     clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
0213     trgttiml = (u32)clock_edge;
0214     trgttimh = (u32)(clock_edge >> 32);
0215
0216     IXGBE_WRITE_REG(hw, IXGBE_CLKTIML, clktiml);
0217     IXGBE_WRITE_REG(hw, IXGBE_CLKTIMH, clktimh);
0218     IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
0219     IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
0220
0221     IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
0222     IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
0223
0224     IXGBE_WRITE_FLUSH(hw);
0225 }
0226
0227 /**
0228  * ixgbe_ptp_setup_sdp_X550
0229  * @adapter: private adapter structure
0230  *
0231  * Enable or disable a clock output signal on SDP 0 for X550 hardware.
0232  *
0233  * Use the target time feature to align the output signal on the next full
0234  * second.
0235  *
0236  * This works by using the cycle counter shift and mult values in reverse, and
0237  * assumes that the values we're shifting will not overflow.
0238  */
0239 static void ixgbe_ptp_setup_sdp_X550(struct ixgbe_adapter *adapter)
0240 {
0241     u32 esdp, tsauxc, freqout, trgttiml, trgttimh, rem, tssdp;
0242     struct cyclecounter *cc = &adapter->hw_cc;
0243     struct ixgbe_hw *hw = &adapter->hw;
0244     u64 ns = 0, clock_edge = 0;
0245     struct timespec64 ts;
0246     unsigned long flags;
0247
0248     /* disable the pin first */
0249     IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, 0x0);
0250     IXGBE_WRITE_FLUSH(hw);
0251
0252     if (!(adapter->flags2 & IXGBE_FLAG2_PTP_PPS_ENABLED))
0253         return;
0254
0255     esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
0256
0257     /* enable the SDP0 pin as output, and connected to the
0258      * native function for Timesync (ClockOut)
0259      */
0260     esdp |= IXGBE_ESDP_SDP0_DIR |
0261         IXGBE_ESDP_SDP0_NATIVE;
0262
0263     /* enable the Clock Out feature on SDP0, and use Target Time 0 to
0264      * enable generation of interrupts on the clock change.
0265      */
0266 #define IXGBE_TSAUXC_DIS_TS_CLEAR 0x40000000
0267     tsauxc = (IXGBE_TSAUXC_EN_CLK | IXGBE_TSAUXC_ST0 |
0268           IXGBE_TSAUXC_EN_TT0 | IXGBE_TSAUXC_SDP0_INT |
0269           IXGBE_TSAUXC_DIS_TS_CLEAR);
0270
0271     tssdp = (IXGBE_TSSDP_TS_SDP0_EN |
0272          IXGBE_TSSDP_TS_SDP0_CLK0);
0273
0274     /* Determine the clock time period to use. This assumes that the
0275      * cycle counter shift is small enough to avoid overflowing a 32bit
0276      * value.
0277      */
0278     freqout = div_u64(NS_PER_HALF_SEC << cc->shift,  cc->mult);
0279
0280     /* Read the current clock time, and save the cycle counter value */
0281     spin_lock_irqsave(&adapter->tmreg_lock, flags);
0282     ns = timecounter_read(&adapter->hw_tc);
0283     clock_edge = adapter->hw_tc.cycle_last;
0284     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
0285
0286     /* Figure out how far past the next second we are */
0287     div_u64_rem(ns, NS_PER_SEC, &rem);
0288
0289     /* Figure out how many nanoseconds to add to round the clock edge up
0290      * to the next full second
0291      */
0292     rem = (NS_PER_SEC - rem);
0293
0294     /* Adjust the clock edge to align with the next full second. */
0295     clock_edge += div_u64(((u64)rem << cc->shift), cc->mult);
0296
0297     /* X550 hardware stores the time in 32bits of 'billions of cycles' and
0298      * 32bits of 'cycles'. There's no guarantee that cycles represents
0299      * nanoseconds. However, we can use the math from a timespec64 to
0300      * convert into the hardware representation.
0301      *
0302      * See ixgbe_ptp_read_X550() for more details.
0303      */
0304     ts = ns_to_timespec64(clock_edge);
0305     trgttiml = (u32)ts.tv_nsec;
0306     trgttimh = (u32)ts.tv_sec;
0307
0308     IXGBE_WRITE_REG(hw, IXGBE_FREQOUT0, freqout);
0309     IXGBE_WRITE_REG(hw, IXGBE_TRGTTIML0, trgttiml);
0310     IXGBE_WRITE_REG(hw, IXGBE_TRGTTIMH0, trgttimh);
0311
0312     IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
0313     IXGBE_WRITE_REG(hw, IXGBE_TSSDP, tssdp);
0314     IXGBE_WRITE_REG(hw, IXGBE_TSAUXC, tsauxc);
0315
0316     IXGBE_WRITE_FLUSH(hw);
0317 }
0318
0319 /**
0320  * ixgbe_ptp_read_X550 - read cycle counter value
0321  * @cc: cyclecounter structure
0322  *
0323  * This function reads SYSTIME registers. It is called by the cyclecounter
0324  * structure to convert from internal representation into nanoseconds. We need
0325  * this for X550 since some skews do not have expected clock frequency and
0326  * result of SYSTIME is 32bits of "billions of cycles" and 32 bits of
0327  * "cycles", rather than seconds and nanoseconds.
0328  */
0329 static u64 ixgbe_ptp_read_X550(const struct cyclecounter *cc)
0330 {
0331     struct ixgbe_adapter *adapter =
0332         container_of(cc, struct ixgbe_adapter, hw_cc);
0333     struct ixgbe_hw *hw = &adapter->hw;
0334     struct timespec64 ts;
0335
0336     /* storage is 32 bits of 'billions of cycles' and 32 bits of 'cycles'.
0337      * Some revisions of hardware run at a higher frequency and so the
0338      * cycles are not guaranteed to be nanoseconds. The timespec64 created
0339      * here is used for its math/conversions but does not necessarily
0340      * represent nominal time.
0341      *
0342      * It should be noted that this cyclecounter will overflow at a
0343      * non-bitmask field since we have to convert our billions of cycles
0344      * into an actual cycles count. This results in some possible weird
0345      * situations at high cycle counter stamps. However given that 32 bits
0346      * of "seconds" is ~138 years this isn't a problem. Even at the
0347      * increased frequency of some revisions, this is still ~103 years.
0348      * Since the SYSTIME values start at 0 and we never write them, it is
0349      * highly unlikely for the cyclecounter to overflow in practice.
0350      */
0351     IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
0352     ts.tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
0353     ts.tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
0354
0355     return (u64)timespec64_to_ns(&ts);
0356 }
0357
0358 /**
0359  * ixgbe_ptp_read_82599 - read raw cycle counter (to be used by time counter)
0360  * @cc: the cyclecounter structure
0361  *
0362  * this function reads the cyclecounter registers and is called by the
0363  * cyclecounter structure used to construct a ns counter from the
0364  * arbitrary fixed point registers
0365  */
0366 static u64 ixgbe_ptp_read_82599(const struct cyclecounter *cc)
0367 {
0368     struct ixgbe_adapter *adapter =
0369         container_of(cc, struct ixgbe_adapter, hw_cc);
0370     struct ixgbe_hw *hw = &adapter->hw;
0371     u64 stamp = 0;
0372
0373     stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIML);
0374     stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
0375
0376     return stamp;
0377 }
0378
0379 /**
0380  * ixgbe_ptp_convert_to_hwtstamp - convert register value to hw timestamp
0381  * @adapter: private adapter structure
0382  * @hwtstamp: stack timestamp structure
0383  * @timestamp: unsigned 64bit system time value
0384  *
0385  * We need to convert the adapter's RX/TXSTMP registers into a hwtstamp value
0386  * which can be used by the stack's ptp functions.
0387  *
0388  * The lock is used to protect consistency of the cyclecounter and the SYSTIME
0389  * registers. However, it does not need to protect against the Rx or Tx
0390  * timestamp registers, as there can't be a new timestamp until the old one is
0391  * unlatched by reading.
0392  *
0393  * In addition to the timestamp in hardware, some controllers need a software
0394  * overflow cyclecounter, and this function takes this into account as well.
0395  **/
0396 static void ixgbe_ptp_convert_to_hwtstamp(struct ixgbe_adapter *adapter,
0397                       struct skb_shared_hwtstamps *hwtstamp,
0398                       u64 timestamp)
0399 {
0400     unsigned long flags;
0401     struct timespec64 systime;
0402     u64 ns;
0403
0404     memset(hwtstamp, 0, sizeof(*hwtstamp));
0405
0406     switch (adapter->hw.mac.type) {
0407     /* X550 and later hardware supposedly represent time using a seconds
0408      * and nanoseconds counter, instead of raw 64bits nanoseconds. We need
0409      * to convert the timestamp into cycles before it can be fed to the
0410      * cyclecounter. We need an actual cyclecounter because some revisions
0411      * of hardware run at a higher frequency and thus the counter does
0412      * not represent seconds/nanoseconds. Instead it can be thought of as
0413      * cycles and billions of cycles.
0414      */
0415     case ixgbe_mac_X550:
0416     case ixgbe_mac_X550EM_x:
0417     case ixgbe_mac_x550em_a:
0418         /* Upper 32 bits represent billions of cycles, lower 32 bits
0419          * represent cycles. However, we use timespec64_to_ns for the
0420          * correct math even though the units haven't been corrected
0421          * yet.
0422          */
0423         systime.tv_sec = timestamp >> 32;
0424         systime.tv_nsec = timestamp & 0xFFFFFFFF;
0425
0426         timestamp = timespec64_to_ns(&systime);
0427         break;
0428     default:
0429         break;
0430     }
0431
0432     spin_lock_irqsave(&adapter->tmreg_lock, flags);
0433     ns = timecounter_cyc2time(&adapter->hw_tc, timestamp);
0434     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
0435
0436     hwtstamp->hwtstamp = ns_to_ktime(ns);
0437 }
0438
0439 /**
0440  * ixgbe_ptp_adjfine_82599
0441  * @ptp: the ptp clock structure
0442  * @scaled_ppm: scaled parts per million adjustment from base
0443  *
0444  * Adjust the frequency of the ptp cycle counter by the
0445  * indicated scaled_ppm from the base frequency.
0446  *
0447  * Scaled parts per million is ppm with a 16-bit binary fractional field.
0448  */
0449 static int ixgbe_ptp_adjfine_82599(struct ptp_clock_info *ptp, long scaled_ppm)
0450 {
0451     struct ixgbe_adapter *adapter =
0452         container_of(ptp, struct ixgbe_adapter, ptp_caps);
0453     struct ixgbe_hw *hw = &adapter->hw;
0454     u64 incval, diff;
0455     int neg_adj = 0;
0456
0457     if (scaled_ppm < 0) {
0458         neg_adj = 1;
0459         scaled_ppm = -scaled_ppm;
0460     }
0461
0462     smp_mb();
0463     incval = READ_ONCE(adapter->base_incval);
0464
0465     diff = mul_u64_u64_div_u64(incval, scaled_ppm,
0466                    1000000ULL << 16);
0467
0468     incval = neg_adj ? (incval - diff) : (incval + diff);
0469
0470     switch (hw->mac.type) {
0471     case ixgbe_mac_X540:
0472         if (incval > 0xFFFFFFFFULL)
0473             e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
0474         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, (u32)incval);
0475         break;
0476     case ixgbe_mac_82599EB:
0477         if (incval > 0x00FFFFFFULL)
0478             e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
0479         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
0480                 BIT(IXGBE_INCPER_SHIFT_82599) |
0481                 ((u32)incval & 0x00FFFFFFUL));
0482         break;
0483     default:
0484         break;
0485     }
0486
0487     return 0;
0488 }
0489
0490 /**
0491  * ixgbe_ptp_adjfine_X550
0492  * @ptp: the ptp clock structure
0493  * @scaled_ppm: scaled parts per million adjustment from base
0494  *
0495  * Adjust the frequency of the SYSTIME registers by the indicated scaled_ppm
0496  * from base frequency.
0497  *
0498  * Scaled parts per million is ppm with a 16-bit binary fractional field.
0499  */
0500 static int ixgbe_ptp_adjfine_X550(struct ptp_clock_info *ptp, long scaled_ppm)
0501 {
0502     struct ixgbe_adapter *adapter =
0503             container_of(ptp, struct ixgbe_adapter, ptp_caps);
0504     struct ixgbe_hw *hw = &adapter->hw;
0505     int neg_adj = 0;
0506     u64 rate;
0507     u32 inca;
0508
0509     if (scaled_ppm < 0) {
0510         neg_adj = 1;
0511         scaled_ppm = -scaled_ppm;
0512     }
0513
0514     rate = mul_u64_u64_div_u64(IXGBE_X550_BASE_PERIOD, scaled_ppm,
0515                    1000000ULL << 16);
0516
0517     /* warn if rate is too large */
0518     if (rate >= INCVALUE_MASK)
0519         e_dev_warn("PTP scaled_ppm adjusted SYSTIME rate overflowed!\n");
0520
0521     inca = rate & INCVALUE_MASK;
0522     if (neg_adj)
0523         inca |= ISGN;
0524
0525     IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, inca);
0526
0527     return 0;
0528 }
0529
0530 /**
0531  * ixgbe_ptp_adjtime
0532  * @ptp: the ptp clock structure
0533  * @delta: offset to adjust the cycle counter by
0534  *
0535  * adjust the timer by resetting the timecounter structure.
0536  */
0537 static int ixgbe_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
0538 {
0539     struct ixgbe_adapter *adapter =
0540         container_of(ptp, struct ixgbe_adapter, ptp_caps);
0541     unsigned long flags;
0542
0543     spin_lock_irqsave(&adapter->tmreg_lock, flags);
0544     timecounter_adjtime(&adapter->hw_tc, delta);
0545     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
0546
0547     if (adapter->ptp_setup_sdp)
0548         adapter->ptp_setup_sdp(adapter);
0549
0550     return 0;
0551 }
0552
0553 /**
0554  * ixgbe_ptp_gettimex
0555  * @ptp: the ptp clock structure
0556  * @ts: timespec to hold the PHC timestamp
0557  * @sts: structure to hold the system time before and after reading the PHC
0558  *
0559  * read the timecounter and return the correct value on ns,
0560  * after converting it into a struct timespec.
0561  */
0562 static int ixgbe_ptp_gettimex(struct ptp_clock_info *ptp,
0563                   struct timespec64 *ts,
0564                   struct ptp_system_timestamp *sts)
0565 {
0566     struct ixgbe_adapter *adapter =
0567         container_of(ptp, struct ixgbe_adapter, ptp_caps);
0568     struct ixgbe_hw *hw = &adapter->hw;
0569     unsigned long flags;
0570     u64 ns, stamp;
0571
0572     spin_lock_irqsave(&adapter->tmreg_lock, flags);
0573
0574     switch (adapter->hw.mac.type) {
0575     case ixgbe_mac_X550:
0576     case ixgbe_mac_X550EM_x:
0577     case ixgbe_mac_x550em_a:
0578         /* Upper 32 bits represent billions of cycles, lower 32 bits
0579          * represent cycles. However, we use timespec64_to_ns for the
0580          * correct math even though the units haven't been corrected
0581          * yet.
0582          */
0583         ptp_read_system_prets(sts);
0584         IXGBE_READ_REG(hw, IXGBE_SYSTIMR);
0585         ptp_read_system_postts(sts);
0586         ts->tv_nsec = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
0587         ts->tv_sec = IXGBE_READ_REG(hw, IXGBE_SYSTIMH);
0588         stamp = timespec64_to_ns(ts);
0589         break;
0590     default:
0591         ptp_read_system_prets(sts);
0592         stamp = IXGBE_READ_REG(hw, IXGBE_SYSTIML);
0593         ptp_read_system_postts(sts);
0594         stamp |= (u64)IXGBE_READ_REG(hw, IXGBE_SYSTIMH) << 32;
0595         break;
0596     }
0597
0598     ns = timecounter_cyc2time(&adapter->hw_tc, stamp);
0599
0600     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
0601
0602     *ts = ns_to_timespec64(ns);
0603
0604     return 0;
0605 }
0606
0607 /**
0608  * ixgbe_ptp_settime
0609  * @ptp: the ptp clock structure
0610  * @ts: the timespec containing the new time for the cycle counter
0611  *
0612  * reset the timecounter to use a new base value instead of the kernel
0613  * wall timer value.
0614  */
0615 static int ixgbe_ptp_settime(struct ptp_clock_info *ptp,
0616                  const struct timespec64 *ts)
0617 {
0618     struct ixgbe_adapter *adapter =
0619         container_of(ptp, struct ixgbe_adapter, ptp_caps);
0620     unsigned long flags;
0621     u64 ns = timespec64_to_ns(ts);
0622
0623     /* reset the timecounter */
0624     spin_lock_irqsave(&adapter->tmreg_lock, flags);
0625     timecounter_init(&adapter->hw_tc, &adapter->hw_cc, ns);
0626     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
0627
0628     if (adapter->ptp_setup_sdp)
0629         adapter->ptp_setup_sdp(adapter);
0630     return 0;
0631 }
0632
0633 /**
0634  * ixgbe_ptp_feature_enable
0635  * @ptp: the ptp clock structure
0636  * @rq: the requested feature to change
0637  * @on: whether to enable or disable the feature
0638  *
0639  * enable (or disable) ancillary features of the phc subsystem.
0640  * our driver only supports the PPS feature on the X540
0641  */
0642 static int ixgbe_ptp_feature_enable(struct ptp_clock_info *ptp,
0643                     struct ptp_clock_request *rq, int on)
0644 {
0645     struct ixgbe_adapter *adapter =
0646         container_of(ptp, struct ixgbe_adapter, ptp_caps);
0647
0648     /**
0649      * When PPS is enabled, unmask the interrupt for the ClockOut
0650      * feature, so that the interrupt handler can send the PPS
0651      * event when the clock SDP triggers. Clear mask when PPS is
0652      * disabled
0653      */
0654     if (rq->type != PTP_CLK_REQ_PPS || !adapter->ptp_setup_sdp)
0655         return -ENOTSUPP;
0656
0657     if (on)
0658         adapter->flags2 |= IXGBE_FLAG2_PTP_PPS_ENABLED;
0659     else
0660         adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
0661
0662     adapter->ptp_setup_sdp(adapter);
0663     return 0;
0664 }
0665
0666 /**
0667  * ixgbe_ptp_check_pps_event
0668  * @adapter: the private adapter structure
0669  *
0670  * This function is called by the interrupt routine when checking for
0671  * interrupts. It will check and handle a pps event.
0672  */
0673 void ixgbe_ptp_check_pps_event(struct ixgbe_adapter *adapter)
0674 {
0675     struct ixgbe_hw *hw = &adapter->hw;
0676     struct ptp_clock_event event;
0677
0678     event.type = PTP_CLOCK_PPS;
0679
0680     /* this check is necessary in case the interrupt was enabled via some
0681      * alternative means (ex. debug_fs). Better to check here than
0682      * everywhere that calls this function.
0683      */
0684     if (!adapter->ptp_clock)
0685         return;
0686
0687     switch (hw->mac.type) {
0688     case ixgbe_mac_X540:
0689         ptp_clock_event(adapter->ptp_clock, &event);
0690         break;
0691     default:
0692         break;
0693     }
0694 }
0695
0696 /**
0697  * ixgbe_ptp_overflow_check - watchdog task to detect SYSTIME overflow
0698  * @adapter: private adapter struct
0699  *
0700  * this watchdog task periodically reads the timecounter
0701  * in order to prevent missing when the system time registers wrap
0702  * around. This needs to be run approximately twice a minute.
0703  */
0704 void ixgbe_ptp_overflow_check(struct ixgbe_adapter *adapter)
0705 {
0706     bool timeout = time_is_before_jiffies(adapter->last_overflow_check +
0707                          IXGBE_OVERFLOW_PERIOD);
0708     unsigned long flags;
0709
0710     if (timeout) {
0711         /* Update the timecounter */
0712         spin_lock_irqsave(&adapter->tmreg_lock, flags);
0713         timecounter_read(&adapter->hw_tc);
0714         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
0715
0716         adapter->last_overflow_check = jiffies;
0717     }
0718 }
0719
0720 /**
0721  * ixgbe_ptp_rx_hang - detect error case when Rx timestamp registers latched
0722  * @adapter: private network adapter structure
0723  *
0724  * this watchdog task is scheduled to detect error case where hardware has
0725  * dropped an Rx packet that was timestamped when the ring is full. The
0726  * particular error is rare but leaves the device in a state unable to timestamp
0727  * any future packets.
0728  */
0729 void ixgbe_ptp_rx_hang(struct ixgbe_adapter *adapter)
0730 {
0731     struct ixgbe_hw *hw = &adapter->hw;
0732     u32 tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
0733     struct ixgbe_ring *rx_ring;
0734     unsigned long rx_event;
0735     int n;
0736
0737     /* if we don't have a valid timestamp in the registers, just update the
0738      * timeout counter and exit
0739      */
0740     if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID)) {
0741         adapter->last_rx_ptp_check = jiffies;
0742         return;
0743     }
0744
0745     /* determine the most recent watchdog or rx_timestamp event */
0746     rx_event = adapter->last_rx_ptp_check;
0747     for (n = 0; n < adapter->num_rx_queues; n++) {
0748         rx_ring = adapter->rx_ring[n];
0749         if (time_after(rx_ring->last_rx_timestamp, rx_event))
0750             rx_event = rx_ring->last_rx_timestamp;
0751     }
0752
0753     /* only need to read the high RXSTMP register to clear the lock */
0754     if (time_is_before_jiffies(rx_event + 5 * HZ)) {
0755         IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
0756         adapter->last_rx_ptp_check = jiffies;
0757
0758         adapter->rx_hwtstamp_cleared++;
0759         e_warn(drv, "clearing RX Timestamp hang\n");
0760     }
0761 }
0762
0763 /**
0764  * ixgbe_ptp_clear_tx_timestamp - utility function to clear Tx timestamp state
0765  * @adapter: the private adapter structure
0766  *
0767  * This function should be called whenever the state related to a Tx timestamp
0768  * needs to be cleared. This helps ensure that all related bits are reset for
0769  * the next Tx timestamp event.
0770  */
0771 static void ixgbe_ptp_clear_tx_timestamp(struct ixgbe_adapter *adapter)
0772 {
0773     struct ixgbe_hw *hw = &adapter->hw;
0774
0775     IXGBE_READ_REG(hw, IXGBE_TXSTMPH);
0776     if (adapter->ptp_tx_skb) {
0777         dev_kfree_skb_any(adapter->ptp_tx_skb);
0778         adapter->ptp_tx_skb = NULL;
0779     }
0780     clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
0781 }
0782
0783 /**
0784  * ixgbe_ptp_tx_hang - detect error case where Tx timestamp never finishes
0785  * @adapter: private network adapter structure
0786  */
0787 void ixgbe_ptp_tx_hang(struct ixgbe_adapter *adapter)
0788 {
0789     bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
0790                           IXGBE_PTP_TX_TIMEOUT);
0791
0792     if (!adapter->ptp_tx_skb)
0793         return;
0794
0795     if (!test_bit(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state))
0796         return;
0797
0798     /* If we haven't received a timestamp within the timeout, it is
0799      * reasonable to assume that it will never occur, so we can unlock the
0800      * timestamp bit when this occurs.
0801      */
0802     if (timeout) {
0803         cancel_work_sync(&adapter->ptp_tx_work);
0804         ixgbe_ptp_clear_tx_timestamp(adapter);
0805         adapter->tx_hwtstamp_timeouts++;
0806         e_warn(drv, "clearing Tx timestamp hang\n");
0807     }
0808 }
0809
0810 /**
0811  * ixgbe_ptp_tx_hwtstamp - utility function which checks for TX time stamp
0812  * @adapter: the private adapter struct
0813  *
0814  * if the timestamp is valid, we convert it into the timecounter ns
0815  * value, then store that result into the shhwtstamps structure which
0816  * is passed up the network stack
0817  */
0818 static void ixgbe_ptp_tx_hwtstamp(struct ixgbe_adapter *adapter)
0819 {
0820     struct sk_buff *skb = adapter->ptp_tx_skb;
0821     struct ixgbe_hw *hw = &adapter->hw;
0822     struct skb_shared_hwtstamps shhwtstamps;
0823     u64 regval = 0;
0824
0825     regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPL);
0826     regval |= (u64)IXGBE_READ_REG(hw, IXGBE_TXSTMPH) << 32;
0827     ixgbe_ptp_convert_to_hwtstamp(adapter, &shhwtstamps, regval);
0828
0829     /* Handle cleanup of the ptp_tx_skb ourselves, and unlock the state
0830      * bit prior to notifying the stack via skb_tstamp_tx(). This prevents
0831      * well behaved applications from attempting to timestamp again prior
0832      * to the lock bit being clear.
0833      */
0834     adapter->ptp_tx_skb = NULL;
0835     clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
0836
0837     /* Notify the stack and then free the skb after we've unlocked */
0838     skb_tstamp_tx(skb, &shhwtstamps);
0839     dev_kfree_skb_any(skb);
0840 }
0841
0842 /**
0843  * ixgbe_ptp_tx_hwtstamp_work
0844  * @work: pointer to the work struct
0845  *
0846  * This work item polls TSYNCTXCTL valid bit to determine when a Tx hardware
0847  * timestamp has been taken for the current skb. It is necessary, because the
0848  * descriptor's "done" bit does not correlate with the timestamp event.
0849  */
0850 static void ixgbe_ptp_tx_hwtstamp_work(struct work_struct *work)
0851 {
0852     struct ixgbe_adapter *adapter = container_of(work, struct ixgbe_adapter,
0853                              ptp_tx_work);
0854     struct ixgbe_hw *hw = &adapter->hw;
0855     bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
0856                           IXGBE_PTP_TX_TIMEOUT);
0857     u32 tsynctxctl;
0858
0859     /* we have to have a valid skb to poll for a timestamp */
0860     if (!adapter->ptp_tx_skb) {
0861         ixgbe_ptp_clear_tx_timestamp(adapter);
0862         return;
0863     }
0864
0865     /* stop polling once we have a valid timestamp */
0866     tsynctxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
0867     if (tsynctxctl & IXGBE_TSYNCTXCTL_VALID) {
0868         ixgbe_ptp_tx_hwtstamp(adapter);
0869         return;
0870     }
0871
0872     if (timeout) {
0873         ixgbe_ptp_clear_tx_timestamp(adapter);
0874         adapter->tx_hwtstamp_timeouts++;
0875         e_warn(drv, "clearing Tx Timestamp hang\n");
0876     } else {
0877         /* reschedule to keep checking if it's not available yet */
0878         schedule_work(&adapter->ptp_tx_work);
0879     }
0880 }
0881
0882 /**
0883  * ixgbe_ptp_rx_pktstamp - utility function to get RX time stamp from buffer
0884  * @q_vector: structure containing interrupt and ring information
0885  * @skb: the packet
0886  *
0887  * This function will be called by the Rx routine of the timestamp for this
0888  * packet is stored in the buffer. The value is stored in little endian format
0889  * starting at the end of the packet data.
0890  */
0891 void ixgbe_ptp_rx_pktstamp(struct ixgbe_q_vector *q_vector,
0892                struct sk_buff *skb)
0893 {
0894     __le64 regval;
0895
0896     /* copy the bits out of the skb, and then trim the skb length */
0897     skb_copy_bits(skb, skb->len - IXGBE_TS_HDR_LEN, &regval,
0898               IXGBE_TS_HDR_LEN);
0899     __pskb_trim(skb, skb->len - IXGBE_TS_HDR_LEN);
0900
0901     /* The timestamp is recorded in little endian format, and is stored at
0902      * the end of the packet.
0903      *
0904      * DWORD: N              N + 1      N + 2
0905      * Field: End of Packet  SYSTIMH    SYSTIML
0906      */
0907     ixgbe_ptp_convert_to_hwtstamp(q_vector->adapter, skb_hwtstamps(skb),
0908                       le64_to_cpu(regval));
0909 }
0910
0911 /**
0912  * ixgbe_ptp_rx_rgtstamp - utility function which checks for RX time stamp
0913  * @q_vector: structure containing interrupt and ring information
0914  * @skb: particular skb to send timestamp with
0915  *
0916  * if the timestamp is valid, we convert it into the timecounter ns
0917  * value, then store that result into the shhwtstamps structure which
0918  * is passed up the network stack
0919  */
0920 void ixgbe_ptp_rx_rgtstamp(struct ixgbe_q_vector *q_vector,
0921                struct sk_buff *skb)
0922 {
0923     struct ixgbe_adapter *adapter;
0924     struct ixgbe_hw *hw;
0925     u64 regval = 0;
0926     u32 tsyncrxctl;
0927
0928     /* we cannot process timestamps on a ring without a q_vector */
0929     if (!q_vector || !q_vector->adapter)
0930         return;
0931
0932     adapter = q_vector->adapter;
0933     hw = &adapter->hw;
0934
0935     /* Read the tsyncrxctl register afterwards in order to prevent taking an
0936      * I/O hit on every packet.
0937      */
0938
0939     tsyncrxctl = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
0940     if (!(tsyncrxctl & IXGBE_TSYNCRXCTL_VALID))
0941         return;
0942
0943     regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPL);
0944     regval |= (u64)IXGBE_READ_REG(hw, IXGBE_RXSTMPH) << 32;
0945
0946     ixgbe_ptp_convert_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
0947 }
0948
0949 /**
0950  * ixgbe_ptp_get_ts_config - get current hardware timestamping configuration
0951  * @adapter: pointer to adapter structure
0952  * @ifr: ioctl data
0953  *
0954  * This function returns the current timestamping settings. Rather than
0955  * attempt to deconstruct registers to fill in the values, simply keep a copy
0956  * of the old settings around, and return a copy when requested.
0957  */
0958 int ixgbe_ptp_get_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
0959 {
0960     struct hwtstamp_config *config = &adapter->tstamp_config;
0961
0962     return copy_to_user(ifr->ifr_data, config,
0963                 sizeof(*config)) ? -EFAULT : 0;
0964 }
0965
0966 /**
0967  * ixgbe_ptp_set_timestamp_mode - setup the hardware for the requested mode
0968  * @adapter: the private ixgbe adapter structure
0969  * @config: the hwtstamp configuration requested
0970  *
0971  * Outgoing time stamping can be enabled and disabled. Play nice and
0972  * disable it when requested, although it shouldn't cause any overhead
0973  * when no packet needs it. At most one packet in the queue may be
0974  * marked for time stamping, otherwise it would be impossible to tell
0975  * for sure to which packet the hardware time stamp belongs.
0976  *
0977  * Incoming time stamping has to be configured via the hardware
0978  * filters. Not all combinations are supported, in particular event
0979  * type has to be specified. Matching the kind of event packet is
0980  * not supported, with the exception of "all V2 events regardless of
0981  * level 2 or 4".
0982  *
0983  * Since hardware always timestamps Path delay packets when timestamping V2
0984  * packets, regardless of the type specified in the register, only use V2
0985  * Event mode. This more accurately tells the user what the hardware is going
0986  * to do anyways.
0987  *
0988  * Note: this may modify the hwtstamp configuration towards a more general
0989  * mode, if required to support the specifically requested mode.
0990  */
0991 static int ixgbe_ptp_set_timestamp_mode(struct ixgbe_adapter *adapter,
0992                  struct hwtstamp_config *config)
0993 {
0994     struct ixgbe_hw *hw = &adapter->hw;
0995     u32 tsync_tx_ctl = IXGBE_TSYNCTXCTL_ENABLED;
0996     u32 tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED;
0997     u32 tsync_rx_mtrl = PTP_EV_PORT << 16;
0998     bool is_l2 = false;
0999     u32 regval;
1000
1001     switch (config->tx_type) {
1002     case HWTSTAMP_TX_OFF:
1003         tsync_tx_ctl = 0;
1004         break;
1005     case HWTSTAMP_TX_ON:
1006         break;
1007     default:
1008         return -ERANGE;
1009     }
1010
1011     switch (config->rx_filter) {
1012     case HWTSTAMP_FILTER_NONE:
1013         tsync_rx_ctl = 0;
1014         tsync_rx_mtrl = 0;
1015         adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1016                     IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1017         break;
1018     case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1019         tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
1020         tsync_rx_mtrl |= IXGBE_RXMTRL_V1_SYNC_MSG;
1021         adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1022                    IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1023         break;
1024     case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1025         tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_L4_V1;
1026         tsync_rx_mtrl |= IXGBE_RXMTRL_V1_DELAY_REQ_MSG;
1027         adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1028                    IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1029         break;
1030     case HWTSTAMP_FILTER_PTP_V2_EVENT:
1031     case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1032     case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1033     case HWTSTAMP_FILTER_PTP_V2_SYNC:
1034     case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1035     case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1036     case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1037     case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1038     case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1039         tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_EVENT_V2;
1040         is_l2 = true;
1041         config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1042         adapter->flags |= (IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1043                    IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1044         break;
1045     case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1046     case HWTSTAMP_FILTER_NTP_ALL:
1047     case HWTSTAMP_FILTER_ALL:
1048         /* The X550 controller is capable of timestamping all packets,
1049          * which allows it to accept any filter.
1050          */
1051         if (hw->mac.type >= ixgbe_mac_X550) {
1052             tsync_rx_ctl |= IXGBE_TSYNCRXCTL_TYPE_ALL;
1053             config->rx_filter = HWTSTAMP_FILTER_ALL;
1054             adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
1055             break;
1056         }
1057         fallthrough;
1058     default:
1059         /*
1060          * register RXMTRL must be set in order to do V1 packets,
1061          * therefore it is not possible to time stamp both V1 Sync and
1062          * Delay_Req messages and hardware does not support
1063          * timestamping all packets => return error
1064          */
1065         adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1066                     IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1067         config->rx_filter = HWTSTAMP_FILTER_NONE;
1068         return -ERANGE;
1069     }
1070
1071     if (hw->mac.type == ixgbe_mac_82598EB) {
1072         adapter->flags &= ~(IXGBE_FLAG_RX_HWTSTAMP_ENABLED |
1073                     IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER);
1074         if (tsync_rx_ctl | tsync_tx_ctl)
1075             return -ERANGE;
1076         return 0;
1077     }
1078
1079     /* Per-packet timestamping only works if the filter is set to all
1080      * packets. Since this is desired, always timestamp all packets as long
1081      * as any Rx filter was configured.
1082      */
1083     switch (hw->mac.type) {
1084     case ixgbe_mac_X550:
1085     case ixgbe_mac_X550EM_x:
1086     case ixgbe_mac_x550em_a:
1087         /* enable timestamping all packets only if at least some
1088          * packets were requested. Otherwise, play nice and disable
1089          * timestamping
1090          */
1091         if (config->rx_filter == HWTSTAMP_FILTER_NONE)
1092             break;
1093
1094         tsync_rx_ctl = IXGBE_TSYNCRXCTL_ENABLED |
1095                    IXGBE_TSYNCRXCTL_TYPE_ALL |
1096                    IXGBE_TSYNCRXCTL_TSIP_UT_EN;
1097         config->rx_filter = HWTSTAMP_FILTER_ALL;
1098         adapter->flags |= IXGBE_FLAG_RX_HWTSTAMP_ENABLED;
1099         adapter->flags &= ~IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER;
1100         is_l2 = true;
1101         break;
1102     default:
1103         break;
1104     }
1105
1106     /* define ethertype filter for timestamping L2 packets */
1107     if (is_l2)
1108         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588),
1109                 (IXGBE_ETQF_FILTER_EN | /* enable filter */
1110                  IXGBE_ETQF_1588 | /* enable timestamping */
1111                  ETH_P_1588));     /* 1588 eth protocol type */
1112     else
1113         IXGBE_WRITE_REG(hw, IXGBE_ETQF(IXGBE_ETQF_FILTER_1588), 0);
1114
1115     /* enable/disable TX */
1116     regval = IXGBE_READ_REG(hw, IXGBE_TSYNCTXCTL);
1117     regval &= ~IXGBE_TSYNCTXCTL_ENABLED;
1118     regval |= tsync_tx_ctl;
1119     IXGBE_WRITE_REG(hw, IXGBE_TSYNCTXCTL, regval);
1120
1121     /* enable/disable RX */
1122     regval = IXGBE_READ_REG(hw, IXGBE_TSYNCRXCTL);
1123     regval &= ~(IXGBE_TSYNCRXCTL_ENABLED | IXGBE_TSYNCRXCTL_TYPE_MASK);
1124     regval |= tsync_rx_ctl;
1125     IXGBE_WRITE_REG(hw, IXGBE_TSYNCRXCTL, regval);
1126
1127     /* define which PTP packets are time stamped */
1128     IXGBE_WRITE_REG(hw, IXGBE_RXMTRL, tsync_rx_mtrl);
1129
1130     IXGBE_WRITE_FLUSH(hw);
1131
1132     /* clear TX/RX time stamp registers, just to be sure */
1133     ixgbe_ptp_clear_tx_timestamp(adapter);
1134     IXGBE_READ_REG(hw, IXGBE_RXSTMPH);
1135
1136     return 0;
1137 }
1138
1139 /**
1140  * ixgbe_ptp_set_ts_config - user entry point for timestamp mode
1141  * @adapter: pointer to adapter struct
1142  * @ifr: ioctl data
1143  *
1144  * Set hardware to requested mode. If unsupported, return an error with no
1145  * changes. Otherwise, store the mode for future reference.
1146  */
1147 int ixgbe_ptp_set_ts_config(struct ixgbe_adapter *adapter, struct ifreq *ifr)
1148 {
1149     struct hwtstamp_config config;
1150     int err;
1151
1152     if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1153         return -EFAULT;
1154
1155     err = ixgbe_ptp_set_timestamp_mode(adapter, &config);
1156     if (err)
1157         return err;
1158
1159     /* save these settings for future reference */
1160     memcpy(&adapter->tstamp_config, &config,
1161            sizeof(adapter->tstamp_config));
1162
1163     return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1164         -EFAULT : 0;
1165 }
1166
1167 static void ixgbe_ptp_link_speed_adjust(struct ixgbe_adapter *adapter,
1168                     u32 *shift, u32 *incval)
1169 {
1170     /**
1171      * Scale the NIC cycle counter by a large factor so that
1172      * relatively small corrections to the frequency can be added
1173      * or subtracted. The drawbacks of a large factor include
1174      * (a) the clock register overflows more quickly, (b) the cycle
1175      * counter structure must be able to convert the systime value
1176      * to nanoseconds using only a multiplier and a right-shift,
1177      * and (c) the value must fit within the timinca register space
1178      * => math based on internal DMA clock rate and available bits
1179      *
1180      * Note that when there is no link, internal DMA clock is same as when
1181      * link speed is 10Gb. Set the registers correctly even when link is
1182      * down to preserve the clock setting
1183      */
1184     switch (adapter->link_speed) {
1185     case IXGBE_LINK_SPEED_100_FULL:
1186         *shift = IXGBE_INCVAL_SHIFT_100;
1187         *incval = IXGBE_INCVAL_100;
1188         break;
1189     case IXGBE_LINK_SPEED_1GB_FULL:
1190         *shift = IXGBE_INCVAL_SHIFT_1GB;
1191         *incval = IXGBE_INCVAL_1GB;
1192         break;
1193     case IXGBE_LINK_SPEED_10GB_FULL:
1194     default:
1195         *shift = IXGBE_INCVAL_SHIFT_10GB;
1196         *incval = IXGBE_INCVAL_10GB;
1197         break;
1198     }
1199 }
1200
1201 /**
1202  * ixgbe_ptp_start_cyclecounter - create the cycle counter from hw
1203  * @adapter: pointer to the adapter structure
1204  *
1205  * This function should be called to set the proper values for the TIMINCA
1206  * register and tell the cyclecounter structure what the tick rate of SYSTIME
1207  * is. It does not directly modify SYSTIME registers or the timecounter
1208  * structure. It should be called whenever a new TIMINCA value is necessary,
1209  * such as during initialization or when the link speed changes.
1210  */
1211 void ixgbe_ptp_start_cyclecounter(struct ixgbe_adapter *adapter)
1212 {
1213     struct ixgbe_hw *hw = &adapter->hw;
1214     struct cyclecounter cc;
1215     unsigned long flags;
1216     u32 incval = 0;
1217     u32 fuse0 = 0;
1218
1219     /* For some of the boards below this mask is technically incorrect.
1220      * The timestamp mask overflows at approximately 61bits. However the
1221      * particular hardware does not overflow on an even bitmask value.
1222      * Instead, it overflows due to conversion of upper 32bits billions of
1223      * cycles. Timecounters are not really intended for this purpose so
1224      * they do not properly function if the overflow point isn't 2^N-1.
1225      * However, the actual SYSTIME values in question take ~138 years to
1226      * overflow. In practice this means they won't actually overflow. A
1227      * proper fix to this problem would require modification of the
1228      * timecounter delta calculations.
1229      */
1230     cc.mask = CLOCKSOURCE_MASK(64);
1231     cc.mult = 1;
1232     cc.shift = 0;
1233
1234     switch (hw->mac.type) {
1235     case ixgbe_mac_X550EM_x:
1236         /* SYSTIME assumes X550EM_x board frequency is 300Mhz, and is
1237          * designed to represent seconds and nanoseconds when this is
1238          * the case. However, some revisions of hardware have a 400Mhz
1239          * clock and we have to compensate for this frequency
1240          * variation using corrected mult and shift values.
1241          */
1242         fuse0 = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0));
1243         if (!(fuse0 & IXGBE_FUSES0_300MHZ)) {
1244             cc.mult = 3;
1245             cc.shift = 2;
1246         }
1247         fallthrough;
1248     case ixgbe_mac_x550em_a:
1249     case ixgbe_mac_X550:
1250         cc.read = ixgbe_ptp_read_X550;
1251         break;
1252     case ixgbe_mac_X540:
1253         cc.read = ixgbe_ptp_read_82599;
1254
1255         ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1256         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA, incval);
1257         break;
1258     case ixgbe_mac_82599EB:
1259         cc.read = ixgbe_ptp_read_82599;
1260
1261         ixgbe_ptp_link_speed_adjust(adapter, &cc.shift, &incval);
1262         incval >>= IXGBE_INCVAL_SHIFT_82599;
1263         cc.shift -= IXGBE_INCVAL_SHIFT_82599;
1264         IXGBE_WRITE_REG(hw, IXGBE_TIMINCA,
1265                 BIT(IXGBE_INCPER_SHIFT_82599) | incval);
1266         break;
1267     default:
1268         /* other devices aren't supported */
1269         return;
1270     }
1271
1272     /* update the base incval used to calculate frequency adjustment */
1273     WRITE_ONCE(adapter->base_incval, incval);
1274     smp_mb();
1275
1276     /* need lock to prevent incorrect read while modifying cyclecounter */
1277     spin_lock_irqsave(&adapter->tmreg_lock, flags);
1278     memcpy(&adapter->hw_cc, &cc, sizeof(adapter->hw_cc));
1279     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1280 }
1281
1282 /**
1283  * ixgbe_ptp_init_systime - Initialize SYSTIME registers
1284  * @adapter: the ixgbe private board structure
1285  *
1286  * Initialize and start the SYSTIME registers.
1287  */
1288 static void ixgbe_ptp_init_systime(struct ixgbe_adapter *adapter)
1289 {
1290     struct ixgbe_hw *hw = &adapter->hw;
1291     u32 tsauxc;
1292
1293     switch (hw->mac.type) {
1294     case ixgbe_mac_X550EM_x:
1295     case ixgbe_mac_x550em_a:
1296     case ixgbe_mac_X550:
1297         tsauxc = IXGBE_READ_REG(hw, IXGBE_TSAUXC);
1298
1299         /* Reset SYSTIME registers to 0 */
1300         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMR, 0);
1301         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1302         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1303
1304         /* Reset interrupt settings */
1305         IXGBE_WRITE_REG(hw, IXGBE_TSIM, IXGBE_TSIM_TXTS);
1306         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_TIMESYNC);
1307
1308         /* Activate the SYSTIME counter */
1309         IXGBE_WRITE_REG(hw, IXGBE_TSAUXC,
1310                 tsauxc & ~IXGBE_TSAUXC_DISABLE_SYSTIME);
1311         break;
1312     case ixgbe_mac_X540:
1313     case ixgbe_mac_82599EB:
1314         /* Reset SYSTIME registers to 0 */
1315         IXGBE_WRITE_REG(hw, IXGBE_SYSTIML, 0);
1316         IXGBE_WRITE_REG(hw, IXGBE_SYSTIMH, 0);
1317         break;
1318     default:
1319         /* Other devices aren't supported */
1320         return;
1321     };
1322
1323     IXGBE_WRITE_FLUSH(hw);
1324 }
1325
1326 /**
1327  * ixgbe_ptp_reset
1328  * @adapter: the ixgbe private board structure
1329  *
1330  * When the MAC resets, all the hardware bits for timesync are reset. This
1331  * function is used to re-enable the device for PTP based on current settings.
1332  * We do lose the current clock time, so just reset the cyclecounter to the
1333  * system real clock time.
1334  *
1335  * This function will maintain hwtstamp_config settings, and resets the SDP
1336  * output if it was enabled.
1337  */
1338 void ixgbe_ptp_reset(struct ixgbe_adapter *adapter)
1339 {
1340     struct ixgbe_hw *hw = &adapter->hw;
1341     unsigned long flags;
1342
1343     /* reset the hardware timestamping mode */
1344     ixgbe_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1345
1346     /* 82598 does not support PTP */
1347     if (hw->mac.type == ixgbe_mac_82598EB)
1348         return;
1349
1350     ixgbe_ptp_start_cyclecounter(adapter);
1351
1352     ixgbe_ptp_init_systime(adapter);
1353
1354     spin_lock_irqsave(&adapter->tmreg_lock, flags);
1355     timecounter_init(&adapter->hw_tc, &adapter->hw_cc,
1356              ktime_to_ns(ktime_get_real()));
1357     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1358
1359     adapter->last_overflow_check = jiffies;
1360
1361     /* Now that the shift has been calculated and the systime
1362      * registers reset, (re-)enable the Clock out feature
1363      */
1364     if (adapter->ptp_setup_sdp)
1365         adapter->ptp_setup_sdp(adapter);
1366 }
1367
1368 /**
1369  * ixgbe_ptp_create_clock
1370  * @adapter: the ixgbe private adapter structure
1371  *
1372  * This function performs setup of the user entry point function table and
1373  * initializes the PTP clock device, which is used to access the clock-like
1374  * features of the PTP core. It will be called by ixgbe_ptp_init, and may
1375  * reuse a previously initialized clock (such as during a suspend/resume
1376  * cycle).
1377  */
1378 static long ixgbe_ptp_create_clock(struct ixgbe_adapter *adapter)
1379 {
1380     struct net_device *netdev = adapter->netdev;
1381     long err;
1382
1383     /* do nothing if we already have a clock device */
1384     if (!IS_ERR_OR_NULL(adapter->ptp_clock))
1385         return 0;
1386
1387     switch (adapter->hw.mac.type) {
1388     case ixgbe_mac_X540:
1389         snprintf(adapter->ptp_caps.name,
1390              sizeof(adapter->ptp_caps.name),
1391              "%s", netdev->name);
1392         adapter->ptp_caps.owner = THIS_MODULE;
1393         adapter->ptp_caps.max_adj = 250000000;
1394         adapter->ptp_caps.n_alarm = 0;
1395         adapter->ptp_caps.n_ext_ts = 0;
1396         adapter->ptp_caps.n_per_out = 0;
1397         adapter->ptp_caps.pps = 1;
1398         adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_82599;
1399         adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1400         adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1401         adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1402         adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1403         adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X540;
1404         break;
1405     case ixgbe_mac_82599EB:
1406         snprintf(adapter->ptp_caps.name,
1407              sizeof(adapter->ptp_caps.name),
1408              "%s", netdev->name);
1409         adapter->ptp_caps.owner = THIS_MODULE;
1410         adapter->ptp_caps.max_adj = 250000000;
1411         adapter->ptp_caps.n_alarm = 0;
1412         adapter->ptp_caps.n_ext_ts = 0;
1413         adapter->ptp_caps.n_per_out = 0;
1414         adapter->ptp_caps.pps = 0;
1415         adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_82599;
1416         adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1417         adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1418         adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1419         adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1420         break;
1421     case ixgbe_mac_X550:
1422     case ixgbe_mac_X550EM_x:
1423     case ixgbe_mac_x550em_a:
1424         snprintf(adapter->ptp_caps.name, 16, "%s", netdev->name);
1425         adapter->ptp_caps.owner = THIS_MODULE;
1426         adapter->ptp_caps.max_adj = 30000000;
1427         adapter->ptp_caps.n_alarm = 0;
1428         adapter->ptp_caps.n_ext_ts = 0;
1429         adapter->ptp_caps.n_per_out = 0;
1430         adapter->ptp_caps.pps = 1;
1431         adapter->ptp_caps.adjfine = ixgbe_ptp_adjfine_X550;
1432         adapter->ptp_caps.adjtime = ixgbe_ptp_adjtime;
1433         adapter->ptp_caps.gettimex64 = ixgbe_ptp_gettimex;
1434         adapter->ptp_caps.settime64 = ixgbe_ptp_settime;
1435         adapter->ptp_caps.enable = ixgbe_ptp_feature_enable;
1436         adapter->ptp_setup_sdp = ixgbe_ptp_setup_sdp_X550;
1437         break;
1438     default:
1439         adapter->ptp_clock = NULL;
1440         adapter->ptp_setup_sdp = NULL;
1441         return -EOPNOTSUPP;
1442     }
1443
1444     adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1445                         &adapter->pdev->dev);
1446     if (IS_ERR(adapter->ptp_clock)) {
1447         err = PTR_ERR(adapter->ptp_clock);
1448         adapter->ptp_clock = NULL;
1449         e_dev_err("ptp_clock_register failed\n");
1450         return err;
1451     } else if (adapter->ptp_clock)
1452         e_dev_info("registered PHC device on %s\n", netdev->name);
1453
1454     /* set default timestamp mode to disabled here. We do this in
1455      * create_clock instead of init, because we don't want to override the
1456      * previous settings during a resume cycle.
1457      */
1458     adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1459     adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1460
1461     return 0;
1462 }
1463
1464 /**
1465  * ixgbe_ptp_init
1466  * @adapter: the ixgbe private adapter structure
1467  *
1468  * This function performs the required steps for enabling PTP
1469  * support. If PTP support has already been loaded it simply calls the
1470  * cyclecounter init routine and exits.
1471  */
1472 void ixgbe_ptp_init(struct ixgbe_adapter *adapter)
1473 {
1474     /* initialize the spin lock first since we can't control when a user
1475      * will call the entry functions once we have initialized the clock
1476      * device
1477      */
1478     spin_lock_init(&adapter->tmreg_lock);
1479
1480     /* obtain a PTP device, or re-use an existing device */
1481     if (ixgbe_ptp_create_clock(adapter))
1482         return;
1483
1484     /* we have a clock so we can initialize work now */
1485     INIT_WORK(&adapter->ptp_tx_work, ixgbe_ptp_tx_hwtstamp_work);
1486
1487     /* reset the PTP related hardware bits */
1488     ixgbe_ptp_reset(adapter);
1489
1490     /* enter the IXGBE_PTP_RUNNING state */
1491     set_bit(__IXGBE_PTP_RUNNING, &adapter->state);
1492
1493     return;
1494 }
1495
1496 /**
1497  * ixgbe_ptp_suspend - stop PTP work items
1498  * @adapter: pointer to adapter struct
1499  *
1500  * this function suspends PTP activity, and prevents more PTP work from being
1501  * generated, but does not destroy the PTP clock device.
1502  */
1503 void ixgbe_ptp_suspend(struct ixgbe_adapter *adapter)
1504 {
1505     /* Leave the IXGBE_PTP_RUNNING state. */
1506     if (!test_and_clear_bit(__IXGBE_PTP_RUNNING, &adapter->state))
1507         return;
1508
1509     adapter->flags2 &= ~IXGBE_FLAG2_PTP_PPS_ENABLED;
1510     if (adapter->ptp_setup_sdp)
1511         adapter->ptp_setup_sdp(adapter);
1512
1513     /* ensure that we cancel any pending PTP Tx work item in progress */
1514     cancel_work_sync(&adapter->ptp_tx_work);
1515     ixgbe_ptp_clear_tx_timestamp(adapter);
1516 }
1517
1518 /**
1519  * ixgbe_ptp_stop - close the PTP device
1520  * @adapter: pointer to adapter struct
1521  *
1522  * completely destroy the PTP device, should only be called when the device is
1523  * being fully closed.
1524  */
1525 void ixgbe_ptp_stop(struct ixgbe_adapter *adapter)
1526 {
1527     /* first, suspend PTP activity */
1528     ixgbe_ptp_suspend(adapter);
1529
1530     /* disable the PTP clock device */
1531     if (adapter->ptp_clock) {
1532         ptp_clock_unregister(adapter->ptp_clock);
1533         adapter->ptp_clock = NULL;
1534         e_dev_info("removed PHC on %s\n",
1535                adapter->netdev->name);
1536     }
1537 }