intel/ixgbe/ixgbe_phy.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #ifndef _IXGBE_PHY_H_
0005 #define _IXGBE_PHY_H_
0006
0007 #include "ixgbe_type.h"
0008 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
0009 #define IXGBE_I2C_EEPROM_DEV_ADDR2   0xA2
0010
0011 /* EEPROM byte offsets */
0012 #define IXGBE_SFF_IDENTIFIER        0x0
0013 #define IXGBE_SFF_IDENTIFIER_SFP    0x3
0014 #define IXGBE_SFF_VENDOR_OUI_BYTE0  0x25
0015 #define IXGBE_SFF_VENDOR_OUI_BYTE1  0x26
0016 #define IXGBE_SFF_VENDOR_OUI_BYTE2  0x27
0017 #define IXGBE_SFF_1GBE_COMP_CODES   0x6
0018 #define IXGBE_SFF_10GBE_COMP_CODES  0x3
0019 #define IXGBE_SFF_CABLE_TECHNOLOGY  0x8
0020 #define IXGBE_SFF_CABLE_SPEC_COMP   0x3C
0021 #define IXGBE_SFF_SFF_8472_SWAP     0x5C
0022 #define IXGBE_SFF_SFF_8472_COMP     0x5E
0023 #define IXGBE_SFF_SFF_8472_OSCB     0x6E
0024 #define IXGBE_SFF_SFF_8472_ESCB     0x76
0025 #define IXGBE_SFF_IDENTIFIER_QSFP_PLUS  0xD
0026 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
0027 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
0028 #define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
0029 #define IXGBE_SFF_QSFP_CONNECTOR    0x82
0030 #define IXGBE_SFF_QSFP_10GBE_COMP   0x83
0031 #define IXGBE_SFF_QSFP_1GBE_COMP    0x86
0032 #define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92
0033 #define IXGBE_SFF_QSFP_DEVICE_TECH  0x93
0034
0035 /* Bitmasks */
0036 #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
0037 #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
0038 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING   0x4
0039 #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
0040 #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
0041 #define IXGBE_SFF_1GBASET_CAPABLE       0x8
0042 #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
0043 #define IXGBE_SFF_10GBASELR_CAPABLE     0x20
0044 #define IXGBE_SFF_SOFT_RS_SELECT_MASK       0x8
0045 #define IXGBE_SFF_SOFT_RS_SELECT_10G        0x8
0046 #define IXGBE_SFF_SOFT_RS_SELECT_1G     0x0
0047 #define IXGBE_SFF_ADDRESSING_MODE       0x4
0048 #define IXGBE_SFF_DDM_IMPLEMENTED       0x40
0049 #define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE      0x1
0050 #define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE     0x8
0051 #define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE  0x23
0052 #define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL   0x0
0053 #define IXGBE_I2C_EEPROM_READ_MASK      0x100
0054 #define IXGBE_I2C_EEPROM_STATUS_MASK        0x3
0055 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
0056 #define IXGBE_I2C_EEPROM_STATUS_PASS        0x1
0057 #define IXGBE_I2C_EEPROM_STATUS_FAIL        0x2
0058 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
0059 #define IXGBE_CS4227                0xBE    /* CS4227 address */
0060 #define IXGBE_CS4227_GLOBAL_ID_LSB      0
0061 #define IXGBE_CS4227_GLOBAL_ID_MSB      1
0062 #define IXGBE_CS4227_SCRATCH            2
0063 #define IXGBE_CS4227_EFUSE_PDF_SKU      0x19F
0064 #define IXGBE_CS4223_SKU_ID         0x0010  /* Quad port */
0065 #define IXGBE_CS4227_SKU_ID         0x0014  /* Dual port */
0066 #define IXGBE_CS4227_RESET_PENDING      0x1357
0067 #define IXGBE_CS4227_RESET_COMPLETE     0x5AA5
0068 #define IXGBE_CS4227_RETRIES            15
0069 #define IXGBE_CS4227_EFUSE_STATUS       0x0181
0070 #define IXGBE_CS4227_LINE_SPARE22_MSB       0x12AD  /* Reg to set speed */
0071 #define IXGBE_CS4227_LINE_SPARE24_LSB       0x12B0  /* Reg to set EDC */
0072 #define IXGBE_CS4227_HOST_SPARE22_MSB       0x1AAD  /* Reg to set speed */
0073 #define IXGBE_CS4227_HOST_SPARE24_LSB       0x1AB0  /* Reg to program EDC */
0074 #define IXGBE_CS4227_EEPROM_STATUS      0x5001
0075 #define IXGBE_CS4227_EEPROM_LOAD_OK     0x0001
0076 #define IXGBE_CS4227_SPEED_1G           0x8000
0077 #define IXGBE_CS4227_SPEED_10G          0
0078 #define IXGBE_CS4227_EDC_MODE_CX1       0x0002
0079 #define IXGBE_CS4227_EDC_MODE_SR        0x0004
0080 #define IXGBE_CS4227_EDC_MODE_DIAG      0x0008
0081 #define IXGBE_CS4227_RESET_HOLD         500 /* microseconds */
0082 #define IXGBE_CS4227_RESET_DELAY        500 /* milliseconds */
0083 #define IXGBE_CS4227_CHECK_DELAY        30  /* milliseconds */
0084 #define IXGBE_PE                0xE0    /* Port expander addr */
0085 #define IXGBE_PE_OUTPUT             1   /* Output reg offset */
0086 #define IXGBE_PE_CONFIG             3   /* Config reg offset */
0087 #define IXGBE_PE_BIT1               BIT(1)
0088
0089 /* Flow control defines */
0090 #define IXGBE_TAF_SYM_PAUSE                  0x400
0091 #define IXGBE_TAF_ASM_PAUSE                  0x800
0092
0093 /* Bit-shift macros */
0094 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
0095 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
0096 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
0097
0098 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
0099 #define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
0100 #define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
0101 #define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
0102 #define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
0103
0104 /* I2C SDA and SCL timing parameters for standard mode */
0105 #define IXGBE_I2C_T_HD_STA  4
0106 #define IXGBE_I2C_T_LOW     5
0107 #define IXGBE_I2C_T_HIGH    4
0108 #define IXGBE_I2C_T_SU_STA  5
0109 #define IXGBE_I2C_T_HD_DATA 5
0110 #define IXGBE_I2C_T_SU_DATA 1
0111 #define IXGBE_I2C_T_RISE    1
0112 #define IXGBE_I2C_T_FALL    1
0113 #define IXGBE_I2C_T_SU_STO  4
0114 #define IXGBE_I2C_T_BUF     5
0115
0116 #define IXGBE_SFP_DETECT_RETRIES    2
0117
0118 #define IXGBE_TN_LASI_STATUS_REG        0x9005
0119 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
0120
0121 /* SFP+ SFF-8472 Compliance code */
0122 #define IXGBE_SFF_SFF_8472_UNSUP      0x00
0123
0124 s32 ixgbe_mii_bus_init(struct ixgbe_hw *hw);
0125
0126 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
0127 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
0128 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
0129                    u32 device_type, u16 *phy_data);
0130 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
0131                 u32 device_type, u16 phy_data);
0132 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
0133                u32 device_type, u16 *phy_data);
0134 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
0135                 u32 device_type, u16 phy_data);
0136 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
0137 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
0138                        ixgbe_link_speed speed,
0139                        bool autoneg_wait_to_complete);
0140 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
0141                            ixgbe_link_speed *speed,
0142                            bool *autoneg);
0143 bool ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
0144
0145 /* PHY specific */
0146 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
0147                  ixgbe_link_speed *speed,
0148                  bool *link_up);
0149 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
0150
0151 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
0152 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
0153 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
0154 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
0155 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
0156                     u16 *list_offset,
0157                     u16 *data_offset);
0158 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
0159 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
0160                 u8 dev_addr, u8 *data);
0161 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
0162                      u8 dev_addr, u8 *data);
0163 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
0164                  u8 dev_addr, u8 data);
0165 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
0166                       u8 dev_addr, u8 data);
0167 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
0168                   u8 *eeprom_data);
0169 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
0170                    u8 *sff8472_data);
0171 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
0172                    u8 eeprom_data);
0173 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
0174                     u16 *val, bool lock);
0175 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *, u8 addr, u16 reg,
0176                      u16 val, bool lock);
0177 #endif /* _IXGBE_PHY_H_ */