intel/ixgbe/ixgbe_dcb_82599.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #ifndef _DCB_82599_CONFIG_H_
0005 #define _DCB_82599_CONFIG_H_
0006
0007 /* DCB register definitions */
0008 #define IXGBE_RTTDCS_TDPAC      0x00000001 /* 0 Round Robin,
0009                         * 1 WSP - Weighted Strict Priority
0010                         */
0011 #define IXGBE_RTTDCS_VMPAC      0x00000002 /* 0 Round Robin,
0012                         * 1 WRR - Weighted Round Robin
0013                         */
0014 #define IXGBE_RTTDCS_TDRM       0x00000010 /* Transmit Recycle Mode */
0015 #define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
0016 #define IXGBE_RTTDCS_BDPM       0x00400000 /* Bypass Data Pipe - must clear! */
0017 #define IXGBE_RTTDCS_BPBFSM     0x00800000 /* Bypass PB Free Space - must
0018                          * clear!
0019                          */
0020 #define IXGBE_RTTDCS_SPEED_CHG  0x80000000 /* Link speed change */
0021
0022 /* Receive UP2TC mapping */
0023 #define IXGBE_RTRUP2TC_UP_SHIFT 3
0024 #define IXGBE_RTRUP2TC_UP_MASK  7
0025 /* Transmit UP2TC mapping */
0026 #define IXGBE_RTTUP2TC_UP_SHIFT 3
0027
0028 #define IXGBE_RTRPT4C_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
0029 #define IXGBE_RTRPT4C_BWG_SHIFT 9  /* Offset to BWG index */
0030 #define IXGBE_RTRPT4C_GSP       0x40000000 /* GSP enable bit */
0031 #define IXGBE_RTRPT4C_LSP       0x80000000 /* LSP enable bit */
0032
0033 #define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet
0034                         * buffers enable
0035                         */
0036 #define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores
0037                         * (RSS) enable
0038                         */
0039
0040 /* RTRPCS Bit Masks */
0041 #define IXGBE_RTRPCS_RRM        0x00000002 /* Receive Recycle Mode enable */
0042 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
0043 #define IXGBE_RTRPCS_RAC        0x00000004
0044 #define IXGBE_RTRPCS_ARBDIS     0x00000040 /* Arbitration disable bit */
0045
0046 /* RTTDT2C Bit Masks */
0047 #define IXGBE_RTTDT2C_MCL_SHIFT 12
0048 #define IXGBE_RTTDT2C_BWG_SHIFT 9
0049 #define IXGBE_RTTDT2C_GSP       0x40000000
0050 #define IXGBE_RTTDT2C_LSP       0x80000000
0051
0052 #define IXGBE_RTTPT2C_MCL_SHIFT 12
0053 #define IXGBE_RTTPT2C_BWG_SHIFT 9
0054 #define IXGBE_RTTPT2C_GSP       0x40000000
0055 #define IXGBE_RTTPT2C_LSP       0x80000000
0056
0057 /* RTTPCS Bit Masks */
0058 #define IXGBE_RTTPCS_TPPAC      0x00000020 /* 0 Round Robin,
0059                         * 1 SP - Strict Priority
0060                         */
0061 #define IXGBE_RTTPCS_ARBDIS     0x00000040 /* Arbiter disable */
0062 #define IXGBE_RTTPCS_TPRM       0x00000100 /* Transmit Recycle Mode enable */
0063 #define IXGBE_RTTPCS_ARBD_SHIFT 22
0064 #define IXGBE_RTTPCS_ARBD_DCB   0x4        /* Arbitration delay in DCB mode */
0065
0066 /* SECTXMINIFG DCB */
0067 #define IXGBE_SECTX_DCB     0x00001F00 /* DCB TX Buffer IFG */
0068
0069
0070 /* DCB hardware-specific driver APIs */
0071
0072 /* DCB PFC functions */
0073 s32 ixgbe_dcb_config_pfc_82599(struct ixgbe_hw *hw, u8 pfc_en, u8 *prio_tc);
0074
0075 /* DCB hw initialization */
0076 s32 ixgbe_dcb_config_rx_arbiter_82599(struct ixgbe_hw *hw,
0077                     u16 *refill,
0078                     u16 *max,
0079                     u8 *bwg_id,
0080                     u8 *prio_type,
0081                     u8 *prio_tc);
0082
0083 s32 ixgbe_dcb_config_tx_desc_arbiter_82599(struct ixgbe_hw *hw,
0084                         u16 *refill,
0085                         u16 *max,
0086                         u8 *bwg_id,
0087                         u8 *prio_type);
0088
0089 s32 ixgbe_dcb_config_tx_data_arbiter_82599(struct ixgbe_hw *hw,
0090                         u16 *refill,
0091                         u16 *max,
0092                         u8 *bwg_id,
0093                         u8 *prio_type,
0094                         u8 *prio_tc);
0095
0096 s32 ixgbe_dcb_hw_config_82599(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
0097                   u16 *max, u8 *bwg_id, u8 *prio_type,
0098                   u8 *prio_tc);
0099
0100 #endif /* _DCB_82599_CONFIG_H */