intel/ixgbe/ixgbe_dcb_82598.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #ifndef _DCB_82598_CONFIG_H_
0005 #define _DCB_82598_CONFIG_H_
0006
0007 /* DCB register definitions */
0008
0009 #define IXGBE_DPMCS_MTSOS_SHIFT 16
0010 #define IXGBE_DPMCS_TDPAC       0x00000001 /* 0 Round Robin, 1 DFP - Deficit Fixed Priority */
0011 #define IXGBE_DPMCS_TRM         0x00000010 /* Transmit Recycle Mode */
0012 #define IXGBE_DPMCS_ARBDIS      0x00000040 /* DCB arbiter disable */
0013 #define IXGBE_DPMCS_TSOEF       0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
0014
0015 #define IXGBE_RUPPBMR_MQA       0x80000000 /* Enable UP to queue mapping */
0016
0017 #define IXGBE_RT2CR_MCL_SHIFT   12 /* Offset to Max Credit Limit setting */
0018 #define IXGBE_RT2CR_LSP         0x80000000 /* LSP enable bit */
0019
0020 #define IXGBE_RDRXCTL_MPBEN     0x00000010 /* DMA config for multiple packet buffers enable */
0021 #define IXGBE_RDRXCTL_MCEN      0x00000040 /* DMA config for multiple cores (RSS) enable */
0022
0023 #define IXGBE_TDTQ2TCCR_MCL_SHIFT   12
0024 #define IXGBE_TDTQ2TCCR_BWG_SHIFT   9
0025 #define IXGBE_TDTQ2TCCR_GSP     0x40000000
0026 #define IXGBE_TDTQ2TCCR_LSP     0x80000000
0027
0028 #define IXGBE_TDPT2TCCR_MCL_SHIFT   12
0029 #define IXGBE_TDPT2TCCR_BWG_SHIFT   9
0030 #define IXGBE_TDPT2TCCR_GSP     0x40000000
0031 #define IXGBE_TDPT2TCCR_LSP     0x80000000
0032
0033 #define IXGBE_PDPMCS_TPPAC      0x00000020 /* 0 Round Robin, 1 for DFP - Deficit Fixed Priority */
0034 #define IXGBE_PDPMCS_ARBDIS     0x00000040 /* Arbiter disable */
0035 #define IXGBE_PDPMCS_TRM        0x00000100 /* Transmit Recycle Mode enable */
0036
0037 #define IXGBE_DTXCTL_ENDBUBD    0x00000004 /* Enable DBU buffer division */
0038
0039 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
0040 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
0041 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
0042 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
0043
0044 #define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000
0045
0046 /* DCB hardware-specific driver APIs */
0047
0048 /* DCB PFC functions */
0049 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8 pfc_en);
0050
0051 /* DCB hw initialization */
0052 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
0053                     u16 *refill,
0054                     u16 *max,
0055                     u8 *prio_type);
0056
0057 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
0058                         u16 *refill,
0059                         u16 *max,
0060                         u8 *bwg_id,
0061                         u8 *prio_type);
0062
0063 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
0064                         u16 *refill,
0065                         u16 *max,
0066                         u8 *bwg_id,
0067                         u8 *prio_type);
0068
0069 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
0070                   u16 *max, u8 *bwg_id, u8 *prio_type);
0071
0072 #endif /* _DCB_82598_CONFIG_H */