intel/ixgbe/ixgbe_dcb_82598.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #include "ixgbe.h"
0005 #include "ixgbe_type.h"
0006 #include "ixgbe_dcb.h"
0007 #include "ixgbe_dcb_82598.h"
0008
0009 /**
0010  * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
0011  * @hw: pointer to hardware structure
0012  * @refill: refill credits index by traffic class
0013  * @max: max credits index by traffic class
0014  * @prio_type: priority type indexed by traffic class
0015  *
0016  * Configure Rx Data Arbiter and credits for each traffic class.
0017  */
0018 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw,
0019                     u16 *refill,
0020                     u16 *max,
0021                     u8 *prio_type)
0022 {
0023     u32    reg           = 0;
0024     u32    credit_refill = 0;
0025     u32    credit_max    = 0;
0026     u8     i             = 0;
0027
0028     reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
0029     IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
0030
0031     reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
0032     /* Enable Arbiter */
0033     reg &= ~IXGBE_RMCS_ARBDIS;
0034     /* Enable Receive Recycle within the BWG */
0035     reg |= IXGBE_RMCS_RRM;
0036     /* Enable Deficit Fixed Priority arbitration*/
0037     reg |= IXGBE_RMCS_DFP;
0038
0039     IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
0040
0041     /* Configure traffic class credits and priority */
0042     for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
0043         credit_refill = refill[i];
0044         credit_max    = max[i];
0045
0046         reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
0047
0048         if (prio_type[i] == prio_link)
0049             reg |= IXGBE_RT2CR_LSP;
0050
0051         IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
0052     }
0053
0054     reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
0055     reg |= IXGBE_RDRXCTL_RDMTS_1_2;
0056     reg |= IXGBE_RDRXCTL_MPBEN;
0057     reg |= IXGBE_RDRXCTL_MCEN;
0058     IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
0059
0060     reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
0061     /* Make sure there is enough descriptors before arbitration */
0062     reg &= ~IXGBE_RXCTRL_DMBYPS;
0063     IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
0064
0065     return 0;
0066 }
0067
0068 /**
0069  * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
0070  * @hw: pointer to hardware structure
0071  * @refill: refill credits index by traffic class
0072  * @max: max credits index by traffic class
0073  * @bwg_id: bandwidth grouping indexed by traffic class
0074  * @prio_type: priority type indexed by traffic class
0075  *
0076  * Configure Tx Descriptor Arbiter and credits for each traffic class.
0077  */
0078 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
0079                         u16 *refill,
0080                         u16 *max,
0081                         u8 *bwg_id,
0082                         u8 *prio_type)
0083 {
0084     u32    reg, max_credits;
0085     u8     i;
0086
0087     reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
0088
0089     /* Enable arbiter */
0090     reg &= ~IXGBE_DPMCS_ARBDIS;
0091     reg |= IXGBE_DPMCS_TSOEF;
0092
0093     /* Configure Max TSO packet size 34KB including payload and headers */
0094     reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
0095
0096     IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
0097
0098     /* Configure traffic class credits and priority */
0099     for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
0100         max_credits = max[i];
0101         reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
0102         reg |= refill[i];
0103         reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
0104
0105         if (prio_type[i] == prio_group)
0106             reg |= IXGBE_TDTQ2TCCR_GSP;
0107
0108         if (prio_type[i] == prio_link)
0109             reg |= IXGBE_TDTQ2TCCR_LSP;
0110
0111         IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
0112     }
0113
0114     return 0;
0115 }
0116
0117 /**
0118  * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
0119  * @hw: pointer to hardware structure
0120  * @refill: refill credits index by traffic class
0121  * @max: max credits index by traffic class
0122  * @bwg_id: bandwidth grouping indexed by traffic class
0123  * @prio_type: priority type indexed by traffic class
0124  *
0125  * Configure Tx Data Arbiter and credits for each traffic class.
0126  */
0127 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
0128                         u16 *refill,
0129                         u16 *max,
0130                         u8 *bwg_id,
0131                         u8 *prio_type)
0132 {
0133     u32 reg;
0134     u8 i;
0135
0136     reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
0137     /* Enable Data Plane Arbiter */
0138     reg &= ~IXGBE_PDPMCS_ARBDIS;
0139     /* Enable DFP and Transmit Recycle Mode */
0140     reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
0141
0142     IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
0143
0144     /* Configure traffic class credits and priority */
0145     for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
0146         reg = refill[i];
0147         reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
0148         reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
0149
0150         if (prio_type[i] == prio_group)
0151             reg |= IXGBE_TDPT2TCCR_GSP;
0152
0153         if (prio_type[i] == prio_link)
0154             reg |= IXGBE_TDPT2TCCR_LSP;
0155
0156         IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
0157     }
0158
0159     /* Enable Tx packet buffer division */
0160     reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
0161     reg |= IXGBE_DTXCTL_ENDBUBD;
0162     IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
0163
0164     return 0;
0165 }
0166
0167 /**
0168  * ixgbe_dcb_config_pfc_82598 - Config priority flow control
0169  * @hw: pointer to hardware structure
0170  * @pfc_en: enabled pfc bitmask
0171  *
0172  * Configure Priority Flow Control for each traffic class.
0173  */
0174 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
0175 {
0176     u32 fcrtl, reg;
0177     u8  i;
0178
0179     /* Enable Transmit Priority Flow Control */
0180     reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
0181     reg &= ~IXGBE_RMCS_TFCE_802_3X;
0182     reg |= IXGBE_RMCS_TFCE_PRIORITY;
0183     IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
0184
0185     /* Enable Receive Priority Flow Control */
0186     reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
0187     reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
0188
0189     if (pfc_en)
0190         reg |= IXGBE_FCTRL_RPFCE;
0191
0192     IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
0193
0194     /* Configure PFC Tx thresholds per TC */
0195     for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
0196         if (!(pfc_en & BIT(i))) {
0197             IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
0198             IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
0199             continue;
0200         }
0201
0202         fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
0203         reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
0204         IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
0205         IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
0206     }
0207
0208     /* Configure pause time */
0209     reg = hw->fc.pause_time * 0x00010001;
0210     for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
0211         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
0212
0213     /* Configure flow control refresh threshold value */
0214     IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
0215
0216
0217     return 0;
0218 }
0219
0220 /**
0221  * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
0222  * @hw: pointer to hardware structure
0223  *
0224  * Configure queue statistics registers, all queues belonging to same traffic
0225  * class uses a single set of queue statistics counters.
0226  */
0227 static s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
0228 {
0229     u32 reg = 0;
0230     u8  i   = 0;
0231     u8  j   = 0;
0232
0233     /* Receive Queues stats setting -  8 queues per statistics reg */
0234     for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
0235         reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
0236         reg |= ((0x1010101) * j);
0237         IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
0238         reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
0239         reg |= ((0x1010101) * j);
0240         IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
0241     }
0242     /* Transmit Queues stats setting -  4 queues per statistics reg */
0243     for (i = 0; i < 8; i++) {
0244         reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
0245         reg |= ((0x1010101) * i);
0246         IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
0247     }
0248
0249     return 0;
0250 }
0251
0252 /**
0253  * ixgbe_dcb_hw_config_82598 - Config and enable DCB
0254  * @hw: pointer to hardware structure
0255  * @pfc_en: enabled pfc bitmask
0256  * @refill: refill credits index by traffic class
0257  * @max: max credits index by traffic class
0258  * @bwg_id: bandwidth grouping indexed by traffic class
0259  * @prio_type: priority type indexed by traffic class
0260  *
0261  * Configure dcb settings and enable dcb mode.
0262  */
0263 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, u8 pfc_en, u16 *refill,
0264                   u16 *max, u8 *bwg_id, u8 *prio_type)
0265 {
0266     ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, prio_type);
0267     ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
0268                            bwg_id, prio_type);
0269     ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
0270                            bwg_id, prio_type);
0271     ixgbe_dcb_config_pfc_82598(hw, pfc_en);
0272     ixgbe_dcb_config_tc_stats_82598(hw);
0273
0274     return 0;
0275 }