intel/ixgbe/ixgbe_dcb.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #ifndef _DCB_CONFIG_H_
0005 #define _DCB_CONFIG_H_
0006
0007 #include <linux/dcbnl.h>
0008 #include "ixgbe_type.h"
0009
0010 /* DCB data structures */
0011
0012 #define IXGBE_MAX_PACKET_BUFFERS 8
0013 #define MAX_USER_PRIORITY        8
0014 #define MAX_BW_GROUP             8
0015 #define BW_PERCENT               100
0016
0017 #define DCB_TX_CONFIG            0
0018 #define DCB_RX_CONFIG            1
0019
0020 /* DCB error Codes */
0021 #define DCB_SUCCESS              0
0022 #define DCB_ERR_CONFIG           -1
0023 #define DCB_ERR_PARAM            -2
0024
0025 /* Transmit and receive Errors */
0026 /* Error in bandwidth group allocation */
0027 #define DCB_ERR_BW_GROUP        -3
0028 /* Error in traffic class bandwidth allocation */
0029 #define DCB_ERR_TC_BW           -4
0030 /* Traffic class has both link strict and group strict enabled */
0031 #define DCB_ERR_LS_GS           -5
0032 /* Link strict traffic class has non zero bandwidth */
0033 #define DCB_ERR_LS_BW_NONZERO   -6
0034 /* Link strict bandwidth group has non zero bandwidth */
0035 #define DCB_ERR_LS_BWG_NONZERO  -7
0036 /*  Traffic class has zero bandwidth */
0037 #define DCB_ERR_TC_BW_ZERO      -8
0038
0039 #define DCB_NOT_IMPLEMENTED      0x7FFFFFFF
0040
0041 struct dcb_pfc_tc_debug {
0042     u8  tc;
0043     u8  pause_status;
0044     u64 pause_quanta;
0045 };
0046
0047 enum strict_prio_type {
0048     prio_none = 0,
0049     prio_group,
0050     prio_link
0051 };
0052
0053 /* DCB capability definitions */
0054 #define IXGBE_DCB_PG_SUPPORT        0x00000001
0055 #define IXGBE_DCB_PFC_SUPPORT       0x00000002
0056 #define IXGBE_DCB_BCN_SUPPORT       0x00000004
0057 #define IXGBE_DCB_UP2TC_SUPPORT     0x00000008
0058 #define IXGBE_DCB_GSP_SUPPORT       0x00000010
0059
0060 #define IXGBE_DCB_8_TC_SUPPORT      0x80
0061
0062 struct dcb_support {
0063     /* DCB capabilities */
0064     u32 capabilities;
0065
0066     /* Each bit represents a number of TCs configurable in the hw.
0067      * If 8 traffic classes can be configured, the value is 0x80.
0068      */
0069     u8  traffic_classes;
0070     u8  pfc_traffic_classes;
0071 };
0072
0073 /* Traffic class bandwidth allocation per direction */
0074 struct tc_bw_alloc {
0075     u8 bwg_id;        /* Bandwidth Group (BWG) ID */
0076     u8 bwg_percent;       /* % of BWG's bandwidth */
0077     u8 link_percent;      /* % of link bandwidth */
0078     u8 up_to_tc_bitmap;   /* User Priority to Traffic Class mapping */
0079     u16 data_credits_refill;  /* Credit refill amount in 64B granularity */
0080     u16 data_credits_max;     /* Max credits for a configured packet buffer
0081                    * in 64B granularity.*/
0082     enum strict_prio_type prio_type; /* Link or Group Strict Priority */
0083 };
0084
0085 enum dcb_pfc_type {
0086     pfc_disabled = 0,
0087     pfc_enabled_full,
0088     pfc_enabled_tx,
0089     pfc_enabled_rx
0090 };
0091
0092 /* Traffic class configuration */
0093 struct tc_configuration {
0094     struct tc_bw_alloc path[2]; /* One each for Tx/Rx */
0095     enum dcb_pfc_type  dcb_pfc; /* Class based flow control setting */
0096
0097     u16 desc_credits_max; /* For Tx Descriptor arbitration */
0098     u8 tc; /* Traffic class (TC) */
0099 };
0100
0101 struct dcb_num_tcs {
0102     u8 pg_tcs;
0103     u8 pfc_tcs;
0104 };
0105
0106 struct ixgbe_dcb_config {
0107     struct dcb_support support;
0108     struct dcb_num_tcs num_tcs;
0109     struct tc_configuration tc_config[MAX_TRAFFIC_CLASS];
0110     u8     bw_percentage[2][MAX_BW_GROUP]; /* One each for Tx/Rx */
0111     bool   pfc_mode_enable;
0112
0113     u32  dcb_cfg_version; /* Not used...OS-specific? */
0114     u32  link_speed; /* For bandwidth allocation validation purpose */
0115 };
0116
0117 /* DCB driver APIs */
0118 void ixgbe_dcb_unpack_pfc(struct ixgbe_dcb_config *cfg, u8 *pfc_en);
0119 void ixgbe_dcb_unpack_refill(struct ixgbe_dcb_config *, int, u16 *);
0120 void ixgbe_dcb_unpack_max(struct ixgbe_dcb_config *, u16 *);
0121 void ixgbe_dcb_unpack_bwgid(struct ixgbe_dcb_config *, int, u8 *);
0122 void ixgbe_dcb_unpack_prio(struct ixgbe_dcb_config *, int, u8 *);
0123 void ixgbe_dcb_unpack_map(struct ixgbe_dcb_config *, int, u8 *);
0124 u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *, int, u8);
0125
0126 /* DCB credits calculation */
0127 s32 ixgbe_dcb_calculate_tc_credits(struct ixgbe_hw *,
0128                    struct ixgbe_dcb_config *, int, u8);
0129
0130 /* DCB hw initialization */
0131 s32 ixgbe_dcb_hw_ets(struct ixgbe_hw *hw, struct ieee_ets *ets, int max);
0132 s32 ixgbe_dcb_hw_ets_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
0133                 u8 *bwg_id, u8 *prio_type, u8 *tc_prio);
0134 s32 ixgbe_dcb_hw_pfc_config(struct ixgbe_hw *hw, u8 pfc_en, u8 *tc_prio);
0135 s32 ixgbe_dcb_hw_config(struct ixgbe_hw *, struct ixgbe_dcb_config *);
0136
0137 void ixgbe_dcb_read_rtrup2tc(struct ixgbe_hw *hw, u8 *map);
0138
0139 /* DCB definitions for credit calculation */
0140 #define DCB_CREDIT_QUANTUM  64   /* DCB Quantum */
0141 #define MAX_CREDIT_REFILL       511  /* 0x1FF * 64B = 32704B */
0142 #define DCB_MAX_TSO_SIZE        (32*1024) /* MAX TSO packet size supported in DCB mode */
0143 #define MINIMUM_CREDIT_FOR_TSO  (DCB_MAX_TSO_SIZE/64 + 1) /* 513 for 32KB TSO packet */
0144 #define MAX_CREDIT              4095 /* Maximum credit supported: 256KB * 1204 / 64B */
0145
0146 #endif /* _DCB_CONFIG_H */