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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003 
0004 #include <linux/pci.h>
0005 #include <linux/delay.h>
0006 #include <linux/sched.h>
0007 
0008 #include "ixgbe.h"
0009 #include "ixgbe_phy.h"
0010 
0011 #define IXGBE_82598_MAX_TX_QUEUES 32
0012 #define IXGBE_82598_MAX_RX_QUEUES 64
0013 #define IXGBE_82598_RAR_ENTRIES   16
0014 #define IXGBE_82598_MC_TBL_SIZE  128
0015 #define IXGBE_82598_VFT_TBL_SIZE 128
0016 #define IXGBE_82598_RX_PB_SIZE   512
0017 
0018 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
0019                      ixgbe_link_speed speed,
0020                      bool autoneg_wait_to_complete);
0021 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
0022                        u8 *eeprom_data);
0023 
0024 /**
0025  *  ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
0026  *  @hw: pointer to the HW structure
0027  *
0028  *  The defaults for 82598 should be in the range of 50us to 50ms,
0029  *  however the hardware default for these parts is 500us to 1ms which is less
0030  *  than the 10ms recommended by the pci-e spec.  To address this we need to
0031  *  increase the value to either 10ms to 250ms for capability version 1 config,
0032  *  or 16ms to 55ms for version 2.
0033  **/
0034 static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
0035 {
0036     u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
0037     u16 pcie_devctl2;
0038 
0039     if (ixgbe_removed(hw->hw_addr))
0040         return;
0041 
0042     /* only take action if timeout value is defaulted to 0 */
0043     if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
0044         goto out;
0045 
0046     /*
0047      * if capababilities version is type 1 we can write the
0048      * timeout of 10ms to 250ms through the GCR register
0049      */
0050     if (!(gcr & IXGBE_GCR_CAP_VER2)) {
0051         gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
0052         goto out;
0053     }
0054 
0055     /*
0056      * for version 2 capabilities we need to write the config space
0057      * directly in order to set the completion timeout value for
0058      * 16ms to 55ms
0059      */
0060     pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
0061     pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
0062     ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
0063 out:
0064     /* disable completion timeout resend */
0065     gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
0066     IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
0067 }
0068 
0069 static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
0070 {
0071     struct ixgbe_mac_info *mac = &hw->mac;
0072 
0073     /* Call PHY identify routine to get the phy type */
0074     ixgbe_identify_phy_generic(hw);
0075 
0076     mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
0077     mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
0078     mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
0079     mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
0080     mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
0081     mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
0082     mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
0083 
0084     return 0;
0085 }
0086 
0087 /**
0088  *  ixgbe_init_phy_ops_82598 - PHY/SFP specific init
0089  *  @hw: pointer to hardware structure
0090  *
0091  *  Initialize any function pointers that were not able to be
0092  *  set during get_invariants because the PHY/SFP type was
0093  *  not known.  Perform the SFP init if necessary.
0094  *
0095  **/
0096 static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
0097 {
0098     struct ixgbe_mac_info *mac = &hw->mac;
0099     struct ixgbe_phy_info *phy = &hw->phy;
0100     s32 ret_val;
0101     u16 list_offset, data_offset;
0102 
0103     /* Identify the PHY */
0104     phy->ops.identify(hw);
0105 
0106     /* Overwrite the link function pointers if copper PHY */
0107     if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
0108         mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
0109         mac->ops.get_link_capabilities =
0110             &ixgbe_get_copper_link_capabilities_generic;
0111     }
0112 
0113     switch (hw->phy.type) {
0114     case ixgbe_phy_tn:
0115         phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
0116         phy->ops.check_link = &ixgbe_check_phy_link_tnx;
0117         break;
0118     case ixgbe_phy_nl:
0119         phy->ops.reset = &ixgbe_reset_phy_nl;
0120 
0121         /* Call SFP+ identify routine to get the SFP+ module type */
0122         ret_val = phy->ops.identify_sfp(hw);
0123         if (ret_val)
0124             return ret_val;
0125         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
0126             return IXGBE_ERR_SFP_NOT_SUPPORTED;
0127 
0128         /* Check to see if SFP+ module is supported */
0129         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
0130                                 &list_offset,
0131                                 &data_offset);
0132         if (ret_val)
0133             return IXGBE_ERR_SFP_NOT_SUPPORTED;
0134         break;
0135     default:
0136         break;
0137     }
0138 
0139     return 0;
0140 }
0141 
0142 /**
0143  *  ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
0144  *  @hw: pointer to hardware structure
0145  *
0146  *  Starts the hardware using the generic start_hw function.
0147  *  Disables relaxed ordering for archs other than SPARC
0148  *  Then set pcie completion timeout
0149  *
0150  **/
0151 static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
0152 {
0153     s32 ret_val;
0154 
0155     ret_val = ixgbe_start_hw_generic(hw);
0156     if (ret_val)
0157         return ret_val;
0158 
0159     /* set the completion timeout for interface */
0160     ixgbe_set_pcie_completion_timeout(hw);
0161 
0162     return 0;
0163 }
0164 
0165 /**
0166  *  ixgbe_get_link_capabilities_82598 - Determines link capabilities
0167  *  @hw: pointer to hardware structure
0168  *  @speed: pointer to link speed
0169  *  @autoneg: boolean auto-negotiation value
0170  *
0171  *  Determines the link capabilities by reading the AUTOC register.
0172  **/
0173 static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
0174                          ixgbe_link_speed *speed,
0175                          bool *autoneg)
0176 {
0177     u32 autoc = 0;
0178 
0179     /*
0180      * Determine link capabilities based on the stored value of AUTOC,
0181      * which represents EEPROM defaults.  If AUTOC value has not been
0182      * stored, use the current register value.
0183      */
0184     if (hw->mac.orig_link_settings_stored)
0185         autoc = hw->mac.orig_autoc;
0186     else
0187         autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
0188 
0189     switch (autoc & IXGBE_AUTOC_LMS_MASK) {
0190     case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
0191         *speed = IXGBE_LINK_SPEED_1GB_FULL;
0192         *autoneg = false;
0193         break;
0194 
0195     case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
0196         *speed = IXGBE_LINK_SPEED_10GB_FULL;
0197         *autoneg = false;
0198         break;
0199 
0200     case IXGBE_AUTOC_LMS_1G_AN:
0201         *speed = IXGBE_LINK_SPEED_1GB_FULL;
0202         *autoneg = true;
0203         break;
0204 
0205     case IXGBE_AUTOC_LMS_KX4_AN:
0206     case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
0207         *speed = IXGBE_LINK_SPEED_UNKNOWN;
0208         if (autoc & IXGBE_AUTOC_KX4_SUPP)
0209             *speed |= IXGBE_LINK_SPEED_10GB_FULL;
0210         if (autoc & IXGBE_AUTOC_KX_SUPP)
0211             *speed |= IXGBE_LINK_SPEED_1GB_FULL;
0212         *autoneg = true;
0213         break;
0214 
0215     default:
0216         return IXGBE_ERR_LINK_SETUP;
0217     }
0218 
0219     return 0;
0220 }
0221 
0222 /**
0223  *  ixgbe_get_media_type_82598 - Determines media type
0224  *  @hw: pointer to hardware structure
0225  *
0226  *  Returns the media type (fiber, copper, backplane)
0227  **/
0228 static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
0229 {
0230     /* Detect if there is a copper PHY attached. */
0231     switch (hw->phy.type) {
0232     case ixgbe_phy_cu_unknown:
0233     case ixgbe_phy_tn:
0234         return ixgbe_media_type_copper;
0235 
0236     default:
0237         break;
0238     }
0239 
0240     /* Media type for I82598 is based on device ID */
0241     switch (hw->device_id) {
0242     case IXGBE_DEV_ID_82598:
0243     case IXGBE_DEV_ID_82598_BX:
0244         /* Default device ID is mezzanine card KX/KX4 */
0245         return ixgbe_media_type_backplane;
0246 
0247     case IXGBE_DEV_ID_82598AF_DUAL_PORT:
0248     case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
0249     case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
0250     case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
0251     case IXGBE_DEV_ID_82598EB_XF_LR:
0252     case IXGBE_DEV_ID_82598EB_SFP_LOM:
0253         return ixgbe_media_type_fiber;
0254 
0255     case IXGBE_DEV_ID_82598EB_CX4:
0256     case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
0257         return ixgbe_media_type_cx4;
0258 
0259     case IXGBE_DEV_ID_82598AT:
0260     case IXGBE_DEV_ID_82598AT2:
0261         return ixgbe_media_type_copper;
0262 
0263     default:
0264         return ixgbe_media_type_unknown;
0265     }
0266 }
0267 
0268 /**
0269  *  ixgbe_fc_enable_82598 - Enable flow control
0270  *  @hw: pointer to hardware structure
0271  *
0272  *  Enable flow control according to the current settings.
0273  **/
0274 static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
0275 {
0276     u32 fctrl_reg;
0277     u32 rmcs_reg;
0278     u32 reg;
0279     u32 fcrtl, fcrth;
0280     u32 link_speed = 0;
0281     int i;
0282     bool link_up;
0283 
0284     /* Validate the water mark configuration */
0285     if (!hw->fc.pause_time)
0286         return IXGBE_ERR_INVALID_LINK_SETTINGS;
0287 
0288     /* Low water mark of zero causes XOFF floods */
0289     for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
0290         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
0291             hw->fc.high_water[i]) {
0292             if (!hw->fc.low_water[i] ||
0293                 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
0294                 hw_dbg(hw, "Invalid water mark configuration\n");
0295                 return IXGBE_ERR_INVALID_LINK_SETTINGS;
0296             }
0297         }
0298     }
0299 
0300     /*
0301      * On 82598 having Rx FC on causes resets while doing 1G
0302      * so if it's on turn it off once we know link_speed. For
0303      * more details see 82598 Specification update.
0304      */
0305     hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
0306     if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
0307         switch (hw->fc.requested_mode) {
0308         case ixgbe_fc_full:
0309             hw->fc.requested_mode = ixgbe_fc_tx_pause;
0310             break;
0311         case ixgbe_fc_rx_pause:
0312             hw->fc.requested_mode = ixgbe_fc_none;
0313             break;
0314         default:
0315             /* no change */
0316             break;
0317         }
0318     }
0319 
0320     /* Negotiate the fc mode to use */
0321     hw->mac.ops.fc_autoneg(hw);
0322 
0323     /* Disable any previous flow control settings */
0324     fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
0325     fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
0326 
0327     rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
0328     rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
0329 
0330     /*
0331      * The possible values of fc.current_mode are:
0332      * 0: Flow control is completely disabled
0333      * 1: Rx flow control is enabled (we can receive pause frames,
0334      *    but not send pause frames).
0335      * 2: Tx flow control is enabled (we can send pause frames but
0336      *     we do not support receiving pause frames).
0337      * 3: Both Rx and Tx flow control (symmetric) are enabled.
0338      * other: Invalid.
0339      */
0340     switch (hw->fc.current_mode) {
0341     case ixgbe_fc_none:
0342         /*
0343          * Flow control is disabled by software override or autoneg.
0344          * The code below will actually disable it in the HW.
0345          */
0346         break;
0347     case ixgbe_fc_rx_pause:
0348         /*
0349          * Rx Flow control is enabled and Tx Flow control is
0350          * disabled by software override. Since there really
0351          * isn't a way to advertise that we are capable of RX
0352          * Pause ONLY, we will advertise that we support both
0353          * symmetric and asymmetric Rx PAUSE.  Later, we will
0354          * disable the adapter's ability to send PAUSE frames.
0355          */
0356         fctrl_reg |= IXGBE_FCTRL_RFCE;
0357         break;
0358     case ixgbe_fc_tx_pause:
0359         /*
0360          * Tx Flow control is enabled, and Rx Flow control is
0361          * disabled by software override.
0362          */
0363         rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
0364         break;
0365     case ixgbe_fc_full:
0366         /* Flow control (both Rx and Tx) is enabled by SW override. */
0367         fctrl_reg |= IXGBE_FCTRL_RFCE;
0368         rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
0369         break;
0370     default:
0371         hw_dbg(hw, "Flow control param set incorrectly\n");
0372         return IXGBE_ERR_CONFIG;
0373     }
0374 
0375     /* Set 802.3x based flow control settings. */
0376     fctrl_reg |= IXGBE_FCTRL_DPF;
0377     IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
0378     IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
0379 
0380     /* Set up and enable Rx high/low water mark thresholds, enable XON. */
0381     for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
0382         if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
0383             hw->fc.high_water[i]) {
0384             fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
0385             fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
0386             IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
0387             IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
0388         } else {
0389             IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
0390             IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
0391         }
0392 
0393     }
0394 
0395     /* Configure pause time (2 TCs per register) */
0396     reg = hw->fc.pause_time * 0x00010001;
0397     for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
0398         IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
0399 
0400     /* Configure flow control refresh threshold value */
0401     IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
0402 
0403     return 0;
0404 }
0405 
0406 /**
0407  *  ixgbe_start_mac_link_82598 - Configures MAC link settings
0408  *  @hw: pointer to hardware structure
0409  *  @autoneg_wait_to_complete: true when waiting for completion is needed
0410  *
0411  *  Configures link settings based on values in the ixgbe_hw struct.
0412  *  Restarts the link.  Performs autonegotiation if needed.
0413  **/
0414 static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
0415                       bool autoneg_wait_to_complete)
0416 {
0417     u32 autoc_reg;
0418     u32 links_reg;
0419     u32 i;
0420     s32 status = 0;
0421 
0422     /* Restart link */
0423     autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
0424     autoc_reg |= IXGBE_AUTOC_AN_RESTART;
0425     IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
0426 
0427     /* Only poll for autoneg to complete if specified to do so */
0428     if (autoneg_wait_to_complete) {
0429         if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
0430              IXGBE_AUTOC_LMS_KX4_AN ||
0431             (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
0432              IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
0433             links_reg = 0; /* Just in case Autoneg time = 0 */
0434             for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
0435                 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
0436                 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
0437                     break;
0438                 msleep(100);
0439             }
0440             if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
0441                 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
0442                 hw_dbg(hw, "Autonegotiation did not complete.\n");
0443             }
0444         }
0445     }
0446 
0447     /* Add delay to filter out noises during initial link setup */
0448     msleep(50);
0449 
0450     return status;
0451 }
0452 
0453 /**
0454  *  ixgbe_validate_link_ready - Function looks for phy link
0455  *  @hw: pointer to hardware structure
0456  *
0457  *  Function indicates success when phy link is available. If phy is not ready
0458  *  within 5 seconds of MAC indicating link, the function returns error.
0459  **/
0460 static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
0461 {
0462     u32 timeout;
0463     u16 an_reg;
0464 
0465     if (hw->device_id != IXGBE_DEV_ID_82598AT2)
0466         return 0;
0467 
0468     for (timeout = 0;
0469          timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
0470         hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
0471 
0472         if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
0473             (an_reg & MDIO_STAT1_LSTATUS))
0474             break;
0475 
0476         msleep(100);
0477     }
0478 
0479     if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
0480         hw_dbg(hw, "Link was indicated but link is down\n");
0481         return IXGBE_ERR_LINK_SETUP;
0482     }
0483 
0484     return 0;
0485 }
0486 
0487 /**
0488  *  ixgbe_check_mac_link_82598 - Get link/speed status
0489  *  @hw: pointer to hardware structure
0490  *  @speed: pointer to link speed
0491  *  @link_up: true is link is up, false otherwise
0492  *  @link_up_wait_to_complete: bool used to wait for link up or not
0493  *
0494  *  Reads the links register to determine if link is up and the current speed
0495  **/
0496 static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
0497                       ixgbe_link_speed *speed, bool *link_up,
0498                       bool link_up_wait_to_complete)
0499 {
0500     u32 links_reg;
0501     u32 i;
0502     u16 link_reg, adapt_comp_reg;
0503 
0504     /*
0505      * SERDES PHY requires us to read link status from register 0xC79F.
0506      * Bit 0 set indicates link is up/ready; clear indicates link down.
0507      * 0xC00C is read to check that the XAUI lanes are active.  Bit 0
0508      * clear indicates active; set indicates inactive.
0509      */
0510     if (hw->phy.type == ixgbe_phy_nl) {
0511         hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
0512         hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
0513         hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
0514                      &adapt_comp_reg);
0515         if (link_up_wait_to_complete) {
0516             for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
0517                 if ((link_reg & 1) &&
0518                     ((adapt_comp_reg & 1) == 0)) {
0519                     *link_up = true;
0520                     break;
0521                 } else {
0522                     *link_up = false;
0523                 }
0524                 msleep(100);
0525                 hw->phy.ops.read_reg(hw, 0xC79F,
0526                              MDIO_MMD_PMAPMD,
0527                              &link_reg);
0528                 hw->phy.ops.read_reg(hw, 0xC00C,
0529                              MDIO_MMD_PMAPMD,
0530                              &adapt_comp_reg);
0531             }
0532         } else {
0533             if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
0534                 *link_up = true;
0535             else
0536                 *link_up = false;
0537         }
0538 
0539         if (!*link_up)
0540             return 0;
0541     }
0542 
0543     links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
0544     if (link_up_wait_to_complete) {
0545         for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
0546             if (links_reg & IXGBE_LINKS_UP) {
0547                 *link_up = true;
0548                 break;
0549             } else {
0550                 *link_up = false;
0551             }
0552             msleep(100);
0553             links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
0554         }
0555     } else {
0556         if (links_reg & IXGBE_LINKS_UP)
0557             *link_up = true;
0558         else
0559             *link_up = false;
0560     }
0561 
0562     if (links_reg & IXGBE_LINKS_SPEED)
0563         *speed = IXGBE_LINK_SPEED_10GB_FULL;
0564     else
0565         *speed = IXGBE_LINK_SPEED_1GB_FULL;
0566 
0567     if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up &&
0568         (ixgbe_validate_link_ready(hw) != 0))
0569         *link_up = false;
0570 
0571     return 0;
0572 }
0573 
0574 /**
0575  *  ixgbe_setup_mac_link_82598 - Set MAC link speed
0576  *  @hw: pointer to hardware structure
0577  *  @speed: new link speed
0578  *  @autoneg_wait_to_complete: true when waiting for completion is needed
0579  *
0580  *  Set the link speed in the AUTOC register and restarts link.
0581  **/
0582 static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
0583                       ixgbe_link_speed speed,
0584                       bool autoneg_wait_to_complete)
0585 {
0586     bool         autoneg       = false;
0587     ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
0588     u32              curr_autoc        = IXGBE_READ_REG(hw, IXGBE_AUTOC);
0589     u32              autoc             = curr_autoc;
0590     u32              link_mode         = autoc & IXGBE_AUTOC_LMS_MASK;
0591 
0592     /* Check to see if speed passed in is supported. */
0593     ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
0594     speed &= link_capabilities;
0595 
0596     if (speed == IXGBE_LINK_SPEED_UNKNOWN)
0597         return IXGBE_ERR_LINK_SETUP;
0598 
0599     /* Set KX4/KX support according to speed requested */
0600     else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
0601          link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
0602         autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
0603         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
0604             autoc |= IXGBE_AUTOC_KX4_SUPP;
0605         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
0606             autoc |= IXGBE_AUTOC_KX_SUPP;
0607         if (autoc != curr_autoc)
0608             IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
0609     }
0610 
0611     /* Setup and restart the link based on the new values in
0612      * ixgbe_hw This will write the AUTOC register based on the new
0613      * stored values
0614      */
0615     return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
0616 }
0617 
0618 
0619 /**
0620  *  ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
0621  *  @hw: pointer to hardware structure
0622  *  @speed: new link speed
0623  *  @autoneg_wait_to_complete: true if waiting is needed to complete
0624  *
0625  *  Sets the link speed in the AUTOC register in the MAC and restarts link.
0626  **/
0627 static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
0628                            ixgbe_link_speed speed,
0629                            bool autoneg_wait_to_complete)
0630 {
0631     s32 status;
0632 
0633     /* Setup the PHY according to input speed */
0634     status = hw->phy.ops.setup_link_speed(hw, speed,
0635                           autoneg_wait_to_complete);
0636     /* Set up MAC */
0637     ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
0638 
0639     return status;
0640 }
0641 
0642 /**
0643  *  ixgbe_reset_hw_82598 - Performs hardware reset
0644  *  @hw: pointer to hardware structure
0645  *
0646  *  Resets the hardware by resetting the transmit and receive units, masks and
0647  *  clears all interrupts, performing a PHY reset, and performing a link (MAC)
0648  *  reset.
0649  **/
0650 static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
0651 {
0652     s32 status;
0653     s32 phy_status = 0;
0654     u32 ctrl;
0655     u32 gheccr;
0656     u32 i;
0657     u32 autoc;
0658     u8  analog_val;
0659 
0660     /* Call adapter stop to disable tx/rx and clear interrupts */
0661     status = hw->mac.ops.stop_adapter(hw);
0662     if (status)
0663         return status;
0664 
0665     /*
0666      * Power up the Atlas Tx lanes if they are currently powered down.
0667      * Atlas Tx lanes are powered down for MAC loopback tests, but
0668      * they are not automatically restored on reset.
0669      */
0670     hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
0671     if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
0672         /* Enable Tx Atlas so packets can be transmitted again */
0673         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
0674                          &analog_val);
0675         analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
0676         hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
0677                           analog_val);
0678 
0679         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
0680                          &analog_val);
0681         analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
0682         hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
0683                           analog_val);
0684 
0685         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
0686                          &analog_val);
0687         analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
0688         hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
0689                           analog_val);
0690 
0691         hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
0692                          &analog_val);
0693         analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
0694         hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
0695                           analog_val);
0696     }
0697 
0698     /* Reset PHY */
0699     if (hw->phy.reset_disable == false) {
0700         /* PHY ops must be identified and initialized prior to reset */
0701 
0702         /* Init PHY and function pointers, perform SFP setup */
0703         phy_status = hw->phy.ops.init(hw);
0704         if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
0705             return phy_status;
0706         if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
0707             goto mac_reset_top;
0708 
0709         hw->phy.ops.reset(hw);
0710     }
0711 
0712 mac_reset_top:
0713     /*
0714      * Issue global reset to the MAC.  This needs to be a SW reset.
0715      * If link reset is used, it might reset the MAC when mng is using it
0716      */
0717     ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
0718     IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
0719     IXGBE_WRITE_FLUSH(hw);
0720     usleep_range(1000, 1200);
0721 
0722     /* Poll for reset bit to self-clear indicating reset is complete */
0723     for (i = 0; i < 10; i++) {
0724         ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
0725         if (!(ctrl & IXGBE_CTRL_RST))
0726             break;
0727         udelay(1);
0728     }
0729     if (ctrl & IXGBE_CTRL_RST) {
0730         status = IXGBE_ERR_RESET_FAILED;
0731         hw_dbg(hw, "Reset polling failed to complete.\n");
0732     }
0733 
0734     msleep(50);
0735 
0736     /*
0737      * Double resets are required for recovery from certain error
0738      * conditions.  Between resets, it is necessary to stall to allow time
0739      * for any pending HW events to complete.
0740      */
0741     if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
0742         hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
0743         goto mac_reset_top;
0744     }
0745 
0746     gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
0747     gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6));
0748     IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
0749 
0750     /*
0751      * Store the original AUTOC value if it has not been
0752      * stored off yet.  Otherwise restore the stored original
0753      * AUTOC value since the reset operation sets back to deaults.
0754      */
0755     autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
0756     if (hw->mac.orig_link_settings_stored == false) {
0757         hw->mac.orig_autoc = autoc;
0758         hw->mac.orig_link_settings_stored = true;
0759     } else if (autoc != hw->mac.orig_autoc) {
0760         IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
0761     }
0762 
0763     /* Store the permanent mac address */
0764     hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
0765 
0766     /*
0767      * Store MAC address from RAR0, clear receive address registers, and
0768      * clear the multicast table
0769      */
0770     hw->mac.ops.init_rx_addrs(hw);
0771 
0772     if (phy_status)
0773         status = phy_status;
0774 
0775     return status;
0776 }
0777 
0778 /**
0779  *  ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
0780  *  @hw: pointer to hardware struct
0781  *  @rar: receive address register index to associate with a VMDq index
0782  *  @vmdq: VMDq set index
0783  **/
0784 static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
0785 {
0786     u32 rar_high;
0787     u32 rar_entries = hw->mac.num_rar_entries;
0788 
0789     /* Make sure we are using a valid rar index range */
0790     if (rar >= rar_entries) {
0791         hw_dbg(hw, "RAR index %d is out of range.\n", rar);
0792         return IXGBE_ERR_INVALID_ARGUMENT;
0793     }
0794 
0795     rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
0796     rar_high &= ~IXGBE_RAH_VIND_MASK;
0797     rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
0798     IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
0799     return 0;
0800 }
0801 
0802 /**
0803  *  ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
0804  *  @hw: pointer to hardware struct
0805  *  @rar: receive address register index to associate with a VMDq index
0806  *  @vmdq: VMDq clear index (not used in 82598, but elsewhere)
0807  **/
0808 static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
0809 {
0810     u32 rar_high;
0811     u32 rar_entries = hw->mac.num_rar_entries;
0812 
0813 
0814     /* Make sure we are using a valid rar index range */
0815     if (rar >= rar_entries) {
0816         hw_dbg(hw, "RAR index %d is out of range.\n", rar);
0817         return IXGBE_ERR_INVALID_ARGUMENT;
0818     }
0819 
0820     rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
0821     if (rar_high & IXGBE_RAH_VIND_MASK) {
0822         rar_high &= ~IXGBE_RAH_VIND_MASK;
0823         IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
0824     }
0825 
0826     return 0;
0827 }
0828 
0829 /**
0830  *  ixgbe_set_vfta_82598 - Set VLAN filter table
0831  *  @hw: pointer to hardware structure
0832  *  @vlan: VLAN id to write to VLAN filter
0833  *  @vind: VMDq output index that maps queue to VLAN id in VFTA
0834  *  @vlan_on: boolean flag to turn on/off VLAN in VFTA
0835  *  @vlvf_bypass: boolean flag - unused
0836  *
0837  *  Turn on/off specified VLAN in the VLAN filter table.
0838  **/
0839 static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
0840                 bool vlan_on, bool vlvf_bypass)
0841 {
0842     u32 regindex;
0843     u32 bitindex;
0844     u32 bits;
0845     u32 vftabyte;
0846 
0847     if (vlan > 4095)
0848         return IXGBE_ERR_PARAM;
0849 
0850     /* Determine 32-bit word position in array */
0851     regindex = (vlan >> 5) & 0x7F;   /* upper seven bits */
0852 
0853     /* Determine the location of the (VMD) queue index */
0854     vftabyte =  ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
0855     bitindex = (vlan & 0x7) << 2;    /* lower 3 bits indicate nibble */
0856 
0857     /* Set the nibble for VMD queue index */
0858     bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
0859     bits &= (~(0x0F << bitindex));
0860     bits |= (vind << bitindex);
0861     IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
0862 
0863     /* Determine the location of the bit for this VLAN id */
0864     bitindex = vlan & 0x1F;   /* lower five bits */
0865 
0866     bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
0867     if (vlan_on)
0868         /* Turn on this VLAN id */
0869         bits |= BIT(bitindex);
0870     else
0871         /* Turn off this VLAN id */
0872         bits &= ~BIT(bitindex);
0873     IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
0874 
0875     return 0;
0876 }
0877 
0878 /**
0879  *  ixgbe_clear_vfta_82598 - Clear VLAN filter table
0880  *  @hw: pointer to hardware structure
0881  *
0882  *  Clears the VLAN filter table, and the VMDq index associated with the filter
0883  **/
0884 static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
0885 {
0886     u32 offset;
0887     u32 vlanbyte;
0888 
0889     for (offset = 0; offset < hw->mac.vft_size; offset++)
0890         IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
0891 
0892     for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
0893         for (offset = 0; offset < hw->mac.vft_size; offset++)
0894             IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
0895                     0);
0896 
0897     return 0;
0898 }
0899 
0900 /**
0901  *  ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
0902  *  @hw: pointer to hardware structure
0903  *  @reg: analog register to read
0904  *  @val: read value
0905  *
0906  *  Performs read operation to Atlas analog register specified.
0907  **/
0908 static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
0909 {
0910     u32  atlas_ctl;
0911 
0912     IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
0913             IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
0914     IXGBE_WRITE_FLUSH(hw);
0915     udelay(10);
0916     atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
0917     *val = (u8)atlas_ctl;
0918 
0919     return 0;
0920 }
0921 
0922 /**
0923  *  ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
0924  *  @hw: pointer to hardware structure
0925  *  @reg: atlas register to write
0926  *  @val: value to write
0927  *
0928  *  Performs write operation to Atlas analog register specified.
0929  **/
0930 static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
0931 {
0932     u32  atlas_ctl;
0933 
0934     atlas_ctl = (reg << 8) | val;
0935     IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
0936     IXGBE_WRITE_FLUSH(hw);
0937     udelay(10);
0938 
0939     return 0;
0940 }
0941 
0942 /**
0943  *  ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
0944  *  @hw: pointer to hardware structure
0945  *  @dev_addr: address to read from
0946  *  @byte_offset: byte offset to read from dev_addr
0947  *  @eeprom_data: value read
0948  *
0949  *  Performs 8 byte read operation to SFP module's data over I2C interface.
0950  **/
0951 static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
0952                     u8 byte_offset, u8 *eeprom_data)
0953 {
0954     s32 status = 0;
0955     u16 sfp_addr = 0;
0956     u16 sfp_data = 0;
0957     u16 sfp_stat = 0;
0958     u16 gssr;
0959     u32 i;
0960 
0961     if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
0962         gssr = IXGBE_GSSR_PHY1_SM;
0963     else
0964         gssr = IXGBE_GSSR_PHY0_SM;
0965 
0966     if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
0967         return IXGBE_ERR_SWFW_SYNC;
0968 
0969     if (hw->phy.type == ixgbe_phy_nl) {
0970         /*
0971          * phy SDA/SCL registers are at addresses 0xC30A to
0972          * 0xC30D.  These registers are used to talk to the SFP+
0973          * module's EEPROM through the SDA/SCL (I2C) interface.
0974          */
0975         sfp_addr = (dev_addr << 8) + byte_offset;
0976         sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
0977         hw->phy.ops.write_reg_mdi(hw,
0978                       IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
0979                       MDIO_MMD_PMAPMD,
0980                       sfp_addr);
0981 
0982         /* Poll status */
0983         for (i = 0; i < 100; i++) {
0984             hw->phy.ops.read_reg_mdi(hw,
0985                         IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
0986                         MDIO_MMD_PMAPMD,
0987                         &sfp_stat);
0988             sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
0989             if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
0990                 break;
0991             usleep_range(10000, 20000);
0992         }
0993 
0994         if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
0995             hw_dbg(hw, "EEPROM read did not pass.\n");
0996             status = IXGBE_ERR_SFP_NOT_PRESENT;
0997             goto out;
0998         }
0999 
1000         /* Read data */
1001         hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1002                     MDIO_MMD_PMAPMD, &sfp_data);
1003 
1004         *eeprom_data = (u8)(sfp_data >> 8);
1005     } else {
1006         status = IXGBE_ERR_PHY;
1007     }
1008 
1009 out:
1010     hw->mac.ops.release_swfw_sync(hw, gssr);
1011     return status;
1012 }
1013 
1014 /**
1015  *  ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1016  *  @hw: pointer to hardware structure
1017  *  @byte_offset: EEPROM byte offset to read
1018  *  @eeprom_data: value read
1019  *
1020  *  Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1021  **/
1022 static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1023                        u8 *eeprom_data)
1024 {
1025     return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
1026                     byte_offset, eeprom_data);
1027 }
1028 
1029 /**
1030  *  ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
1031  *  @hw: pointer to hardware structure
1032  *  @byte_offset: byte offset at address 0xA2
1033  *  @sff8472_data: value read
1034  *
1035  *  Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
1036  **/
1037 static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
1038                        u8 *sff8472_data)
1039 {
1040     return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
1041                     byte_offset, sff8472_data);
1042 }
1043 
1044 /**
1045  *  ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1046  *  port devices.
1047  *  @hw: pointer to the HW structure
1048  *
1049  *  Calls common function and corrects issue with some single port devices
1050  *  that enable LAN1 but not LAN0.
1051  **/
1052 static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1053 {
1054     struct ixgbe_bus_info *bus = &hw->bus;
1055     u16 pci_gen = 0;
1056     u16 pci_ctrl2 = 0;
1057 
1058     ixgbe_set_lan_id_multi_port_pcie(hw);
1059 
1060     /* check if LAN0 is disabled */
1061     hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1062     if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1063 
1064         hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1065 
1066         /* if LAN0 is completely disabled force function to 0 */
1067         if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1068             !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1069             !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1070 
1071             bus->func = 0;
1072         }
1073     }
1074 }
1075 
1076 /**
1077  * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1078  * @hw: pointer to hardware structure
1079  * @num_pb: number of packet buffers to allocate
1080  * @headroom: reserve n KB of headroom
1081  * @strategy: packet buffer allocation strategy
1082  **/
1083 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1084                   u32 headroom, int strategy)
1085 {
1086     u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1087     u8  i = 0;
1088 
1089     if (!num_pb)
1090         return;
1091 
1092     /* Setup Rx packet buffer sizes */
1093     switch (strategy) {
1094     case PBA_STRATEGY_WEIGHTED:
1095         /* Setup the first four at 80KB */
1096         rxpktsize = IXGBE_RXPBSIZE_80KB;
1097         for (; i < 4; i++)
1098             IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1099         /* Setup the last four at 48KB...don't re-init i */
1100         rxpktsize = IXGBE_RXPBSIZE_48KB;
1101         fallthrough;
1102     case PBA_STRATEGY_EQUAL:
1103     default:
1104         /* Divide the remaining Rx packet buffer evenly among the TCs */
1105         for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1106             IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1107         break;
1108     }
1109 
1110     /* Setup Tx packet buffer sizes */
1111     for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1112         IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1113 }
1114 
1115 static const struct ixgbe_mac_operations mac_ops_82598 = {
1116     .init_hw        = &ixgbe_init_hw_generic,
1117     .reset_hw       = &ixgbe_reset_hw_82598,
1118     .start_hw       = &ixgbe_start_hw_82598,
1119     .clear_hw_cntrs     = &ixgbe_clear_hw_cntrs_generic,
1120     .get_media_type     = &ixgbe_get_media_type_82598,
1121     .enable_rx_dma          = &ixgbe_enable_rx_dma_generic,
1122     .get_mac_addr       = &ixgbe_get_mac_addr_generic,
1123     .stop_adapter       = &ixgbe_stop_adapter_generic,
1124     .get_bus_info           = &ixgbe_get_bus_info_generic,
1125     .set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie_82598,
1126     .read_analog_reg8   = &ixgbe_read_analog_reg8_82598,
1127     .write_analog_reg8  = &ixgbe_write_analog_reg8_82598,
1128     .setup_link     = &ixgbe_setup_mac_link_82598,
1129     .set_rxpba      = &ixgbe_set_rxpba_82598,
1130     .check_link     = &ixgbe_check_mac_link_82598,
1131     .get_link_capabilities  = &ixgbe_get_link_capabilities_82598,
1132     .led_on         = &ixgbe_led_on_generic,
1133     .led_off        = &ixgbe_led_off_generic,
1134     .init_led_link_act  = ixgbe_init_led_link_act_generic,
1135     .blink_led_start    = &ixgbe_blink_led_start_generic,
1136     .blink_led_stop     = &ixgbe_blink_led_stop_generic,
1137     .set_rar        = &ixgbe_set_rar_generic,
1138     .clear_rar      = &ixgbe_clear_rar_generic,
1139     .set_vmdq       = &ixgbe_set_vmdq_82598,
1140     .clear_vmdq     = &ixgbe_clear_vmdq_82598,
1141     .init_rx_addrs      = &ixgbe_init_rx_addrs_generic,
1142     .update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
1143     .enable_mc      = &ixgbe_enable_mc_generic,
1144     .disable_mc     = &ixgbe_disable_mc_generic,
1145     .clear_vfta     = &ixgbe_clear_vfta_82598,
1146     .set_vfta       = &ixgbe_set_vfta_82598,
1147     .fc_enable      = &ixgbe_fc_enable_82598,
1148     .setup_fc       = ixgbe_setup_fc_generic,
1149     .fc_autoneg     = ixgbe_fc_autoneg,
1150     .set_fw_drv_ver         = NULL,
1151     .acquire_swfw_sync      = &ixgbe_acquire_swfw_sync,
1152     .release_swfw_sync      = &ixgbe_release_swfw_sync,
1153     .init_swfw_sync     = NULL,
1154     .get_thermal_sensor_data = NULL,
1155     .init_thermal_sensor_thresh = NULL,
1156     .prot_autoc_read    = &prot_autoc_read_generic,
1157     .prot_autoc_write   = &prot_autoc_write_generic,
1158     .enable_rx      = &ixgbe_enable_rx_generic,
1159     .disable_rx     = &ixgbe_disable_rx_generic,
1160 };
1161 
1162 static const struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1163     .init_params        = &ixgbe_init_eeprom_params_generic,
1164     .read           = &ixgbe_read_eerd_generic,
1165     .write          = &ixgbe_write_eeprom_generic,
1166     .write_buffer       = &ixgbe_write_eeprom_buffer_bit_bang_generic,
1167     .read_buffer        = &ixgbe_read_eerd_buffer_generic,
1168     .calc_checksum          = &ixgbe_calc_eeprom_checksum_generic,
1169     .validate_checksum  = &ixgbe_validate_eeprom_checksum_generic,
1170     .update_checksum    = &ixgbe_update_eeprom_checksum_generic,
1171 };
1172 
1173 static const struct ixgbe_phy_operations phy_ops_82598 = {
1174     .identify       = &ixgbe_identify_phy_generic,
1175     .identify_sfp       = &ixgbe_identify_module_generic,
1176     .init           = &ixgbe_init_phy_ops_82598,
1177     .reset          = &ixgbe_reset_phy_generic,
1178     .read_reg       = &ixgbe_read_phy_reg_generic,
1179     .write_reg      = &ixgbe_write_phy_reg_generic,
1180     .read_reg_mdi       = &ixgbe_read_phy_reg_mdi,
1181     .write_reg_mdi      = &ixgbe_write_phy_reg_mdi,
1182     .setup_link     = &ixgbe_setup_phy_link_generic,
1183     .setup_link_speed   = &ixgbe_setup_phy_link_speed_generic,
1184     .read_i2c_sff8472   = &ixgbe_read_i2c_sff8472_82598,
1185     .read_i2c_eeprom    = &ixgbe_read_i2c_eeprom_82598,
1186     .check_overtemp     = &ixgbe_tn_check_overtemp,
1187 };
1188 
1189 const struct ixgbe_info ixgbe_82598_info = {
1190     .mac            = ixgbe_mac_82598EB,
1191     .get_invariants     = &ixgbe_get_invariants_82598,
1192     .mac_ops        = &mac_ops_82598,
1193     .eeprom_ops     = &eeprom_ops_82598,
1194     .phy_ops        = &phy_ops_82598,
1195     .mvals          = ixgbe_mvals_8259X,
1196 };
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