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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 1999 - 2008 Intel Corporation. */
0003 
0004 /* ixgb_hw.c
0005  * Shared functions for accessing and configuring the adapter
0006  */
0007 
0008 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0009 
0010 #include <linux/pci_ids.h>
0011 #include "ixgb_hw.h"
0012 #include "ixgb_ids.h"
0013 
0014 #include <linux/etherdevice.h>
0015 
0016 /*  Local function prototypes */
0017 
0018 static u32 ixgb_hash_mc_addr(struct ixgb_hw *hw, u8 * mc_addr);
0019 
0020 static void ixgb_mta_set(struct ixgb_hw *hw, u32 hash_value);
0021 
0022 static void ixgb_get_bus_info(struct ixgb_hw *hw);
0023 
0024 static bool ixgb_link_reset(struct ixgb_hw *hw);
0025 
0026 static void ixgb_optics_reset(struct ixgb_hw *hw);
0027 
0028 static void ixgb_optics_reset_bcm(struct ixgb_hw *hw);
0029 
0030 static ixgb_phy_type ixgb_identify_phy(struct ixgb_hw *hw);
0031 
0032 static void ixgb_clear_hw_cntrs(struct ixgb_hw *hw);
0033 
0034 static void ixgb_clear_vfta(struct ixgb_hw *hw);
0035 
0036 static void ixgb_init_rx_addrs(struct ixgb_hw *hw);
0037 
0038 static u16 ixgb_read_phy_reg(struct ixgb_hw *hw,
0039                   u32 reg_address,
0040                   u32 phy_address,
0041                   u32 device_type);
0042 
0043 static bool ixgb_setup_fc(struct ixgb_hw *hw);
0044 
0045 static bool mac_addr_valid(u8 *mac_addr);
0046 
0047 static u32 ixgb_mac_reset(struct ixgb_hw *hw)
0048 {
0049     u32 ctrl_reg;
0050 
0051     ctrl_reg =  IXGB_CTRL0_RST |
0052                 IXGB_CTRL0_SDP3_DIR |   /* All pins are Output=1 */
0053                 IXGB_CTRL0_SDP2_DIR |
0054                 IXGB_CTRL0_SDP1_DIR |
0055                 IXGB_CTRL0_SDP0_DIR |
0056                 IXGB_CTRL0_SDP3  |   /* Initial value 1101   */
0057                 IXGB_CTRL0_SDP2  |
0058                 IXGB_CTRL0_SDP0;
0059 
0060 #ifdef HP_ZX1
0061     /* Workaround for 82597EX reset errata */
0062     IXGB_WRITE_REG_IO(hw, CTRL0, ctrl_reg);
0063 #else
0064     IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
0065 #endif
0066 
0067     /* Delay a few ms just to allow the reset to complete */
0068     msleep(IXGB_DELAY_AFTER_RESET);
0069     ctrl_reg = IXGB_READ_REG(hw, CTRL0);
0070 #ifdef DBG
0071     /* Make sure the self-clearing global reset bit did self clear */
0072     ASSERT(!(ctrl_reg & IXGB_CTRL0_RST));
0073 #endif
0074 
0075     if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN) {
0076         ctrl_reg =  /* Enable interrupt from XFP and SerDes */
0077                IXGB_CTRL1_GPI0_EN |
0078                IXGB_CTRL1_SDP6_DIR |
0079                IXGB_CTRL1_SDP7_DIR |
0080                IXGB_CTRL1_SDP6 |
0081                IXGB_CTRL1_SDP7;
0082         IXGB_WRITE_REG(hw, CTRL1, ctrl_reg);
0083         ixgb_optics_reset_bcm(hw);
0084     }
0085 
0086     if (hw->phy_type == ixgb_phy_type_txn17401)
0087         ixgb_optics_reset(hw);
0088 
0089     return ctrl_reg;
0090 }
0091 
0092 /******************************************************************************
0093  * Reset the transmit and receive units; mask and clear all interrupts.
0094  *
0095  * hw - Struct containing variables accessed by shared code
0096  *****************************************************************************/
0097 bool
0098 ixgb_adapter_stop(struct ixgb_hw *hw)
0099 {
0100     u32 ctrl_reg;
0101 
0102     ENTER();
0103 
0104     /* If we are stopped or resetting exit gracefully and wait to be
0105      * started again before accessing the hardware.
0106      */
0107     if (hw->adapter_stopped) {
0108         pr_debug("Exiting because the adapter is already stopped!!!\n");
0109         return false;
0110     }
0111 
0112     /* Set the Adapter Stopped flag so other driver functions stop
0113      * touching the Hardware.
0114      */
0115     hw->adapter_stopped = true;
0116 
0117     /* Clear interrupt mask to stop board from generating interrupts */
0118     pr_debug("Masking off all interrupts\n");
0119     IXGB_WRITE_REG(hw, IMC, 0xFFFFFFFF);
0120 
0121     /* Disable the Transmit and Receive units.  Then delay to allow
0122      * any pending transactions to complete before we hit the MAC with
0123      * the global reset.
0124      */
0125     IXGB_WRITE_REG(hw, RCTL, IXGB_READ_REG(hw, RCTL) & ~IXGB_RCTL_RXEN);
0126     IXGB_WRITE_REG(hw, TCTL, IXGB_READ_REG(hw, TCTL) & ~IXGB_TCTL_TXEN);
0127     IXGB_WRITE_FLUSH(hw);
0128     msleep(IXGB_DELAY_BEFORE_RESET);
0129 
0130     /* Issue a global reset to the MAC.  This will reset the chip's
0131      * transmit, receive, DMA, and link units.  It will not effect
0132      * the current PCI configuration.  The global reset bit is self-
0133      * clearing, and should clear within a microsecond.
0134      */
0135     pr_debug("Issuing a global reset to MAC\n");
0136 
0137     ctrl_reg = ixgb_mac_reset(hw);
0138 
0139     /* Clear interrupt mask to stop board from generating interrupts */
0140     pr_debug("Masking off all interrupts\n");
0141     IXGB_WRITE_REG(hw, IMC, 0xffffffff);
0142 
0143     /* Clear any pending interrupt events. */
0144     IXGB_READ_REG(hw, ICR);
0145 
0146     return ctrl_reg & IXGB_CTRL0_RST;
0147 }
0148 
0149 
0150 /******************************************************************************
0151  * Identifies the vendor of the optics module on the adapter.  The SR adapters
0152  * support two different types of XPAK optics, so it is necessary to determine
0153  * which optics are present before applying any optics-specific workarounds.
0154  *
0155  * hw - Struct containing variables accessed by shared code.
0156  *
0157  * Returns: the vendor of the XPAK optics module.
0158  *****************************************************************************/
0159 static ixgb_xpak_vendor
0160 ixgb_identify_xpak_vendor(struct ixgb_hw *hw)
0161 {
0162     u32 i;
0163     u16 vendor_name[5];
0164     ixgb_xpak_vendor xpak_vendor;
0165 
0166     ENTER();
0167 
0168     /* Read the first few bytes of the vendor string from the XPAK NVR
0169      * registers.  These are standard XENPAK/XPAK registers, so all XPAK
0170      * devices should implement them. */
0171     for (i = 0; i < 5; i++) {
0172         vendor_name[i] = ixgb_read_phy_reg(hw,
0173                            MDIO_PMA_PMD_XPAK_VENDOR_NAME
0174                            + i, IXGB_PHY_ADDRESS,
0175                            MDIO_MMD_PMAPMD);
0176     }
0177 
0178     /* Determine the actual vendor */
0179     if (vendor_name[0] == 'I' &&
0180         vendor_name[1] == 'N' &&
0181         vendor_name[2] == 'T' &&
0182         vendor_name[3] == 'E' && vendor_name[4] == 'L') {
0183         xpak_vendor = ixgb_xpak_vendor_intel;
0184     } else {
0185         xpak_vendor = ixgb_xpak_vendor_infineon;
0186     }
0187 
0188     return xpak_vendor;
0189 }
0190 
0191 /******************************************************************************
0192  * Determine the physical layer module on the adapter.
0193  *
0194  * hw - Struct containing variables accessed by shared code.  The device_id
0195  *      field must be (correctly) populated before calling this routine.
0196  *
0197  * Returns: the phy type of the adapter.
0198  *****************************************************************************/
0199 static ixgb_phy_type
0200 ixgb_identify_phy(struct ixgb_hw *hw)
0201 {
0202     ixgb_phy_type phy_type;
0203     ixgb_xpak_vendor xpak_vendor;
0204 
0205     ENTER();
0206 
0207     /* Infer the transceiver/phy type from the device id */
0208     switch (hw->device_id) {
0209     case IXGB_DEVICE_ID_82597EX:
0210         pr_debug("Identified TXN17401 optics\n");
0211         phy_type = ixgb_phy_type_txn17401;
0212         break;
0213 
0214     case IXGB_DEVICE_ID_82597EX_SR:
0215         /* The SR adapters carry two different types of XPAK optics
0216          * modules; read the vendor identifier to determine the exact
0217          * type of optics. */
0218         xpak_vendor = ixgb_identify_xpak_vendor(hw);
0219         if (xpak_vendor == ixgb_xpak_vendor_intel) {
0220             pr_debug("Identified TXN17201 optics\n");
0221             phy_type = ixgb_phy_type_txn17201;
0222         } else {
0223             pr_debug("Identified G6005 optics\n");
0224             phy_type = ixgb_phy_type_g6005;
0225         }
0226         break;
0227     case IXGB_DEVICE_ID_82597EX_LR:
0228         pr_debug("Identified G6104 optics\n");
0229         phy_type = ixgb_phy_type_g6104;
0230         break;
0231     case IXGB_DEVICE_ID_82597EX_CX4:
0232         pr_debug("Identified CX4\n");
0233         xpak_vendor = ixgb_identify_xpak_vendor(hw);
0234         if (xpak_vendor == ixgb_xpak_vendor_intel) {
0235             pr_debug("Identified TXN17201 optics\n");
0236             phy_type = ixgb_phy_type_txn17201;
0237         } else {
0238             pr_debug("Identified G6005 optics\n");
0239             phy_type = ixgb_phy_type_g6005;
0240         }
0241         break;
0242     default:
0243         pr_debug("Unknown physical layer module\n");
0244         phy_type = ixgb_phy_type_unknown;
0245         break;
0246     }
0247 
0248     /* update phy type for sun specific board */
0249     if (hw->subsystem_vendor_id == PCI_VENDOR_ID_SUN)
0250         phy_type = ixgb_phy_type_bcm;
0251 
0252     return phy_type;
0253 }
0254 
0255 /******************************************************************************
0256  * Performs basic configuration of the adapter.
0257  *
0258  * hw - Struct containing variables accessed by shared code
0259  *
0260  * Resets the controller.
0261  * Reads and validates the EEPROM.
0262  * Initializes the receive address registers.
0263  * Initializes the multicast table.
0264  * Clears all on-chip counters.
0265  * Calls routine to setup flow control settings.
0266  * Leaves the transmit and receive units disabled and uninitialized.
0267  *
0268  * Returns:
0269  *      true if successful,
0270  *      false if unrecoverable problems were encountered.
0271  *****************************************************************************/
0272 bool
0273 ixgb_init_hw(struct ixgb_hw *hw)
0274 {
0275     u32 i;
0276     bool status;
0277 
0278     ENTER();
0279 
0280     /* Issue a global reset to the MAC.  This will reset the chip's
0281      * transmit, receive, DMA, and link units.  It will not effect
0282      * the current PCI configuration.  The global reset bit is self-
0283      * clearing, and should clear within a microsecond.
0284      */
0285     pr_debug("Issuing a global reset to MAC\n");
0286 
0287     ixgb_mac_reset(hw);
0288 
0289     pr_debug("Issuing an EE reset to MAC\n");
0290 #ifdef HP_ZX1
0291     /* Workaround for 82597EX reset errata */
0292     IXGB_WRITE_REG_IO(hw, CTRL1, IXGB_CTRL1_EE_RST);
0293 #else
0294     IXGB_WRITE_REG(hw, CTRL1, IXGB_CTRL1_EE_RST);
0295 #endif
0296 
0297     /* Delay a few ms just to allow the reset to complete */
0298     msleep(IXGB_DELAY_AFTER_EE_RESET);
0299 
0300     if (!ixgb_get_eeprom_data(hw))
0301         return false;
0302 
0303     /* Use the device id to determine the type of phy/transceiver. */
0304     hw->device_id = ixgb_get_ee_device_id(hw);
0305     hw->phy_type = ixgb_identify_phy(hw);
0306 
0307     /* Setup the receive addresses.
0308      * Receive Address Registers (RARs 0 - 15).
0309      */
0310     ixgb_init_rx_addrs(hw);
0311 
0312     /*
0313      * Check that a valid MAC address has been set.
0314      * If it is not valid, we fail hardware init.
0315      */
0316     if (!mac_addr_valid(hw->curr_mac_addr)) {
0317         pr_debug("MAC address invalid after ixgb_init_rx_addrs\n");
0318         return(false);
0319     }
0320 
0321     /* tell the routines in this file they can access hardware again */
0322     hw->adapter_stopped = false;
0323 
0324     /* Fill in the bus_info structure */
0325     ixgb_get_bus_info(hw);
0326 
0327     /* Zero out the Multicast HASH table */
0328     pr_debug("Zeroing the MTA\n");
0329     for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
0330         IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
0331 
0332     /* Zero out the VLAN Filter Table Array */
0333     ixgb_clear_vfta(hw);
0334 
0335     /* Zero all of the hardware counters */
0336     ixgb_clear_hw_cntrs(hw);
0337 
0338     /* Call a subroutine to setup flow control. */
0339     status = ixgb_setup_fc(hw);
0340 
0341     /* 82597EX errata: Call check-for-link in case lane deskew is locked */
0342     ixgb_check_for_link(hw);
0343 
0344     return status;
0345 }
0346 
0347 /******************************************************************************
0348  * Initializes receive address filters.
0349  *
0350  * hw - Struct containing variables accessed by shared code
0351  *
0352  * Places the MAC address in receive address register 0 and clears the rest
0353  * of the receive address registers. Clears the multicast table. Assumes
0354  * the receiver is in reset when the routine is called.
0355  *****************************************************************************/
0356 static void
0357 ixgb_init_rx_addrs(struct ixgb_hw *hw)
0358 {
0359     u32 i;
0360 
0361     ENTER();
0362 
0363     /*
0364      * If the current mac address is valid, assume it is a software override
0365      * to the permanent address.
0366      * Otherwise, use the permanent address from the eeprom.
0367      */
0368     if (!mac_addr_valid(hw->curr_mac_addr)) {
0369 
0370         /* Get the MAC address from the eeprom for later reference */
0371         ixgb_get_ee_mac_addr(hw, hw->curr_mac_addr);
0372 
0373         pr_debug("Keeping Permanent MAC Addr = %pM\n",
0374              hw->curr_mac_addr);
0375     } else {
0376 
0377         /* Setup the receive address. */
0378         pr_debug("Overriding MAC Address in RAR[0]\n");
0379         pr_debug("New MAC Addr = %pM\n", hw->curr_mac_addr);
0380 
0381         ixgb_rar_set(hw, hw->curr_mac_addr, 0);
0382     }
0383 
0384     /* Zero out the other 15 receive addresses. */
0385     pr_debug("Clearing RAR[1-15]\n");
0386     for (i = 1; i < IXGB_RAR_ENTRIES; i++) {
0387         /* Write high reg first to disable the AV bit first */
0388         IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
0389         IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
0390     }
0391 }
0392 
0393 /******************************************************************************
0394  * Updates the MAC's list of multicast addresses.
0395  *
0396  * hw - Struct containing variables accessed by shared code
0397  * mc_addr_list - the list of new multicast addresses
0398  * mc_addr_count - number of addresses
0399  * pad - number of bytes between addresses in the list
0400  *
0401  * The given list replaces any existing list. Clears the last 15 receive
0402  * address registers and the multicast table. Uses receive address registers
0403  * for the first 15 multicast addresses, and hashes the rest into the
0404  * multicast table.
0405  *****************************************************************************/
0406 void
0407 ixgb_mc_addr_list_update(struct ixgb_hw *hw,
0408               u8 *mc_addr_list,
0409               u32 mc_addr_count,
0410               u32 pad)
0411 {
0412     u32 hash_value;
0413     u32 i;
0414     u32 rar_used_count = 1;     /* RAR[0] is used for our MAC address */
0415     u8 *mca;
0416 
0417     ENTER();
0418 
0419     /* Set the new number of MC addresses that we are being requested to use. */
0420     hw->num_mc_addrs = mc_addr_count;
0421 
0422     /* Clear RAR[1-15] */
0423     pr_debug("Clearing RAR[1-15]\n");
0424     for (i = rar_used_count; i < IXGB_RAR_ENTRIES; i++) {
0425         IXGB_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
0426         IXGB_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
0427     }
0428 
0429     /* Clear the MTA */
0430     pr_debug("Clearing MTA\n");
0431     for (i = 0; i < IXGB_MC_TBL_SIZE; i++)
0432         IXGB_WRITE_REG_ARRAY(hw, MTA, i, 0);
0433 
0434     /* Add the new addresses */
0435     mca = mc_addr_list;
0436     for (i = 0; i < mc_addr_count; i++) {
0437         pr_debug("Adding the multicast addresses:\n");
0438         pr_debug("MC Addr #%d = %pM\n", i, mca);
0439 
0440         /* Place this multicast address in the RAR if there is room, *
0441          * else put it in the MTA
0442          */
0443         if (rar_used_count < IXGB_RAR_ENTRIES) {
0444             ixgb_rar_set(hw, mca, rar_used_count);
0445             pr_debug("Added a multicast address to RAR[%d]\n", i);
0446             rar_used_count++;
0447         } else {
0448             hash_value = ixgb_hash_mc_addr(hw, mca);
0449 
0450             pr_debug("Hash value = 0x%03X\n", hash_value);
0451 
0452             ixgb_mta_set(hw, hash_value);
0453         }
0454 
0455         mca += ETH_ALEN + pad;
0456     }
0457 
0458     pr_debug("MC Update Complete\n");
0459 }
0460 
0461 /******************************************************************************
0462  * Hashes an address to determine its location in the multicast table
0463  *
0464  * hw - Struct containing variables accessed by shared code
0465  * mc_addr - the multicast address to hash
0466  *
0467  * Returns:
0468  *      The hash value
0469  *****************************************************************************/
0470 static u32
0471 ixgb_hash_mc_addr(struct ixgb_hw *hw,
0472            u8 *mc_addr)
0473 {
0474     u32 hash_value = 0;
0475 
0476     ENTER();
0477 
0478     /* The portion of the address that is used for the hash table is
0479      * determined by the mc_filter_type setting.
0480      */
0481     switch (hw->mc_filter_type) {
0482         /* [0] [1] [2] [3] [4] [5]
0483          * 01  AA  00  12  34  56
0484          * LSB                 MSB - According to H/W docs */
0485     case 0:
0486         /* [47:36] i.e. 0x563 for above example address */
0487         hash_value =
0488             ((mc_addr[4] >> 4) | (((u16) mc_addr[5]) << 4));
0489         break;
0490     case 1:     /* [46:35] i.e. 0xAC6 for above example address */
0491         hash_value =
0492             ((mc_addr[4] >> 3) | (((u16) mc_addr[5]) << 5));
0493         break;
0494     case 2:     /* [45:34] i.e. 0x5D8 for above example address */
0495         hash_value =
0496             ((mc_addr[4] >> 2) | (((u16) mc_addr[5]) << 6));
0497         break;
0498     case 3:     /* [43:32] i.e. 0x634 for above example address */
0499         hash_value = ((mc_addr[4]) | (((u16) mc_addr[5]) << 8));
0500         break;
0501     default:
0502         /* Invalid mc_filter_type, what should we do? */
0503         pr_debug("MC filter type param set incorrectly\n");
0504         ASSERT(0);
0505         break;
0506     }
0507 
0508     hash_value &= 0xFFF;
0509     return hash_value;
0510 }
0511 
0512 /******************************************************************************
0513  * Sets the bit in the multicast table corresponding to the hash value.
0514  *
0515  * hw - Struct containing variables accessed by shared code
0516  * hash_value - Multicast address hash value
0517  *****************************************************************************/
0518 static void
0519 ixgb_mta_set(struct ixgb_hw *hw,
0520           u32 hash_value)
0521 {
0522     u32 hash_bit, hash_reg;
0523     u32 mta_reg;
0524 
0525     /* The MTA is a register array of 128 32-bit registers.
0526      * It is treated like an array of 4096 bits.  We want to set
0527      * bit BitArray[hash_value]. So we figure out what register
0528      * the bit is in, read it, OR in the new bit, then write
0529      * back the new value.  The register is determined by the
0530      * upper 7 bits of the hash value and the bit within that
0531      * register are determined by the lower 5 bits of the value.
0532      */
0533     hash_reg = (hash_value >> 5) & 0x7F;
0534     hash_bit = hash_value & 0x1F;
0535 
0536     mta_reg = IXGB_READ_REG_ARRAY(hw, MTA, hash_reg);
0537 
0538     mta_reg |= (1 << hash_bit);
0539 
0540     IXGB_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta_reg);
0541 }
0542 
0543 /******************************************************************************
0544  * Puts an ethernet address into a receive address register.
0545  *
0546  * hw - Struct containing variables accessed by shared code
0547  * addr - Address to put into receive address register
0548  * index - Receive address register to write
0549  *****************************************************************************/
0550 void
0551 ixgb_rar_set(struct ixgb_hw *hw,
0552           const u8 *addr,
0553           u32 index)
0554 {
0555     u32 rar_low, rar_high;
0556 
0557     ENTER();
0558 
0559     /* HW expects these in little endian so we reverse the byte order
0560      * from network order (big endian) to little endian
0561      */
0562     rar_low = ((u32) addr[0] |
0563            ((u32)addr[1] << 8) |
0564            ((u32)addr[2] << 16) |
0565            ((u32)addr[3] << 24));
0566 
0567     rar_high = ((u32) addr[4] |
0568             ((u32)addr[5] << 8) |
0569             IXGB_RAH_AV);
0570 
0571     IXGB_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
0572     IXGB_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
0573 }
0574 
0575 /******************************************************************************
0576  * Writes a value to the specified offset in the VLAN filter table.
0577  *
0578  * hw - Struct containing variables accessed by shared code
0579  * offset - Offset in VLAN filter table to write
0580  * value - Value to write into VLAN filter table
0581  *****************************************************************************/
0582 void
0583 ixgb_write_vfta(struct ixgb_hw *hw,
0584          u32 offset,
0585          u32 value)
0586 {
0587     IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, value);
0588 }
0589 
0590 /******************************************************************************
0591  * Clears the VLAN filter table
0592  *
0593  * hw - Struct containing variables accessed by shared code
0594  *****************************************************************************/
0595 static void
0596 ixgb_clear_vfta(struct ixgb_hw *hw)
0597 {
0598     u32 offset;
0599 
0600     for (offset = 0; offset < IXGB_VLAN_FILTER_TBL_SIZE; offset++)
0601         IXGB_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
0602 }
0603 
0604 /******************************************************************************
0605  * Configures the flow control settings based on SW configuration.
0606  *
0607  * hw - Struct containing variables accessed by shared code
0608  *****************************************************************************/
0609 
0610 static bool
0611 ixgb_setup_fc(struct ixgb_hw *hw)
0612 {
0613     u32 ctrl_reg;
0614     u32 pap_reg = 0;   /* by default, assume no pause time */
0615     bool status = true;
0616 
0617     ENTER();
0618 
0619     /* Get the current control reg 0 settings */
0620     ctrl_reg = IXGB_READ_REG(hw, CTRL0);
0621 
0622     /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
0623     ctrl_reg &= ~(IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
0624 
0625     /* The possible values of the "flow_control" parameter are:
0626      *      0:  Flow control is completely disabled
0627      *      1:  Rx flow control is enabled (we can receive pause frames
0628      *          but not send pause frames).
0629      *      2:  Tx flow control is enabled (we can send pause frames
0630      *          but we do not support receiving pause frames).
0631      *      3:  Both Rx and TX flow control (symmetric) are enabled.
0632      *  other:  Invalid.
0633      */
0634     switch (hw->fc.type) {
0635     case ixgb_fc_none:  /* 0 */
0636         /* Set CMDC bit to disable Rx Flow control */
0637         ctrl_reg |= (IXGB_CTRL0_CMDC);
0638         break;
0639     case ixgb_fc_rx_pause:  /* 1 */
0640         /* RX Flow control is enabled, and TX Flow control is
0641          * disabled.
0642          */
0643         ctrl_reg |= (IXGB_CTRL0_RPE);
0644         break;
0645     case ixgb_fc_tx_pause:  /* 2 */
0646         /* TX Flow control is enabled, and RX Flow control is
0647          * disabled, by a software over-ride.
0648          */
0649         ctrl_reg |= (IXGB_CTRL0_TPE);
0650         pap_reg = hw->fc.pause_time;
0651         break;
0652     case ixgb_fc_full:  /* 3 */
0653         /* Flow control (both RX and TX) is enabled by a software
0654          * over-ride.
0655          */
0656         ctrl_reg |= (IXGB_CTRL0_RPE | IXGB_CTRL0_TPE);
0657         pap_reg = hw->fc.pause_time;
0658         break;
0659     default:
0660         /* We should never get here.  The value should be 0-3. */
0661         pr_debug("Flow control param set incorrectly\n");
0662         ASSERT(0);
0663         break;
0664     }
0665 
0666     /* Write the new settings */
0667     IXGB_WRITE_REG(hw, CTRL0, ctrl_reg);
0668 
0669     if (pap_reg != 0)
0670         IXGB_WRITE_REG(hw, PAP, pap_reg);
0671 
0672     /* Set the flow control receive threshold registers.  Normally,
0673      * these registers will be set to a default threshold that may be
0674      * adjusted later by the driver's runtime code.  However, if the
0675      * ability to transmit pause frames in not enabled, then these
0676      * registers will be set to 0.
0677      */
0678     if (!(hw->fc.type & ixgb_fc_tx_pause)) {
0679         IXGB_WRITE_REG(hw, FCRTL, 0);
0680         IXGB_WRITE_REG(hw, FCRTH, 0);
0681     } else {
0682        /* We need to set up the Receive Threshold high and low water
0683         * marks as well as (optionally) enabling the transmission of XON
0684         * frames. */
0685         if (hw->fc.send_xon) {
0686             IXGB_WRITE_REG(hw, FCRTL,
0687                 (hw->fc.low_water | IXGB_FCRTL_XONE));
0688         } else {
0689             IXGB_WRITE_REG(hw, FCRTL, hw->fc.low_water);
0690         }
0691         IXGB_WRITE_REG(hw, FCRTH, hw->fc.high_water);
0692     }
0693     return status;
0694 }
0695 
0696 /******************************************************************************
0697  * Reads a word from a device over the Management Data Interface (MDI) bus.
0698  * This interface is used to manage Physical layer devices.
0699  *
0700  * hw          - Struct containing variables accessed by hw code
0701  * reg_address - Offset of device register being read.
0702  * phy_address - Address of device on MDI.
0703  *
0704  * Returns:  Data word (16 bits) from MDI device.
0705  *
0706  * The 82597EX has support for several MDI access methods.  This routine
0707  * uses the new protocol MDI Single Command and Address Operation.
0708  * This requires that first an address cycle command is sent, followed by a
0709  * read command.
0710  *****************************************************************************/
0711 static u16
0712 ixgb_read_phy_reg(struct ixgb_hw *hw,
0713         u32 reg_address,
0714         u32 phy_address,
0715         u32 device_type)
0716 {
0717     u32 i;
0718     u32 data;
0719     u32 command = 0;
0720 
0721     ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
0722     ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
0723     ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
0724 
0725     /* Setup and write the address cycle command */
0726     command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
0727            (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
0728            (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
0729            (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
0730 
0731     IXGB_WRITE_REG(hw, MSCA, command);
0732 
0733     /**************************************************************
0734     ** Check every 10 usec to see if the address cycle completed
0735     ** The COMMAND bit will clear when the operation is complete.
0736     ** This may take as long as 64 usecs (we'll wait 100 usecs max)
0737     ** from the CPU Write to the Ready bit assertion.
0738     **************************************************************/
0739 
0740     for (i = 0; i < 10; i++)
0741     {
0742         udelay(10);
0743 
0744         command = IXGB_READ_REG(hw, MSCA);
0745 
0746         if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
0747             break;
0748     }
0749 
0750     ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
0751 
0752     /* Address cycle complete, setup and write the read command */
0753     command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT) |
0754            (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
0755            (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
0756            (IXGB_MSCA_READ | IXGB_MSCA_MDI_COMMAND));
0757 
0758     IXGB_WRITE_REG(hw, MSCA, command);
0759 
0760     /**************************************************************
0761     ** Check every 10 usec to see if the read command completed
0762     ** The COMMAND bit will clear when the operation is complete.
0763     ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
0764     ** from the CPU Write to the Ready bit assertion.
0765     **************************************************************/
0766 
0767     for (i = 0; i < 10; i++)
0768     {
0769         udelay(10);
0770 
0771         command = IXGB_READ_REG(hw, MSCA);
0772 
0773         if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
0774             break;
0775     }
0776 
0777     ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
0778 
0779     /* Operation is complete, get the data from the MDIO Read/Write Data
0780      * register and return.
0781      */
0782     data = IXGB_READ_REG(hw, MSRWD);
0783     data >>= IXGB_MSRWD_READ_DATA_SHIFT;
0784     return((u16) data);
0785 }
0786 
0787 /******************************************************************************
0788  * Writes a word to a device over the Management Data Interface (MDI) bus.
0789  * This interface is used to manage Physical layer devices.
0790  *
0791  * hw          - Struct containing variables accessed by hw code
0792  * reg_address - Offset of device register being read.
0793  * phy_address - Address of device on MDI.
0794  * device_type - Also known as the Device ID or DID.
0795  * data        - 16-bit value to be written
0796  *
0797  * Returns:  void.
0798  *
0799  * The 82597EX has support for several MDI access methods.  This routine
0800  * uses the new protocol MDI Single Command and Address Operation.
0801  * This requires that first an address cycle command is sent, followed by a
0802  * write command.
0803  *****************************************************************************/
0804 static void
0805 ixgb_write_phy_reg(struct ixgb_hw *hw,
0806             u32 reg_address,
0807             u32 phy_address,
0808             u32 device_type,
0809             u16 data)
0810 {
0811     u32 i;
0812     u32 command = 0;
0813 
0814     ASSERT(reg_address <= IXGB_MAX_PHY_REG_ADDRESS);
0815     ASSERT(phy_address <= IXGB_MAX_PHY_ADDRESS);
0816     ASSERT(device_type <= IXGB_MAX_PHY_DEV_TYPE);
0817 
0818     /* Put the data in the MDIO Read/Write Data register */
0819     IXGB_WRITE_REG(hw, MSRWD, (u32)data);
0820 
0821     /* Setup and write the address cycle command */
0822     command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT)  |
0823                (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
0824                (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
0825                (IXGB_MSCA_ADDR_CYCLE | IXGB_MSCA_MDI_COMMAND));
0826 
0827     IXGB_WRITE_REG(hw, MSCA, command);
0828 
0829     /**************************************************************
0830     ** Check every 10 usec to see if the address cycle completed
0831     ** The COMMAND bit will clear when the operation is complete.
0832     ** This may take as long as 64 usecs (we'll wait 100 usecs max)
0833     ** from the CPU Write to the Ready bit assertion.
0834     **************************************************************/
0835 
0836     for (i = 0; i < 10; i++)
0837     {
0838         udelay(10);
0839 
0840         command = IXGB_READ_REG(hw, MSCA);
0841 
0842         if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
0843             break;
0844     }
0845 
0846     ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
0847 
0848     /* Address cycle complete, setup and write the write command */
0849     command = ((reg_address << IXGB_MSCA_NP_ADDR_SHIFT)  |
0850                (device_type << IXGB_MSCA_DEV_TYPE_SHIFT) |
0851                (phy_address << IXGB_MSCA_PHY_ADDR_SHIFT) |
0852                (IXGB_MSCA_WRITE | IXGB_MSCA_MDI_COMMAND));
0853 
0854     IXGB_WRITE_REG(hw, MSCA, command);
0855 
0856     /**************************************************************
0857     ** Check every 10 usec to see if the read command completed
0858     ** The COMMAND bit will clear when the operation is complete.
0859     ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
0860     ** from the CPU Write to the Ready bit assertion.
0861     **************************************************************/
0862 
0863     for (i = 0; i < 10; i++)
0864     {
0865         udelay(10);
0866 
0867         command = IXGB_READ_REG(hw, MSCA);
0868 
0869         if ((command & IXGB_MSCA_MDI_COMMAND) == 0)
0870             break;
0871     }
0872 
0873     ASSERT((command & IXGB_MSCA_MDI_COMMAND) == 0);
0874 
0875     /* Operation is complete, return. */
0876 }
0877 
0878 /******************************************************************************
0879  * Checks to see if the link status of the hardware has changed.
0880  *
0881  * hw - Struct containing variables accessed by hw code
0882  *
0883  * Called by any function that needs to check the link status of the adapter.
0884  *****************************************************************************/
0885 void
0886 ixgb_check_for_link(struct ixgb_hw *hw)
0887 {
0888     u32 status_reg;
0889     u32 xpcss_reg;
0890 
0891     ENTER();
0892 
0893     xpcss_reg = IXGB_READ_REG(hw, XPCSS);
0894     status_reg = IXGB_READ_REG(hw, STATUS);
0895 
0896     if ((xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
0897         (status_reg & IXGB_STATUS_LU)) {
0898         hw->link_up = true;
0899     } else if (!(xpcss_reg & IXGB_XPCSS_ALIGN_STATUS) &&
0900            (status_reg & IXGB_STATUS_LU)) {
0901         pr_debug("XPCSS Not Aligned while Status:LU is set\n");
0902         hw->link_up = ixgb_link_reset(hw);
0903     } else {
0904         /*
0905          * 82597EX errata.  Since the lane deskew problem may prevent
0906          * link, reset the link before reporting link down.
0907          */
0908         hw->link_up = ixgb_link_reset(hw);
0909     }
0910     /*  Anything else for 10 Gig?? */
0911 }
0912 
0913 /******************************************************************************
0914  * Check for a bad link condition that may have occurred.
0915  * The indication is that the RFC / LFC registers may be incrementing
0916  * continually.  A full adapter reset is required to recover.
0917  *
0918  * hw - Struct containing variables accessed by hw code
0919  *
0920  * Called by any function that needs to check the link status of the adapter.
0921  *****************************************************************************/
0922 bool ixgb_check_for_bad_link(struct ixgb_hw *hw)
0923 {
0924     u32 newLFC, newRFC;
0925     bool bad_link_returncode = false;
0926 
0927     if (hw->phy_type == ixgb_phy_type_txn17401) {
0928         newLFC = IXGB_READ_REG(hw, LFC);
0929         newRFC = IXGB_READ_REG(hw, RFC);
0930         if ((hw->lastLFC + 250 < newLFC)
0931             || (hw->lastRFC + 250 < newRFC)) {
0932             pr_debug("BAD LINK! too many LFC/RFC since last check\n");
0933             bad_link_returncode = true;
0934         }
0935         hw->lastLFC = newLFC;
0936         hw->lastRFC = newRFC;
0937     }
0938 
0939     return bad_link_returncode;
0940 }
0941 
0942 /******************************************************************************
0943  * Clears all hardware statistics counters.
0944  *
0945  * hw - Struct containing variables accessed by shared code
0946  *****************************************************************************/
0947 static void
0948 ixgb_clear_hw_cntrs(struct ixgb_hw *hw)
0949 {
0950     ENTER();
0951 
0952     /* if we are stopped or resetting exit gracefully */
0953     if (hw->adapter_stopped) {
0954         pr_debug("Exiting because the adapter is stopped!!!\n");
0955         return;
0956     }
0957 
0958     IXGB_READ_REG(hw, TPRL);
0959     IXGB_READ_REG(hw, TPRH);
0960     IXGB_READ_REG(hw, GPRCL);
0961     IXGB_READ_REG(hw, GPRCH);
0962     IXGB_READ_REG(hw, BPRCL);
0963     IXGB_READ_REG(hw, BPRCH);
0964     IXGB_READ_REG(hw, MPRCL);
0965     IXGB_READ_REG(hw, MPRCH);
0966     IXGB_READ_REG(hw, UPRCL);
0967     IXGB_READ_REG(hw, UPRCH);
0968     IXGB_READ_REG(hw, VPRCL);
0969     IXGB_READ_REG(hw, VPRCH);
0970     IXGB_READ_REG(hw, JPRCL);
0971     IXGB_READ_REG(hw, JPRCH);
0972     IXGB_READ_REG(hw, GORCL);
0973     IXGB_READ_REG(hw, GORCH);
0974     IXGB_READ_REG(hw, TORL);
0975     IXGB_READ_REG(hw, TORH);
0976     IXGB_READ_REG(hw, RNBC);
0977     IXGB_READ_REG(hw, RUC);
0978     IXGB_READ_REG(hw, ROC);
0979     IXGB_READ_REG(hw, RLEC);
0980     IXGB_READ_REG(hw, CRCERRS);
0981     IXGB_READ_REG(hw, ICBC);
0982     IXGB_READ_REG(hw, ECBC);
0983     IXGB_READ_REG(hw, MPC);
0984     IXGB_READ_REG(hw, TPTL);
0985     IXGB_READ_REG(hw, TPTH);
0986     IXGB_READ_REG(hw, GPTCL);
0987     IXGB_READ_REG(hw, GPTCH);
0988     IXGB_READ_REG(hw, BPTCL);
0989     IXGB_READ_REG(hw, BPTCH);
0990     IXGB_READ_REG(hw, MPTCL);
0991     IXGB_READ_REG(hw, MPTCH);
0992     IXGB_READ_REG(hw, UPTCL);
0993     IXGB_READ_REG(hw, UPTCH);
0994     IXGB_READ_REG(hw, VPTCL);
0995     IXGB_READ_REG(hw, VPTCH);
0996     IXGB_READ_REG(hw, JPTCL);
0997     IXGB_READ_REG(hw, JPTCH);
0998     IXGB_READ_REG(hw, GOTCL);
0999     IXGB_READ_REG(hw, GOTCH);
1000     IXGB_READ_REG(hw, TOTL);
1001     IXGB_READ_REG(hw, TOTH);
1002     IXGB_READ_REG(hw, DC);
1003     IXGB_READ_REG(hw, PLT64C);
1004     IXGB_READ_REG(hw, TSCTC);
1005     IXGB_READ_REG(hw, TSCTFC);
1006     IXGB_READ_REG(hw, IBIC);
1007     IXGB_READ_REG(hw, RFC);
1008     IXGB_READ_REG(hw, LFC);
1009     IXGB_READ_REG(hw, PFRC);
1010     IXGB_READ_REG(hw, PFTC);
1011     IXGB_READ_REG(hw, MCFRC);
1012     IXGB_READ_REG(hw, MCFTC);
1013     IXGB_READ_REG(hw, XONRXC);
1014     IXGB_READ_REG(hw, XONTXC);
1015     IXGB_READ_REG(hw, XOFFRXC);
1016     IXGB_READ_REG(hw, XOFFTXC);
1017     IXGB_READ_REG(hw, RJC);
1018 }
1019 
1020 /******************************************************************************
1021  * Turns on the software controllable LED
1022  *
1023  * hw - Struct containing variables accessed by shared code
1024  *****************************************************************************/
1025 void
1026 ixgb_led_on(struct ixgb_hw *hw)
1027 {
1028     u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1029 
1030     /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1031     ctrl0_reg &= ~IXGB_CTRL0_SDP0;
1032     IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1033 }
1034 
1035 /******************************************************************************
1036  * Turns off the software controllable LED
1037  *
1038  * hw - Struct containing variables accessed by shared code
1039  *****************************************************************************/
1040 void
1041 ixgb_led_off(struct ixgb_hw *hw)
1042 {
1043     u32 ctrl0_reg = IXGB_READ_REG(hw, CTRL0);
1044 
1045     /* To turn off the LED, set software-definable pin 0 (SDP0). */
1046     ctrl0_reg |= IXGB_CTRL0_SDP0;
1047     IXGB_WRITE_REG(hw, CTRL0, ctrl0_reg);
1048 }
1049 
1050 /******************************************************************************
1051  * Gets the current PCI bus type, speed, and width of the hardware
1052  *
1053  * hw - Struct containing variables accessed by shared code
1054  *****************************************************************************/
1055 static void
1056 ixgb_get_bus_info(struct ixgb_hw *hw)
1057 {
1058     u32 status_reg;
1059 
1060     status_reg = IXGB_READ_REG(hw, STATUS);
1061 
1062     hw->bus.type = (status_reg & IXGB_STATUS_PCIX_MODE) ?
1063         ixgb_bus_type_pcix : ixgb_bus_type_pci;
1064 
1065     if (hw->bus.type == ixgb_bus_type_pci) {
1066         hw->bus.speed = (status_reg & IXGB_STATUS_PCI_SPD) ?
1067             ixgb_bus_speed_66 : ixgb_bus_speed_33;
1068     } else {
1069         switch (status_reg & IXGB_STATUS_PCIX_SPD_MASK) {
1070         case IXGB_STATUS_PCIX_SPD_66:
1071             hw->bus.speed = ixgb_bus_speed_66;
1072             break;
1073         case IXGB_STATUS_PCIX_SPD_100:
1074             hw->bus.speed = ixgb_bus_speed_100;
1075             break;
1076         case IXGB_STATUS_PCIX_SPD_133:
1077             hw->bus.speed = ixgb_bus_speed_133;
1078             break;
1079         default:
1080             hw->bus.speed = ixgb_bus_speed_reserved;
1081             break;
1082         }
1083     }
1084 
1085     hw->bus.width = (status_reg & IXGB_STATUS_BUS64) ?
1086         ixgb_bus_width_64 : ixgb_bus_width_32;
1087 }
1088 
1089 /******************************************************************************
1090  * Tests a MAC address to ensure it is a valid Individual Address
1091  *
1092  * mac_addr - pointer to MAC address.
1093  *
1094  *****************************************************************************/
1095 static bool
1096 mac_addr_valid(u8 *mac_addr)
1097 {
1098     bool is_valid = true;
1099     ENTER();
1100 
1101     /* Make sure it is not a multicast address */
1102     if (is_multicast_ether_addr(mac_addr)) {
1103         pr_debug("MAC address is multicast\n");
1104         is_valid = false;
1105     }
1106     /* Not a broadcast address */
1107     else if (is_broadcast_ether_addr(mac_addr)) {
1108         pr_debug("MAC address is broadcast\n");
1109         is_valid = false;
1110     }
1111     /* Reject the zero address */
1112     else if (is_zero_ether_addr(mac_addr)) {
1113         pr_debug("MAC address is all zeros\n");
1114         is_valid = false;
1115     }
1116     return is_valid;
1117 }
1118 
1119 /******************************************************************************
1120  * Resets the 10GbE link.  Waits the settle time and returns the state of
1121  * the link.
1122  *
1123  * hw - Struct containing variables accessed by shared code
1124  *****************************************************************************/
1125 static bool
1126 ixgb_link_reset(struct ixgb_hw *hw)
1127 {
1128     bool link_status = false;
1129     u8 wait_retries = MAX_RESET_ITERATIONS;
1130     u8 lrst_retries = MAX_RESET_ITERATIONS;
1131 
1132     do {
1133         /* Reset the link */
1134         IXGB_WRITE_REG(hw, CTRL0,
1135                    IXGB_READ_REG(hw, CTRL0) | IXGB_CTRL0_LRST);
1136 
1137         /* Wait for link-up and lane re-alignment */
1138         do {
1139             udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET);
1140             link_status =
1141                 ((IXGB_READ_REG(hw, STATUS) & IXGB_STATUS_LU)
1142                  && (IXGB_READ_REG(hw, XPCSS) &
1143                  IXGB_XPCSS_ALIGN_STATUS)) ? true : false;
1144         } while (!link_status && --wait_retries);
1145 
1146     } while (!link_status && --lrst_retries);
1147 
1148     return link_status;
1149 }
1150 
1151 /******************************************************************************
1152  * Resets the 10GbE optics module.
1153  *
1154  * hw - Struct containing variables accessed by shared code
1155  *****************************************************************************/
1156 static void
1157 ixgb_optics_reset(struct ixgb_hw *hw)
1158 {
1159     if (hw->phy_type == ixgb_phy_type_txn17401) {
1160         ixgb_write_phy_reg(hw,
1161                    MDIO_CTRL1,
1162                    IXGB_PHY_ADDRESS,
1163                    MDIO_MMD_PMAPMD,
1164                    MDIO_CTRL1_RESET);
1165 
1166         ixgb_read_phy_reg(hw, MDIO_CTRL1, IXGB_PHY_ADDRESS, MDIO_MMD_PMAPMD);
1167     }
1168 }
1169 
1170 /******************************************************************************
1171  * Resets the 10GbE optics module for Sun variant NIC.
1172  *
1173  * hw - Struct containing variables accessed by shared code
1174  *****************************************************************************/
1175 
1176 #define   IXGB_BCM8704_USER_PMD_TX_CTRL_REG         0xC803
1177 #define   IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL     0x0164
1178 #define   IXGB_BCM8704_USER_CTRL_REG                0xC800
1179 #define   IXGB_BCM8704_USER_CTRL_REG_VAL            0x7FBF
1180 #define   IXGB_BCM8704_USER_DEV3_ADDR               0x0003
1181 #define   IXGB_SUN_PHY_ADDRESS                      0x0000
1182 #define   IXGB_SUN_PHY_RESET_DELAY                     305
1183 
1184 static void
1185 ixgb_optics_reset_bcm(struct ixgb_hw *hw)
1186 {
1187     u32 ctrl = IXGB_READ_REG(hw, CTRL0);
1188     ctrl &= ~IXGB_CTRL0_SDP2;
1189     ctrl |= IXGB_CTRL0_SDP3;
1190     IXGB_WRITE_REG(hw, CTRL0, ctrl);
1191     IXGB_WRITE_FLUSH(hw);
1192 
1193     /* SerDes needs extra delay */
1194     msleep(IXGB_SUN_PHY_RESET_DELAY);
1195 
1196     /* Broadcom 7408L configuration */
1197     /* Reference clock config */
1198     ixgb_write_phy_reg(hw,
1199                IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1200                IXGB_SUN_PHY_ADDRESS,
1201                IXGB_BCM8704_USER_DEV3_ADDR,
1202                IXGB_BCM8704_USER_PMD_TX_CTRL_REG_VAL);
1203     /*  we must read the registers twice */
1204     ixgb_read_phy_reg(hw,
1205               IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1206               IXGB_SUN_PHY_ADDRESS,
1207               IXGB_BCM8704_USER_DEV3_ADDR);
1208     ixgb_read_phy_reg(hw,
1209               IXGB_BCM8704_USER_PMD_TX_CTRL_REG,
1210               IXGB_SUN_PHY_ADDRESS,
1211               IXGB_BCM8704_USER_DEV3_ADDR);
1212 
1213     ixgb_write_phy_reg(hw,
1214                IXGB_BCM8704_USER_CTRL_REG,
1215                IXGB_SUN_PHY_ADDRESS,
1216                IXGB_BCM8704_USER_DEV3_ADDR,
1217                IXGB_BCM8704_USER_CTRL_REG_VAL);
1218     ixgb_read_phy_reg(hw,
1219               IXGB_BCM8704_USER_CTRL_REG,
1220               IXGB_SUN_PHY_ADDRESS,
1221               IXGB_BCM8704_USER_DEV3_ADDR);
1222     ixgb_read_phy_reg(hw,
1223               IXGB_BCM8704_USER_CTRL_REG,
1224               IXGB_SUN_PHY_ADDRESS,
1225               IXGB_BCM8704_USER_DEV3_ADDR);
1226 
1227     /* SerDes needs extra delay */
1228     msleep(IXGB_SUN_PHY_RESET_DELAY);
1229 }
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