intel/ixgb/ixgb_ee.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright(c) 1999 - 2008 Intel Corporation. */
0003
0004 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0005
0006 #include "ixgb_hw.h"
0007 #include "ixgb_ee.h"
0008 /* Local prototypes */
0009 static u16 ixgb_shift_in_bits(struct ixgb_hw *hw);
0010
0011 static void ixgb_shift_out_bits(struct ixgb_hw *hw,
0012                 u16 data,
0013                 u16 count);
0014 static void ixgb_standby_eeprom(struct ixgb_hw *hw);
0015
0016 static bool ixgb_wait_eeprom_command(struct ixgb_hw *hw);
0017
0018 static void ixgb_cleanup_eeprom(struct ixgb_hw *hw);
0019
0020 /******************************************************************************
0021  * Raises the EEPROM's clock input.
0022  *
0023  * hw - Struct containing variables accessed by shared code
0024  * eecd_reg - EECD's current value
0025  *****************************************************************************/
0026 static void
0027 ixgb_raise_clock(struct ixgb_hw *hw,
0028           u32 *eecd_reg)
0029 {
0030     /* Raise the clock input to the EEPROM (by setting the SK bit), and then
0031      *  wait 50 microseconds.
0032      */
0033     *eecd_reg = *eecd_reg | IXGB_EECD_SK;
0034     IXGB_WRITE_REG(hw, EECD, *eecd_reg);
0035     IXGB_WRITE_FLUSH(hw);
0036     udelay(50);
0037 }
0038
0039 /******************************************************************************
0040  * Lowers the EEPROM's clock input.
0041  *
0042  * hw - Struct containing variables accessed by shared code
0043  * eecd_reg - EECD's current value
0044  *****************************************************************************/
0045 static void
0046 ixgb_lower_clock(struct ixgb_hw *hw,
0047           u32 *eecd_reg)
0048 {
0049     /* Lower the clock input to the EEPROM (by clearing the SK bit), and then
0050      * wait 50 microseconds.
0051      */
0052     *eecd_reg = *eecd_reg & ~IXGB_EECD_SK;
0053     IXGB_WRITE_REG(hw, EECD, *eecd_reg);
0054     IXGB_WRITE_FLUSH(hw);
0055     udelay(50);
0056 }
0057
0058 /******************************************************************************
0059  * Shift data bits out to the EEPROM.
0060  *
0061  * hw - Struct containing variables accessed by shared code
0062  * data - data to send to the EEPROM
0063  * count - number of bits to shift out
0064  *****************************************************************************/
0065 static void
0066 ixgb_shift_out_bits(struct ixgb_hw *hw,
0067                      u16 data,
0068                      u16 count)
0069 {
0070     u32 eecd_reg;
0071     u32 mask;
0072
0073     /* We need to shift "count" bits out to the EEPROM. So, value in the
0074      * "data" parameter will be shifted out to the EEPROM one bit at a time.
0075      * In order to do this, "data" must be broken down into bits.
0076      */
0077     mask = 0x01 << (count - 1);
0078     eecd_reg = IXGB_READ_REG(hw, EECD);
0079     eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
0080     do {
0081         /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
0082          * and then raising and then lowering the clock (the SK bit controls
0083          * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
0084          * by setting "DI" to "0" and then raising and then lowering the clock.
0085          */
0086         eecd_reg &= ~IXGB_EECD_DI;
0087
0088         if (data & mask)
0089             eecd_reg |= IXGB_EECD_DI;
0090
0091         IXGB_WRITE_REG(hw, EECD, eecd_reg);
0092         IXGB_WRITE_FLUSH(hw);
0093
0094         udelay(50);
0095
0096         ixgb_raise_clock(hw, &eecd_reg);
0097         ixgb_lower_clock(hw, &eecd_reg);
0098
0099         mask = mask >> 1;
0100
0101     } while (mask);
0102
0103     /* We leave the "DI" bit set to "0" when we leave this routine. */
0104     eecd_reg &= ~IXGB_EECD_DI;
0105     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0106 }
0107
0108 /******************************************************************************
0109  * Shift data bits in from the EEPROM
0110  *
0111  * hw - Struct containing variables accessed by shared code
0112  *****************************************************************************/
0113 static u16
0114 ixgb_shift_in_bits(struct ixgb_hw *hw)
0115 {
0116     u32 eecd_reg;
0117     u32 i;
0118     u16 data;
0119
0120     /* In order to read a register from the EEPROM, we need to shift 16 bits
0121      * in from the EEPROM. Bits are "shifted in" by raising the clock input to
0122      * the EEPROM (setting the SK bit), and then reading the value of the "DO"
0123      * bit.  During this "shifting in" process the "DI" bit should always be
0124      * clear..
0125      */
0126
0127     eecd_reg = IXGB_READ_REG(hw, EECD);
0128
0129     eecd_reg &= ~(IXGB_EECD_DO | IXGB_EECD_DI);
0130     data = 0;
0131
0132     for (i = 0; i < 16; i++) {
0133         data = data << 1;
0134         ixgb_raise_clock(hw, &eecd_reg);
0135
0136         eecd_reg = IXGB_READ_REG(hw, EECD);
0137
0138         eecd_reg &= ~(IXGB_EECD_DI);
0139         if (eecd_reg & IXGB_EECD_DO)
0140             data |= 1;
0141
0142         ixgb_lower_clock(hw, &eecd_reg);
0143     }
0144
0145     return data;
0146 }
0147
0148 /******************************************************************************
0149  * Prepares EEPROM for access
0150  *
0151  * hw - Struct containing variables accessed by shared code
0152  *
0153  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
0154  * function should be called before issuing a command to the EEPROM.
0155  *****************************************************************************/
0156 static void
0157 ixgb_setup_eeprom(struct ixgb_hw *hw)
0158 {
0159     u32 eecd_reg;
0160
0161     eecd_reg = IXGB_READ_REG(hw, EECD);
0162
0163     /*  Clear SK and DI  */
0164     eecd_reg &= ~(IXGB_EECD_SK | IXGB_EECD_DI);
0165     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0166
0167     /*  Set CS  */
0168     eecd_reg |= IXGB_EECD_CS;
0169     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0170 }
0171
0172 /******************************************************************************
0173  * Returns EEPROM to a "standby" state
0174  *
0175  * hw - Struct containing variables accessed by shared code
0176  *****************************************************************************/
0177 static void
0178 ixgb_standby_eeprom(struct ixgb_hw *hw)
0179 {
0180     u32 eecd_reg;
0181
0182     eecd_reg = IXGB_READ_REG(hw, EECD);
0183
0184     /*  Deselect EEPROM  */
0185     eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_SK);
0186     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0187     IXGB_WRITE_FLUSH(hw);
0188     udelay(50);
0189
0190     /*  Clock high  */
0191     eecd_reg |= IXGB_EECD_SK;
0192     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0193     IXGB_WRITE_FLUSH(hw);
0194     udelay(50);
0195
0196     /*  Select EEPROM  */
0197     eecd_reg |= IXGB_EECD_CS;
0198     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0199     IXGB_WRITE_FLUSH(hw);
0200     udelay(50);
0201
0202     /*  Clock low  */
0203     eecd_reg &= ~IXGB_EECD_SK;
0204     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0205     IXGB_WRITE_FLUSH(hw);
0206     udelay(50);
0207 }
0208
0209 /******************************************************************************
0210  * Raises then lowers the EEPROM's clock pin
0211  *
0212  * hw - Struct containing variables accessed by shared code
0213  *****************************************************************************/
0214 static void
0215 ixgb_clock_eeprom(struct ixgb_hw *hw)
0216 {
0217     u32 eecd_reg;
0218
0219     eecd_reg = IXGB_READ_REG(hw, EECD);
0220
0221     /*  Rising edge of clock  */
0222     eecd_reg |= IXGB_EECD_SK;
0223     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0224     IXGB_WRITE_FLUSH(hw);
0225     udelay(50);
0226
0227     /*  Falling edge of clock  */
0228     eecd_reg &= ~IXGB_EECD_SK;
0229     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0230     IXGB_WRITE_FLUSH(hw);
0231     udelay(50);
0232 }
0233
0234 /******************************************************************************
0235  * Terminates a command by lowering the EEPROM's chip select pin
0236  *
0237  * hw - Struct containing variables accessed by shared code
0238  *****************************************************************************/
0239 static void
0240 ixgb_cleanup_eeprom(struct ixgb_hw *hw)
0241 {
0242     u32 eecd_reg;
0243
0244     eecd_reg = IXGB_READ_REG(hw, EECD);
0245
0246     eecd_reg &= ~(IXGB_EECD_CS | IXGB_EECD_DI);
0247
0248     IXGB_WRITE_REG(hw, EECD, eecd_reg);
0249
0250     ixgb_clock_eeprom(hw);
0251 }
0252
0253 /******************************************************************************
0254  * Waits for the EEPROM to finish the current command.
0255  *
0256  * hw - Struct containing variables accessed by shared code
0257  *
0258  * The command is done when the EEPROM's data out pin goes high.
0259  *
0260  * Returns:
0261  *      true: EEPROM data pin is high before timeout.
0262  *      false:  Time expired.
0263  *****************************************************************************/
0264 static bool
0265 ixgb_wait_eeprom_command(struct ixgb_hw *hw)
0266 {
0267     u32 eecd_reg;
0268     u32 i;
0269
0270     /* Toggle the CS line.  This in effect tells to EEPROM to actually execute
0271      * the command in question.
0272      */
0273     ixgb_standby_eeprom(hw);
0274
0275     /* Now read DO repeatedly until is high (equal to '1').  The EEPROM will
0276      * signal that the command has been completed by raising the DO signal.
0277      * If DO does not go high in 10 milliseconds, then error out.
0278      */
0279     for (i = 0; i < 200; i++) {
0280         eecd_reg = IXGB_READ_REG(hw, EECD);
0281
0282         if (eecd_reg & IXGB_EECD_DO)
0283             return true;
0284
0285         udelay(50);
0286     }
0287     ASSERT(0);
0288     return false;
0289 }
0290
0291 /******************************************************************************
0292  * Verifies that the EEPROM has a valid checksum
0293  *
0294  * hw - Struct containing variables accessed by shared code
0295  *
0296  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
0297  * If the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
0298  * valid.
0299  *
0300  * Returns:
0301  *  true: Checksum is valid
0302  *  false: Checksum is not valid.
0303  *****************************************************************************/
0304 bool
0305 ixgb_validate_eeprom_checksum(struct ixgb_hw *hw)
0306 {
0307     u16 checksum = 0;
0308     u16 i;
0309
0310     for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++)
0311         checksum += ixgb_read_eeprom(hw, i);
0312
0313     if (checksum == (u16) EEPROM_SUM)
0314         return true;
0315     else
0316         return false;
0317 }
0318
0319 /******************************************************************************
0320  * Calculates the EEPROM checksum and writes it to the EEPROM
0321  *
0322  * hw - Struct containing variables accessed by shared code
0323  *
0324  * Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
0325  * Writes the difference to word offset 63 of the EEPROM.
0326  *****************************************************************************/
0327 void
0328 ixgb_update_eeprom_checksum(struct ixgb_hw *hw)
0329 {
0330     u16 checksum = 0;
0331     u16 i;
0332
0333     for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
0334         checksum += ixgb_read_eeprom(hw, i);
0335
0336     checksum = (u16) EEPROM_SUM - checksum;
0337
0338     ixgb_write_eeprom(hw, EEPROM_CHECKSUM_REG, checksum);
0339 }
0340
0341 /******************************************************************************
0342  * Writes a 16 bit word to a given offset in the EEPROM.
0343  *
0344  * hw - Struct containing variables accessed by shared code
0345  * reg - offset within the EEPROM to be written to
0346  * data - 16 bit word to be written to the EEPROM
0347  *
0348  * If ixgb_update_eeprom_checksum is not called after this function, the
0349  * EEPROM will most likely contain an invalid checksum.
0350  *
0351  *****************************************************************************/
0352 void
0353 ixgb_write_eeprom(struct ixgb_hw *hw, u16 offset, u16 data)
0354 {
0355     struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
0356
0357     /* Prepare the EEPROM for writing */
0358     ixgb_setup_eeprom(hw);
0359
0360     /*  Send the 9-bit EWEN (write enable) command to the EEPROM (5-bit opcode
0361      *  plus 4-bit dummy).  This puts the EEPROM into write/erase mode.
0362      */
0363     ixgb_shift_out_bits(hw, EEPROM_EWEN_OPCODE, 5);
0364     ixgb_shift_out_bits(hw, 0, 4);
0365
0366     /*  Prepare the EEPROM  */
0367     ixgb_standby_eeprom(hw);
0368
0369     /*  Send the Write command (3-bit opcode + 6-bit addr)  */
0370     ixgb_shift_out_bits(hw, EEPROM_WRITE_OPCODE, 3);
0371     ixgb_shift_out_bits(hw, offset, 6);
0372
0373     /*  Send the data  */
0374     ixgb_shift_out_bits(hw, data, 16);
0375
0376     ixgb_wait_eeprom_command(hw);
0377
0378     /*  Recover from write  */
0379     ixgb_standby_eeprom(hw);
0380
0381     /* Send the 9-bit EWDS (write disable) command to the EEPROM (5-bit
0382      * opcode plus 4-bit dummy).  This takes the EEPROM out of write/erase
0383      * mode.
0384      */
0385     ixgb_shift_out_bits(hw, EEPROM_EWDS_OPCODE, 5);
0386     ixgb_shift_out_bits(hw, 0, 4);
0387
0388     /*  Done with writing  */
0389     ixgb_cleanup_eeprom(hw);
0390
0391     /* clear the init_ctrl_reg_1 to signify that the cache is invalidated */
0392     ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR);
0393 }
0394
0395 /******************************************************************************
0396  * Reads a 16 bit word from the EEPROM.
0397  *
0398  * hw - Struct containing variables accessed by shared code
0399  * offset - offset of 16 bit word in the EEPROM to read
0400  *
0401  * Returns:
0402  *  The 16-bit value read from the eeprom
0403  *****************************************************************************/
0404 u16
0405 ixgb_read_eeprom(struct ixgb_hw *hw,
0406           u16 offset)
0407 {
0408     u16 data;
0409
0410     /*  Prepare the EEPROM for reading  */
0411     ixgb_setup_eeprom(hw);
0412
0413     /*  Send the READ command (opcode + addr)  */
0414     ixgb_shift_out_bits(hw, EEPROM_READ_OPCODE, 3);
0415     /*
0416      * We have a 64 word EEPROM, there are 6 address bits
0417      */
0418     ixgb_shift_out_bits(hw, offset, 6);
0419
0420     /*  Read the data  */
0421     data = ixgb_shift_in_bits(hw);
0422
0423     /*  End this read operation  */
0424     ixgb_standby_eeprom(hw);
0425
0426     return data;
0427 }
0428
0429 /******************************************************************************
0430  * Reads eeprom and stores data in shared structure.
0431  * Validates eeprom checksum and eeprom signature.
0432  *
0433  * hw - Struct containing variables accessed by shared code
0434  *
0435  * Returns:
0436  *      true: if eeprom read is successful
0437  *      false: otherwise.
0438  *****************************************************************************/
0439 bool
0440 ixgb_get_eeprom_data(struct ixgb_hw *hw)
0441 {
0442     u16 i;
0443     u16 checksum = 0;
0444     struct ixgb_ee_map_type *ee_map;
0445
0446     ENTER();
0447
0448     ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
0449
0450     pr_debug("Reading eeprom data\n");
0451     for (i = 0; i < IXGB_EEPROM_SIZE ; i++) {
0452         u16 ee_data;
0453         ee_data = ixgb_read_eeprom(hw, i);
0454         checksum += ee_data;
0455         hw->eeprom[i] = cpu_to_le16(ee_data);
0456     }
0457
0458     if (checksum != (u16) EEPROM_SUM) {
0459         pr_debug("Checksum invalid\n");
0460         /* clear the init_ctrl_reg_1 to signify that the cache is
0461          * invalidated */
0462         ee_map->init_ctrl_reg_1 = cpu_to_le16(EEPROM_ICW1_SIGNATURE_CLEAR);
0463         return false;
0464     }
0465
0466     if ((ee_map->init_ctrl_reg_1 & cpu_to_le16(EEPROM_ICW1_SIGNATURE_MASK))
0467          != cpu_to_le16(EEPROM_ICW1_SIGNATURE_VALID)) {
0468         pr_debug("Signature invalid\n");
0469         return false;
0470     }
0471
0472     return true;
0473 }
0474
0475 /******************************************************************************
0476  * Local function to check if the eeprom signature is good
0477  * If the eeprom signature is good, calls ixgb)get_eeprom_data.
0478  *
0479  * hw - Struct containing variables accessed by shared code
0480  *
0481  * Returns:
0482  *      true: eeprom signature was good and the eeprom read was successful
0483  *      false: otherwise.
0484  ******************************************************************************/
0485 static bool
0486 ixgb_check_and_get_eeprom_data (struct ixgb_hw* hw)
0487 {
0488     struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
0489
0490     if ((ee_map->init_ctrl_reg_1 & cpu_to_le16(EEPROM_ICW1_SIGNATURE_MASK))
0491         == cpu_to_le16(EEPROM_ICW1_SIGNATURE_VALID)) {
0492         return true;
0493     } else {
0494         return ixgb_get_eeprom_data(hw);
0495     }
0496 }
0497
0498 /******************************************************************************
0499  * return a word from the eeprom
0500  *
0501  * hw - Struct containing variables accessed by shared code
0502  * index - Offset of eeprom word
0503  *
0504  * Returns:
0505  *          Word at indexed offset in eeprom, if valid, 0 otherwise.
0506  ******************************************************************************/
0507 __le16
0508 ixgb_get_eeprom_word(struct ixgb_hw *hw, u16 index)
0509 {
0510
0511     if (index < IXGB_EEPROM_SIZE && ixgb_check_and_get_eeprom_data(hw))
0512         return hw->eeprom[index];
0513
0514     return 0;
0515 }
0516
0517 /******************************************************************************
0518  * return the mac address from EEPROM
0519  *
0520  * hw       - Struct containing variables accessed by shared code
0521  * mac_addr - Ethernet Address if EEPROM contents are valid, 0 otherwise
0522  *
0523  * Returns: None.
0524  ******************************************************************************/
0525 void
0526 ixgb_get_ee_mac_addr(struct ixgb_hw *hw,
0527             u8 *mac_addr)
0528 {
0529     int i;
0530     struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
0531
0532     ENTER();
0533
0534     if (ixgb_check_and_get_eeprom_data(hw)) {
0535         for (i = 0; i < ETH_ALEN; i++) {
0536             mac_addr[i] = ee_map->mac_addr[i];
0537         }
0538         pr_debug("eeprom mac address = %pM\n", mac_addr);
0539     }
0540 }
0541
0542
0543 /******************************************************************************
0544  * return the Printed Board Assembly number from EEPROM
0545  *
0546  * hw - Struct containing variables accessed by shared code
0547  *
0548  * Returns:
0549  *          PBA number if EEPROM contents are valid, 0 otherwise
0550  ******************************************************************************/
0551 u32
0552 ixgb_get_ee_pba_number(struct ixgb_hw *hw)
0553 {
0554     if (ixgb_check_and_get_eeprom_data(hw))
0555         return le16_to_cpu(hw->eeprom[EEPROM_PBA_1_2_REG])
0556             | (le16_to_cpu(hw->eeprom[EEPROM_PBA_3_4_REG])<<16);
0557
0558     return 0;
0559 }
0560
0561
0562 /******************************************************************************
0563  * return the Device Id from EEPROM
0564  *
0565  * hw - Struct containing variables accessed by shared code
0566  *
0567  * Returns:
0568  *          Device Id if EEPROM contents are valid, 0 otherwise
0569  ******************************************************************************/
0570 u16
0571 ixgb_get_ee_device_id(struct ixgb_hw *hw)
0572 {
0573     struct ixgb_ee_map_type *ee_map = (struct ixgb_ee_map_type *)hw->eeprom;
0574
0575     if (ixgb_check_and_get_eeprom_data(hw))
0576         return le16_to_cpu(ee_map->device_id);
0577
0578     return 0;
0579 }
0580