intel/igc/igc_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c)  2018 Intel Corporation */
0003
0004 #ifndef _IGC_REGS_H_
0005 #define _IGC_REGS_H_
0006
0007 /* General Register Descriptions */
0008 #define IGC_CTRL        0x00000  /* Device Control - RW */
0009 #define IGC_STATUS      0x00008  /* Device Status - RO */
0010 #define IGC_EECD        0x00010  /* EEPROM/Flash Control - RW */
0011 #define IGC_CTRL_EXT        0x00018  /* Extended Device Control - RW */
0012 #define IGC_MDIC        0x00020  /* MDI Control - RW */
0013 #define IGC_CONNSW      0x00034  /* Copper/Fiber switch control - RW */
0014 #define IGC_VET         0x00038  /* VLAN Ether Type - RW */
0015 #define IGC_I225_PHPM       0x00E14  /* I225 PHY Power Management */
0016 #define IGC_GPHY_VERSION    0x0001E  /* I225 gPHY Firmware Version */
0017
0018 /* Internal Packet Buffer Size Registers */
0019 #define IGC_RXPBS       0x02404  /* Rx Packet Buffer Size - RW */
0020 #define IGC_TXPBS       0x03404  /* Tx Packet Buffer Size - RW */
0021
0022 /* NVM  Register Descriptions */
0023 #define IGC_EERD        0x12014  /* EEprom mode read - RW */
0024 #define IGC_EEWR        0x12018  /* EEprom mode write - RW */
0025
0026 /* Flow Control Register Descriptions */
0027 #define IGC_FCAL        0x00028  /* FC Address Low - RW */
0028 #define IGC_FCAH        0x0002C  /* FC Address High - RW */
0029 #define IGC_FCT         0x00030  /* FC Type - RW */
0030 #define IGC_FCTTV       0x00170  /* FC Transmit Timer - RW */
0031 #define IGC_FCRTL       0x02160  /* FC Receive Threshold Low - RW */
0032 #define IGC_FCRTH       0x02168  /* FC Receive Threshold High - RW */
0033 #define IGC_FCRTV       0x02460  /* FC Refresh Timer Value - RW */
0034
0035 /* Semaphore registers */
0036 #define IGC_SW_FW_SYNC      0x05B5C  /* SW-FW Synchronization - RW */
0037 #define IGC_SWSM        0x05B50  /* SW Semaphore */
0038 #define IGC_FWSM        0x05B54  /* FW Semaphore */
0039
0040 /* Function Active and Power State to MNG */
0041 #define IGC_FACTPS      0x05B30
0042
0043 /* Interrupt Register Description */
0044 #define IGC_EICR        0x01580  /* Ext. Interrupt Cause read - W0 */
0045 #define IGC_EICS        0x01520  /* Ext. Interrupt Cause Set - W0 */
0046 #define IGC_EIMS        0x01524  /* Ext. Interrupt Mask Set/Read - RW */
0047 #define IGC_EIMC        0x01528  /* Ext. Interrupt Mask Clear - WO */
0048 #define IGC_EIAC        0x0152C  /* Ext. Interrupt Auto Clear - RW */
0049 #define IGC_EIAM        0x01530  /* Ext. Interrupt Auto Mask - RW */
0050 #define IGC_ICR         0x01500  /* Intr Cause Read - RC/W1C */
0051 #define IGC_ICS         0x01504  /* Intr Cause Set - WO */
0052 #define IGC_IMS         0x01508  /* Intr Mask Set/Read - RW */
0053 #define IGC_IMC         0x0150C  /* Intr Mask Clear - WO */
0054 #define IGC_IAM         0x01510  /* Intr Ack Auto Mask- RW */
0055 /* Intr Throttle - RW */
0056 #define IGC_EITR(_n)        (0x01680 + (0x4 * (_n)))
0057 /* Interrupt Vector Allocation - RW */
0058 #define IGC_IVAR0       0x01700
0059 #define IGC_IVAR_MISC       0x01740  /* IVAR for "other" causes - RW */
0060 #define IGC_GPIE        0x01514  /* General Purpose Intr Enable - RW */
0061
0062 /* RSS registers */
0063 #define IGC_MRQC        0x05818 /* Multiple Receive Control - RW */
0064
0065 /* Filtering Registers */
0066 #define IGC_ETQF(_n)        (0x05CB0 + (4 * (_n))) /* EType Queue Fltr */
0067 #define IGC_FHFT(_n)        (0x09000 + (256 * (_n))) /* Flexible Host Filter */
0068 #define IGC_FHFT_EXT(_n)    (0x09A00 + (256 * (_n))) /* Flexible Host Filter Extended */
0069 #define IGC_FHFTSL      0x05804 /* Flex Filter indirect table select */
0070
0071 /* ETQF register bit definitions */
0072 #define IGC_ETQF_FILTER_ENABLE  BIT(26)
0073 #define IGC_ETQF_QUEUE_ENABLE   BIT(31)
0074 #define IGC_ETQF_QUEUE_SHIFT    16
0075 #define IGC_ETQF_QUEUE_MASK 0x00070000
0076 #define IGC_ETQF_ETYPE_MASK 0x0000FFFF
0077
0078 /* FHFT register bit definitions */
0079 #define IGC_FHFT_LENGTH_MASK    GENMASK(7, 0)
0080 #define IGC_FHFT_QUEUE_SHIFT    8
0081 #define IGC_FHFT_QUEUE_MASK GENMASK(10, 8)
0082 #define IGC_FHFT_PRIO_SHIFT 16
0083 #define IGC_FHFT_PRIO_MASK  GENMASK(18, 16)
0084 #define IGC_FHFT_IMM_INT    BIT(24)
0085 #define IGC_FHFT_DROP       BIT(25)
0086
0087 /* FHFTSL register bit definitions */
0088 #define IGC_FHFTSL_FTSL_SHIFT   0
0089 #define IGC_FHFTSL_FTSL_MASK    GENMASK(1, 0)
0090
0091 /* Redirection Table - RW Array */
0092 #define IGC_RETA(_i)        (0x05C00 + ((_i) * 4))
0093 /* RSS Random Key - RW Array */
0094 #define IGC_RSSRK(_i)       (0x05C80 + ((_i) * 4))
0095
0096 /* Receive Register Descriptions */
0097 #define IGC_RCTL        0x00100  /* Rx Control - RW */
0098 #define IGC_SRRCTL(_n)      (0x0C00C + ((_n) * 0x40))
0099 #define IGC_PSRTYPE(_i)     (0x05480 + ((_i) * 4))
0100 #define IGC_RDBAL(_n)       (0x0C000 + ((_n) * 0x40))
0101 #define IGC_RDBAH(_n)       (0x0C004 + ((_n) * 0x40))
0102 #define IGC_RDLEN(_n)       (0x0C008 + ((_n) * 0x40))
0103 #define IGC_RDH(_n)     (0x0C010 + ((_n) * 0x40))
0104 #define IGC_RDT(_n)     (0x0C018 + ((_n) * 0x40))
0105 #define IGC_RXDCTL(_n)      (0x0C028 + ((_n) * 0x40))
0106 #define IGC_RQDPC(_n)       (0x0C030 + ((_n) * 0x40))
0107 #define IGC_RXCSUM      0x05000  /* Rx Checksum Control - RW */
0108 #define IGC_RLPML       0x05004  /* Rx Long Packet Max Length */
0109 #define IGC_RFCTL       0x05008  /* Receive Filter Control*/
0110 #define IGC_MTA         0x05200  /* Multicast Table Array - RW Array */
0111 #define IGC_RA          0x05400  /* Receive Address - RW Array */
0112 #define IGC_UTA         0x0A000  /* Unicast Table Array - RW */
0113 #define IGC_RAL(_n)     (0x05400 + ((_n) * 0x08))
0114 #define IGC_RAH(_n)     (0x05404 + ((_n) * 0x08))
0115 #define IGC_VLANPQF     0x055B0  /* VLAN Priority Queue Filter - RW */
0116
0117 /* Transmit Register Descriptions */
0118 #define IGC_TCTL        0x00400  /* Tx Control - RW */
0119 #define IGC_TIPG        0x00410  /* Tx Inter-packet gap - RW */
0120 #define IGC_TDBAL(_n)       (0x0E000 + ((_n) * 0x40))
0121 #define IGC_TDBAH(_n)       (0x0E004 + ((_n) * 0x40))
0122 #define IGC_TDLEN(_n)       (0x0E008 + ((_n) * 0x40))
0123 #define IGC_TDH(_n)     (0x0E010 + ((_n) * 0x40))
0124 #define IGC_TDT(_n)     (0x0E018 + ((_n) * 0x40))
0125 #define IGC_TXDCTL(_n)      (0x0E028 + ((_n) * 0x40))
0126
0127 /* MMD Register Descriptions */
0128 #define IGC_MMDAC       13 /* MMD Access Control */
0129 #define IGC_MMDAAD      14 /* MMD Access Address/Data */
0130
0131 /* Statistics Register Descriptions */
0132 #define IGC_CRCERRS 0x04000  /* CRC Error Count - R/clr */
0133 #define IGC_ALGNERRC    0x04004  /* Alignment Error Count - R/clr */
0134 #define IGC_RXERRC  0x0400C  /* Receive Error Count - R/clr */
0135 #define IGC_MPC     0x04010  /* Missed Packet Count - R/clr */
0136 #define IGC_SCC     0x04014  /* Single Collision Count - R/clr */
0137 #define IGC_ECOL    0x04018  /* Excessive Collision Count - R/clr */
0138 #define IGC_MCC     0x0401C  /* Multiple Collision Count - R/clr */
0139 #define IGC_LATECOL 0x04020  /* Late Collision Count - R/clr */
0140 #define IGC_COLC    0x04028  /* Collision Count - R/clr */
0141 #define IGC_RERC    0x0402C  /* Receive Error Count - R/clr */
0142 #define IGC_DC      0x04030  /* Defer Count - R/clr */
0143 #define IGC_TNCRS   0x04034  /* Tx-No CRS - R/clr */
0144 #define IGC_HTDPMC  0x0403C  /* Host Transmit Discarded by MAC - R/clr */
0145 #define IGC_RLEC    0x04040  /* Receive Length Error Count - R/clr */
0146 #define IGC_XONRXC  0x04048  /* XON Rx Count - R/clr */
0147 #define IGC_XONTXC  0x0404C  /* XON Tx Count - R/clr */
0148 #define IGC_XOFFRXC 0x04050  /* XOFF Rx Count - R/clr */
0149 #define IGC_XOFFTXC 0x04054  /* XOFF Tx Count - R/clr */
0150 #define IGC_FCRUC   0x04058  /* Flow Control Rx Unsupported Count- R/clr */
0151 #define IGC_PRC64   0x0405C  /* Packets Rx (64 bytes) - R/clr */
0152 #define IGC_PRC127  0x04060  /* Packets Rx (65-127 bytes) - R/clr */
0153 #define IGC_PRC255  0x04064  /* Packets Rx (128-255 bytes) - R/clr */
0154 #define IGC_PRC511  0x04068  /* Packets Rx (255-511 bytes) - R/clr */
0155 #define IGC_PRC1023 0x0406C  /* Packets Rx (512-1023 bytes) - R/clr */
0156 #define IGC_PRC1522 0x04070  /* Packets Rx (1024-1522 bytes) - R/clr */
0157 #define IGC_GPRC    0x04074  /* Good Packets Rx Count - R/clr */
0158 #define IGC_BPRC    0x04078  /* Broadcast Packets Rx Count - R/clr */
0159 #define IGC_MPRC    0x0407C  /* Multicast Packets Rx Count - R/clr */
0160 #define IGC_GPTC    0x04080  /* Good Packets Tx Count - R/clr */
0161 #define IGC_GORCL   0x04088  /* Good Octets Rx Count Low - R/clr */
0162 #define IGC_GORCH   0x0408C  /* Good Octets Rx Count High - R/clr */
0163 #define IGC_GOTCL   0x04090  /* Good Octets Tx Count Low - R/clr */
0164 #define IGC_GOTCH   0x04094  /* Good Octets Tx Count High - R/clr */
0165 #define IGC_RNBC    0x040A0  /* Rx No Buffers Count - R/clr */
0166 #define IGC_RUC     0x040A4  /* Rx Undersize Count - R/clr */
0167 #define IGC_RFC     0x040A8  /* Rx Fragment Count - R/clr */
0168 #define IGC_ROC     0x040AC  /* Rx Oversize Count - R/clr */
0169 #define IGC_RJC     0x040B0  /* Rx Jabber Count - R/clr */
0170 #define IGC_MGTPRC  0x040B4  /* Management Packets Rx Count - R/clr */
0171 #define IGC_MGTPDC  0x040B8  /* Management Packets Dropped Count - R/clr */
0172 #define IGC_MGTPTC  0x040BC  /* Management Packets Tx Count - R/clr */
0173 #define IGC_TORL    0x040C0  /* Total Octets Rx Low - R/clr */
0174 #define IGC_TORH    0x040C4  /* Total Octets Rx High - R/clr */
0175 #define IGC_TOTL    0x040C8  /* Total Octets Tx Low - R/clr */
0176 #define IGC_TOTH    0x040CC  /* Total Octets Tx High - R/clr */
0177 #define IGC_TPR     0x040D0  /* Total Packets Rx - R/clr */
0178 #define IGC_TPT     0x040D4  /* Total Packets Tx - R/clr */
0179 #define IGC_PTC64   0x040D8  /* Packets Tx (64 bytes) - R/clr */
0180 #define IGC_PTC127  0x040DC  /* Packets Tx (65-127 bytes) - R/clr */
0181 #define IGC_PTC255  0x040E0  /* Packets Tx (128-255 bytes) - R/clr */
0182 #define IGC_PTC511  0x040E4  /* Packets Tx (256-511 bytes) - R/clr */
0183 #define IGC_PTC1023 0x040E8  /* Packets Tx (512-1023 bytes) - R/clr */
0184 #define IGC_PTC1522 0x040EC  /* Packets Tx (1024-1522 Bytes) - R/clr */
0185 #define IGC_MPTC    0x040F0  /* Multicast Packets Tx Count - R/clr */
0186 #define IGC_BPTC    0x040F4  /* Broadcast Packets Tx Count - R/clr */
0187 #define IGC_TSCTC   0x040F8  /* TCP Segmentation Context Tx - R/clr */
0188 #define IGC_IAC     0x04100  /* Interrupt Assertion Count */
0189 #define IGC_RPTHC   0x04104  /* Rx Packets To Host */
0190 #define IGC_TLPIC   0x04148  /* EEE Tx LPI Count */
0191 #define IGC_RLPIC   0x0414C  /* EEE Rx LPI Count */
0192 #define IGC_HGPTC   0x04118  /* Host Good Packets Tx Count */
0193 #define IGC_RXDMTC  0x04120  /* Rx Descriptor Minimum Threshold Count */
0194 #define IGC_HGORCL  0x04128  /* Host Good Octets Received Count Low */
0195 #define IGC_HGORCH  0x0412C  /* Host Good Octets Received Count High */
0196 #define IGC_HGOTCL  0x04130  /* Host Good Octets Transmit Count Low */
0197 #define IGC_HGOTCH  0x04134  /* Host Good Octets Transmit Count High */
0198 #define IGC_LENERRS 0x04138  /* Length Errors Count */
0199
0200 /* Time sync registers */
0201 #define IGC_TSICR   0x0B66C  /* Time Sync Interrupt Cause */
0202 #define IGC_TSIM    0x0B674  /* Time Sync Interrupt Mask Register */
0203 #define IGC_TSAUXC  0x0B640  /* Timesync Auxiliary Control register */
0204 #define IGC_TSYNCRXCTL  0x0B620  /* Rx Time Sync Control register - RW */
0205 #define IGC_TSYNCTXCTL  0x0B614  /* Tx Time Sync Control register - RW */
0206 #define IGC_TSYNCRXCFG  0x05F50  /* Time Sync Rx Configuration - RW */
0207 #define IGC_TSSDP   0x0003C  /* Time Sync SDP Configuration Register - RW */
0208 #define IGC_TRGTTIML0   0x0B644 /* Target Time Register 0 Low  - RW */
0209 #define IGC_TRGTTIMH0   0x0B648 /* Target Time Register 0 High - RW */
0210 #define IGC_TRGTTIML1   0x0B64C /* Target Time Register 1 Low  - RW */
0211 #define IGC_TRGTTIMH1   0x0B650 /* Target Time Register 1 High - RW */
0212 #define IGC_FREQOUT0    0x0B654 /* Frequency Out 0 Control Register - RW */
0213 #define IGC_FREQOUT1    0x0B658 /* Frequency Out 1 Control Register - RW */
0214 #define IGC_AUXSTMPL0   0x0B65C /* Auxiliary Time Stamp 0 Register Low  - RO */
0215 #define IGC_AUXSTMPH0   0x0B660 /* Auxiliary Time Stamp 0 Register High - RO */
0216 #define IGC_AUXSTMPL1   0x0B664 /* Auxiliary Time Stamp 1 Register Low  - RO */
0217 #define IGC_AUXSTMPH1   0x0B668 /* Auxiliary Time Stamp 1 Register High - RO */
0218
0219 #define IGC_IMIR(_i)    (0x05A80 + ((_i) * 4))  /* Immediate Interrupt */
0220 #define IGC_IMIREXT(_i) (0x05AA0 + ((_i) * 4))  /* Immediate INTR Ext*/
0221
0222 #define IGC_FTQF(_n)    (0x059E0 + (4 * (_n)))  /* 5-tuple Queue Fltr */
0223
0224 /* Transmit Scheduling Registers */
0225 #define IGC_TQAVCTRL        0x3570
0226 #define IGC_TXQCTL(_n)      (0x3344 + 0x4 * (_n))
0227 #define IGC_BASET_L     0x3314
0228 #define IGC_BASET_H     0x3318
0229 #define IGC_QBVCYCLET       0x331C
0230 #define IGC_QBVCYCLET_S     0x3320
0231
0232 #define IGC_STQT(_n)        (0x3324 + 0x4 * (_n))
0233 #define IGC_ENDQT(_n)       (0x3334 + 0x4 * (_n))
0234 #define IGC_DTXMXPKTSZ      0x355C
0235
0236 #define IGC_TQAVCC(_n)      (0x3004 + ((_n) * 0x40))
0237 #define IGC_TQAVHC(_n)      (0x300C + ((_n) * 0x40))
0238
0239 /* System Time Registers */
0240 #define IGC_SYSTIML 0x0B600  /* System time register Low - RO */
0241 #define IGC_SYSTIMH 0x0B604  /* System time register High - RO */
0242 #define IGC_SYSTIMR 0x0B6F8  /* System time register Residue */
0243 #define IGC_TIMINCA 0x0B608  /* Increment attributes register - RW */
0244
0245 #define IGC_TXSTMPL 0x0B618  /* Tx timestamp value Low - RO */
0246 #define IGC_TXSTMPH 0x0B61C  /* Tx timestamp value High - RO */
0247
0248 #define IGC_TIMADJ  0x0B60C  /* Time Adjustment Offset Register */
0249
0250 /* PCIe Registers */
0251 #define IGC_PTM_CTRL        0x12540  /* PTM Control */
0252 #define IGC_PTM_STAT        0x12544  /* PTM Status */
0253 #define IGC_PTM_CYCLE_CTRL  0x1254C  /* PTM Cycle Control */
0254
0255 /* PTM Time registers */
0256 #define IGC_PTM_T1_TIM0_L   0x12558  /* T1 on Timer 0 Low */
0257 #define IGC_PTM_T1_TIM0_H   0x1255C  /* T1 on Timer 0 High */
0258
0259 #define IGC_PTM_CURR_T2_L   0x1258C  /* Current T2 Low */
0260 #define IGC_PTM_CURR_T2_H   0x12590  /* Current T2 High */
0261 #define IGC_PTM_PREV_T2_L   0x12584  /* Previous T2 Low */
0262 #define IGC_PTM_PREV_T2_H   0x12588  /* Previous T2 High */
0263 #define IGC_PTM_PREV_T4M1   0x12578  /* T4 Minus T1 on previous PTM Cycle */
0264 #define IGC_PTM_CURR_T4M1   0x1257C  /* T4 Minus T1 on this PTM Cycle */
0265 #define IGC_PTM_PREV_T3M2   0x12580  /* T3 Minus T2 on previous PTM Cycle */
0266 #define IGC_PTM_TDELAY      0x12594  /* PTM PCIe Link Delay */
0267
0268 #define IGC_PCIE_DIG_DELAY  0x12550  /* PCIe Digital Delay */
0269 #define IGC_PCIE_PHY_DELAY  0x12554  /* PCIe PHY Delay */
0270
0271 /* Management registers */
0272 #define IGC_MANC    0x05820  /* Management Control - RW */
0273
0274 /* Shadow Ram Write Register - RW */
0275 #define IGC_SRWR    0x12018
0276
0277 /* Wake Up registers */
0278 #define IGC_WUC     0x05800  /* Wakeup Control - RW */
0279 #define IGC_WUFC    0x05808  /* Wakeup Filter Control - RW */
0280 #define IGC_WUS     0x05810  /* Wakeup Status - R/W1C */
0281 #define IGC_WUPL    0x05900  /* Wakeup Packet Length - RW */
0282 #define IGC_WUFC_EXT    0x0580C  /* Wakeup Filter Control Register Extended - RW */
0283
0284 /* Wake Up packet memory */
0285 #define IGC_WUPM_REG(_i)    (0x05A00 + ((_i) * 4))
0286
0287 /* Energy Efficient Ethernet "EEE" registers */
0288 #define IGC_EEER    0x0E30 /* Energy Efficient Ethernet "EEE"*/
0289 #define IGC_IPCNFG  0x0E38 /* Internal PHY Configuration */
0290 #define IGC_EEE_SU  0x0E34 /* EEE Setup */
0291
0292 /* LTR registers */
0293 #define IGC_LTRC    0x01A0 /* Latency Tolerance Reporting Control */
0294 #define IGC_DMACR   0x02508 /* DMA Coalescing Control Register */
0295 #define IGC_LTRMINV 0x5BB0 /* LTR Minimum Value */
0296 #define IGC_LTRMAXV 0x5BB4 /* LTR Maximum Value */
0297
0298 /* forward declaration */
0299 struct igc_hw;
0300 u32 igc_rd32(struct igc_hw *hw, u32 reg);
0301
0302 /* write operations, indexed using DWORDS */
0303 #define wr32(reg, val) \
0304 do { \
0305     u8 __iomem *hw_addr = READ_ONCE((hw)->hw_addr); \
0306     if (!IGC_REMOVED(hw_addr)) \
0307         writel((val), &hw_addr[(reg)]); \
0308 } while (0)
0309
0310 #define rd32(reg) (igc_rd32(hw, reg))
0311
0312 #define wrfl() ((void)rd32(IGC_STATUS))
0313
0314 #define array_wr32(reg, offset, value) \
0315     wr32((reg) + ((offset) << 2), (value))
0316
0317 #define array_rd32(reg, offset) (igc_rd32(hw, (reg) + ((offset) << 2)))
0318
0319 #define IGC_REMOVED(h) unlikely(!(h))
0320
0321 #endif