Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c)  2019 Intel Corporation */
0003 
0004 #include "igc.h"
0005 
0006 #include <linux/module.h>
0007 #include <linux/device.h>
0008 #include <linux/pci.h>
0009 #include <linux/ptp_classify.h>
0010 #include <linux/clocksource.h>
0011 #include <linux/ktime.h>
0012 #include <linux/delay.h>
0013 #include <linux/iopoll.h>
0014 
0015 #define INCVALUE_MASK       0x7fffffff
0016 #define ISGN            0x80000000
0017 
0018 #define IGC_PTP_TX_TIMEOUT      (HZ * 15)
0019 
0020 #define IGC_PTM_STAT_SLEEP      2
0021 #define IGC_PTM_STAT_TIMEOUT        100
0022 
0023 /* SYSTIM read access for I225 */
0024 void igc_ptp_read(struct igc_adapter *adapter, struct timespec64 *ts)
0025 {
0026     struct igc_hw *hw = &adapter->hw;
0027     u32 sec, nsec;
0028 
0029     /* The timestamp is latched when SYSTIML is read. */
0030     nsec = rd32(IGC_SYSTIML);
0031     sec = rd32(IGC_SYSTIMH);
0032 
0033     ts->tv_sec = sec;
0034     ts->tv_nsec = nsec;
0035 }
0036 
0037 static void igc_ptp_write_i225(struct igc_adapter *adapter,
0038                    const struct timespec64 *ts)
0039 {
0040     struct igc_hw *hw = &adapter->hw;
0041 
0042     wr32(IGC_SYSTIML, ts->tv_nsec);
0043     wr32(IGC_SYSTIMH, ts->tv_sec);
0044 }
0045 
0046 static int igc_ptp_adjfine_i225(struct ptp_clock_info *ptp, long scaled_ppm)
0047 {
0048     struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
0049                            ptp_caps);
0050     struct igc_hw *hw = &igc->hw;
0051     int neg_adj = 0;
0052     u64 rate;
0053     u32 inca;
0054 
0055     if (scaled_ppm < 0) {
0056         neg_adj = 1;
0057         scaled_ppm = -scaled_ppm;
0058     }
0059     rate = scaled_ppm;
0060     rate <<= 14;
0061     rate = div_u64(rate, 78125);
0062 
0063     inca = rate & INCVALUE_MASK;
0064     if (neg_adj)
0065         inca |= ISGN;
0066 
0067     wr32(IGC_TIMINCA, inca);
0068 
0069     return 0;
0070 }
0071 
0072 static int igc_ptp_adjtime_i225(struct ptp_clock_info *ptp, s64 delta)
0073 {
0074     struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
0075                            ptp_caps);
0076     struct timespec64 now, then = ns_to_timespec64(delta);
0077     unsigned long flags;
0078 
0079     spin_lock_irqsave(&igc->tmreg_lock, flags);
0080 
0081     igc_ptp_read(igc, &now);
0082     now = timespec64_add(now, then);
0083     igc_ptp_write_i225(igc, (const struct timespec64 *)&now);
0084 
0085     spin_unlock_irqrestore(&igc->tmreg_lock, flags);
0086 
0087     return 0;
0088 }
0089 
0090 static int igc_ptp_gettimex64_i225(struct ptp_clock_info *ptp,
0091                    struct timespec64 *ts,
0092                    struct ptp_system_timestamp *sts)
0093 {
0094     struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
0095                            ptp_caps);
0096     struct igc_hw *hw = &igc->hw;
0097     unsigned long flags;
0098 
0099     spin_lock_irqsave(&igc->tmreg_lock, flags);
0100 
0101     ptp_read_system_prets(sts);
0102     ts->tv_nsec = rd32(IGC_SYSTIML);
0103     ts->tv_sec = rd32(IGC_SYSTIMH);
0104     ptp_read_system_postts(sts);
0105 
0106     spin_unlock_irqrestore(&igc->tmreg_lock, flags);
0107 
0108     return 0;
0109 }
0110 
0111 static int igc_ptp_settime_i225(struct ptp_clock_info *ptp,
0112                 const struct timespec64 *ts)
0113 {
0114     struct igc_adapter *igc = container_of(ptp, struct igc_adapter,
0115                            ptp_caps);
0116     unsigned long flags;
0117 
0118     spin_lock_irqsave(&igc->tmreg_lock, flags);
0119 
0120     igc_ptp_write_i225(igc, ts);
0121 
0122     spin_unlock_irqrestore(&igc->tmreg_lock, flags);
0123 
0124     return 0;
0125 }
0126 
0127 static void igc_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
0128 {
0129     u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
0130     static const u32 mask[IGC_N_SDP] = {
0131         IGC_CTRL_SDP0_DIR,
0132         IGC_CTRL_SDP1_DIR,
0133         IGC_CTRL_EXT_SDP2_DIR,
0134         IGC_CTRL_EXT_SDP3_DIR,
0135     };
0136 
0137     if (input)
0138         *ptr &= ~mask[pin];
0139     else
0140         *ptr |= mask[pin];
0141 }
0142 
0143 static void igc_pin_perout(struct igc_adapter *igc, int chan, int pin, int freq)
0144 {
0145     static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
0146         IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
0147     };
0148     static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
0149         IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
0150     };
0151     static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
0152         IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
0153     };
0154     static const u32 igc_ts_sdp_sel_tt0[IGC_N_SDP] = {
0155         IGC_TS_SDP0_SEL_TT0, IGC_TS_SDP1_SEL_TT0,
0156         IGC_TS_SDP2_SEL_TT0, IGC_TS_SDP3_SEL_TT0,
0157     };
0158     static const u32 igc_ts_sdp_sel_tt1[IGC_N_SDP] = {
0159         IGC_TS_SDP0_SEL_TT1, IGC_TS_SDP1_SEL_TT1,
0160         IGC_TS_SDP2_SEL_TT1, IGC_TS_SDP3_SEL_TT1,
0161     };
0162     static const u32 igc_ts_sdp_sel_fc0[IGC_N_SDP] = {
0163         IGC_TS_SDP0_SEL_FC0, IGC_TS_SDP1_SEL_FC0,
0164         IGC_TS_SDP2_SEL_FC0, IGC_TS_SDP3_SEL_FC0,
0165     };
0166     static const u32 igc_ts_sdp_sel_fc1[IGC_N_SDP] = {
0167         IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
0168         IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
0169     };
0170     static const u32 igc_ts_sdp_sel_clr[IGC_N_SDP] = {
0171         IGC_TS_SDP0_SEL_FC1, IGC_TS_SDP1_SEL_FC1,
0172         IGC_TS_SDP2_SEL_FC1, IGC_TS_SDP3_SEL_FC1,
0173     };
0174     struct igc_hw *hw = &igc->hw;
0175     u32 ctrl, ctrl_ext, tssdp = 0;
0176 
0177     ctrl = rd32(IGC_CTRL);
0178     ctrl_ext = rd32(IGC_CTRL_EXT);
0179     tssdp = rd32(IGC_TSSDP);
0180 
0181     igc_pin_direction(pin, 0, &ctrl, &ctrl_ext);
0182 
0183     /* Make sure this pin is not enabled as an input. */
0184     if ((tssdp & IGC_AUX0_SEL_SDP3) == igc_aux0_sel_sdp[pin])
0185         tssdp &= ~IGC_AUX0_TS_SDP_EN;
0186 
0187     if ((tssdp & IGC_AUX1_SEL_SDP3) == igc_aux1_sel_sdp[pin])
0188         tssdp &= ~IGC_AUX1_TS_SDP_EN;
0189 
0190     tssdp &= ~igc_ts_sdp_sel_clr[pin];
0191     if (freq) {
0192         if (chan == 1)
0193             tssdp |= igc_ts_sdp_sel_fc1[pin];
0194         else
0195             tssdp |= igc_ts_sdp_sel_fc0[pin];
0196     } else {
0197         if (chan == 1)
0198             tssdp |= igc_ts_sdp_sel_tt1[pin];
0199         else
0200             tssdp |= igc_ts_sdp_sel_tt0[pin];
0201     }
0202     tssdp |= igc_ts_sdp_en[pin];
0203 
0204     wr32(IGC_TSSDP, tssdp);
0205     wr32(IGC_CTRL, ctrl);
0206     wr32(IGC_CTRL_EXT, ctrl_ext);
0207 }
0208 
0209 static void igc_pin_extts(struct igc_adapter *igc, int chan, int pin)
0210 {
0211     static const u32 igc_aux0_sel_sdp[IGC_N_SDP] = {
0212         IGC_AUX0_SEL_SDP0, IGC_AUX0_SEL_SDP1, IGC_AUX0_SEL_SDP2, IGC_AUX0_SEL_SDP3,
0213     };
0214     static const u32 igc_aux1_sel_sdp[IGC_N_SDP] = {
0215         IGC_AUX1_SEL_SDP0, IGC_AUX1_SEL_SDP1, IGC_AUX1_SEL_SDP2, IGC_AUX1_SEL_SDP3,
0216     };
0217     static const u32 igc_ts_sdp_en[IGC_N_SDP] = {
0218         IGC_TS_SDP0_EN, IGC_TS_SDP1_EN, IGC_TS_SDP2_EN, IGC_TS_SDP3_EN,
0219     };
0220     struct igc_hw *hw = &igc->hw;
0221     u32 ctrl, ctrl_ext, tssdp = 0;
0222 
0223     ctrl = rd32(IGC_CTRL);
0224     ctrl_ext = rd32(IGC_CTRL_EXT);
0225     tssdp = rd32(IGC_TSSDP);
0226 
0227     igc_pin_direction(pin, 1, &ctrl, &ctrl_ext);
0228 
0229     /* Make sure this pin is not enabled as an output. */
0230     tssdp &= ~igc_ts_sdp_en[pin];
0231 
0232     if (chan == 1) {
0233         tssdp &= ~IGC_AUX1_SEL_SDP3;
0234         tssdp |= igc_aux1_sel_sdp[pin] | IGC_AUX1_TS_SDP_EN;
0235     } else {
0236         tssdp &= ~IGC_AUX0_SEL_SDP3;
0237         tssdp |= igc_aux0_sel_sdp[pin] | IGC_AUX0_TS_SDP_EN;
0238     }
0239 
0240     wr32(IGC_TSSDP, tssdp);
0241     wr32(IGC_CTRL, ctrl);
0242     wr32(IGC_CTRL_EXT, ctrl_ext);
0243 }
0244 
0245 static int igc_ptp_feature_enable_i225(struct ptp_clock_info *ptp,
0246                        struct ptp_clock_request *rq, int on)
0247 {
0248     struct igc_adapter *igc =
0249         container_of(ptp, struct igc_adapter, ptp_caps);
0250     struct igc_hw *hw = &igc->hw;
0251     unsigned long flags;
0252     struct timespec64 ts;
0253     int use_freq = 0, pin = -1;
0254     u32 tsim, tsauxc, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
0255     s64 ns;
0256 
0257     switch (rq->type) {
0258     case PTP_CLK_REQ_EXTTS:
0259         /* Reject requests with unsupported flags */
0260         if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
0261                     PTP_RISING_EDGE |
0262                     PTP_FALLING_EDGE |
0263                     PTP_STRICT_FLAGS))
0264             return -EOPNOTSUPP;
0265 
0266         /* Reject requests failing to enable both edges. */
0267         if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
0268             (rq->extts.flags & PTP_ENABLE_FEATURE) &&
0269             (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
0270             return -EOPNOTSUPP;
0271 
0272         if (on) {
0273             pin = ptp_find_pin(igc->ptp_clock, PTP_PF_EXTTS,
0274                        rq->extts.index);
0275             if (pin < 0)
0276                 return -EBUSY;
0277         }
0278         if (rq->extts.index == 1) {
0279             tsauxc_mask = IGC_TSAUXC_EN_TS1;
0280             tsim_mask = IGC_TSICR_AUTT1;
0281         } else {
0282             tsauxc_mask = IGC_TSAUXC_EN_TS0;
0283             tsim_mask = IGC_TSICR_AUTT0;
0284         }
0285         spin_lock_irqsave(&igc->tmreg_lock, flags);
0286         tsauxc = rd32(IGC_TSAUXC);
0287         tsim = rd32(IGC_TSIM);
0288         if (on) {
0289             igc_pin_extts(igc, rq->extts.index, pin);
0290             tsauxc |= tsauxc_mask;
0291             tsim |= tsim_mask;
0292         } else {
0293             tsauxc &= ~tsauxc_mask;
0294             tsim &= ~tsim_mask;
0295         }
0296         wr32(IGC_TSAUXC, tsauxc);
0297         wr32(IGC_TSIM, tsim);
0298         spin_unlock_irqrestore(&igc->tmreg_lock, flags);
0299         return 0;
0300 
0301     case PTP_CLK_REQ_PEROUT:
0302         /* Reject requests with unsupported flags */
0303         if (rq->perout.flags)
0304             return -EOPNOTSUPP;
0305 
0306         if (on) {
0307             pin = ptp_find_pin(igc->ptp_clock, PTP_PF_PEROUT,
0308                        rq->perout.index);
0309             if (pin < 0)
0310                 return -EBUSY;
0311         }
0312         ts.tv_sec = rq->perout.period.sec;
0313         ts.tv_nsec = rq->perout.period.nsec;
0314         ns = timespec64_to_ns(&ts);
0315         ns = ns >> 1;
0316         if (on && (ns <= 70000000LL || ns == 125000000LL ||
0317                ns == 250000000LL || ns == 500000000LL)) {
0318             if (ns < 8LL)
0319                 return -EINVAL;
0320             use_freq = 1;
0321         }
0322         ts = ns_to_timespec64(ns);
0323         if (rq->perout.index == 1) {
0324             if (use_freq) {
0325                 tsauxc_mask = IGC_TSAUXC_EN_CLK1;
0326                 tsim_mask = 0;
0327             } else {
0328                 tsauxc_mask = IGC_TSAUXC_EN_TT1;
0329                 tsim_mask = IGC_TSICR_TT1;
0330             }
0331             trgttiml = IGC_TRGTTIML1;
0332             trgttimh = IGC_TRGTTIMH1;
0333             freqout = IGC_FREQOUT1;
0334         } else {
0335             if (use_freq) {
0336                 tsauxc_mask = IGC_TSAUXC_EN_CLK0;
0337                 tsim_mask = 0;
0338             } else {
0339                 tsauxc_mask = IGC_TSAUXC_EN_TT0;
0340                 tsim_mask = IGC_TSICR_TT0;
0341             }
0342             trgttiml = IGC_TRGTTIML0;
0343             trgttimh = IGC_TRGTTIMH0;
0344             freqout = IGC_FREQOUT0;
0345         }
0346         spin_lock_irqsave(&igc->tmreg_lock, flags);
0347         tsauxc = rd32(IGC_TSAUXC);
0348         tsim = rd32(IGC_TSIM);
0349         if (rq->perout.index == 1) {
0350             tsauxc &= ~(IGC_TSAUXC_EN_TT1 | IGC_TSAUXC_EN_CLK1);
0351             tsim &= ~IGC_TSICR_TT1;
0352         } else {
0353             tsauxc &= ~(IGC_TSAUXC_EN_TT0 | IGC_TSAUXC_EN_CLK0);
0354             tsim &= ~IGC_TSICR_TT0;
0355         }
0356         if (on) {
0357             int i = rq->perout.index;
0358 
0359             igc_pin_perout(igc, i, pin, use_freq);
0360             igc->perout[i].start.tv_sec = rq->perout.start.sec;
0361             igc->perout[i].start.tv_nsec = rq->perout.start.nsec;
0362             igc->perout[i].period.tv_sec = ts.tv_sec;
0363             igc->perout[i].period.tv_nsec = ts.tv_nsec;
0364             wr32(trgttimh, rq->perout.start.sec);
0365             /* For now, always select timer 0 as source. */
0366             wr32(trgttiml, rq->perout.start.nsec | IGC_TT_IO_TIMER_SEL_SYSTIM0);
0367             if (use_freq)
0368                 wr32(freqout, ns);
0369             tsauxc |= tsauxc_mask;
0370             tsim |= tsim_mask;
0371         }
0372         wr32(IGC_TSAUXC, tsauxc);
0373         wr32(IGC_TSIM, tsim);
0374         spin_unlock_irqrestore(&igc->tmreg_lock, flags);
0375         return 0;
0376 
0377     case PTP_CLK_REQ_PPS:
0378         spin_lock_irqsave(&igc->tmreg_lock, flags);
0379         tsim = rd32(IGC_TSIM);
0380         if (on)
0381             tsim |= IGC_TSICR_SYS_WRAP;
0382         else
0383             tsim &= ~IGC_TSICR_SYS_WRAP;
0384         igc->pps_sys_wrap_on = on;
0385         wr32(IGC_TSIM, tsim);
0386         spin_unlock_irqrestore(&igc->tmreg_lock, flags);
0387         return 0;
0388 
0389     default:
0390         break;
0391     }
0392 
0393     return -EOPNOTSUPP;
0394 }
0395 
0396 static int igc_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
0397                   enum ptp_pin_function func, unsigned int chan)
0398 {
0399     switch (func) {
0400     case PTP_PF_NONE:
0401     case PTP_PF_EXTTS:
0402     case PTP_PF_PEROUT:
0403         break;
0404     case PTP_PF_PHYSYNC:
0405         return -1;
0406     }
0407     return 0;
0408 }
0409 
0410 /**
0411  * igc_ptp_systim_to_hwtstamp - convert system time value to HW timestamp
0412  * @adapter: board private structure
0413  * @hwtstamps: timestamp structure to update
0414  * @systim: unsigned 64bit system time value
0415  *
0416  * We need to convert the system time value stored in the RX/TXSTMP registers
0417  * into a hwtstamp which can be used by the upper level timestamping functions.
0418  **/
0419 static void igc_ptp_systim_to_hwtstamp(struct igc_adapter *adapter,
0420                        struct skb_shared_hwtstamps *hwtstamps,
0421                        u64 systim)
0422 {
0423     switch (adapter->hw.mac.type) {
0424     case igc_i225:
0425         memset(hwtstamps, 0, sizeof(*hwtstamps));
0426         /* Upper 32 bits contain s, lower 32 bits contain ns. */
0427         hwtstamps->hwtstamp = ktime_set(systim >> 32,
0428                         systim & 0xFFFFFFFF);
0429         break;
0430     default:
0431         break;
0432     }
0433 }
0434 
0435 /**
0436  * igc_ptp_rx_pktstamp - Retrieve timestamp from Rx packet buffer
0437  * @adapter: Pointer to adapter the packet buffer belongs to
0438  * @buf: Pointer to packet buffer
0439  *
0440  * This function retrieves the timestamp saved in the beginning of packet
0441  * buffer. While two timestamps are available, one in timer0 reference and the
0442  * other in timer1 reference, this function considers only the timestamp in
0443  * timer0 reference.
0444  *
0445  * Returns timestamp value.
0446  */
0447 ktime_t igc_ptp_rx_pktstamp(struct igc_adapter *adapter, __le32 *buf)
0448 {
0449     ktime_t timestamp;
0450     u32 secs, nsecs;
0451     int adjust;
0452 
0453     /* Timestamps are saved in little endian at the beginning of the packet
0454      * buffer following the layout:
0455      *
0456      * DWORD: | 0              | 1              | 2              | 3              |
0457      * Field: | Timer1 SYSTIML | Timer1 SYSTIMH | Timer0 SYSTIML | Timer0 SYSTIMH |
0458      *
0459      * SYSTIML holds the nanoseconds part while SYSTIMH holds the seconds
0460      * part of the timestamp.
0461      */
0462     nsecs = le32_to_cpu(buf[2]);
0463     secs = le32_to_cpu(buf[3]);
0464 
0465     timestamp = ktime_set(secs, nsecs);
0466 
0467     /* Adjust timestamp for the RX latency based on link speed */
0468     switch (adapter->link_speed) {
0469     case SPEED_10:
0470         adjust = IGC_I225_RX_LATENCY_10;
0471         break;
0472     case SPEED_100:
0473         adjust = IGC_I225_RX_LATENCY_100;
0474         break;
0475     case SPEED_1000:
0476         adjust = IGC_I225_RX_LATENCY_1000;
0477         break;
0478     case SPEED_2500:
0479         adjust = IGC_I225_RX_LATENCY_2500;
0480         break;
0481     default:
0482         adjust = 0;
0483         netdev_warn_once(adapter->netdev, "Imprecise timestamp\n");
0484         break;
0485     }
0486 
0487     return ktime_sub_ns(timestamp, adjust);
0488 }
0489 
0490 static void igc_ptp_disable_rx_timestamp(struct igc_adapter *adapter)
0491 {
0492     struct igc_hw *hw = &adapter->hw;
0493     u32 val;
0494     int i;
0495 
0496     wr32(IGC_TSYNCRXCTL, 0);
0497 
0498     for (i = 0; i < adapter->num_rx_queues; i++) {
0499         val = rd32(IGC_SRRCTL(i));
0500         val &= ~IGC_SRRCTL_TIMESTAMP;
0501         wr32(IGC_SRRCTL(i), val);
0502     }
0503 
0504     val = rd32(IGC_RXPBS);
0505     val &= ~IGC_RXPBS_CFG_TS_EN;
0506     wr32(IGC_RXPBS, val);
0507 }
0508 
0509 static void igc_ptp_enable_rx_timestamp(struct igc_adapter *adapter)
0510 {
0511     struct igc_hw *hw = &adapter->hw;
0512     u32 val;
0513     int i;
0514 
0515     val = rd32(IGC_RXPBS);
0516     val |= IGC_RXPBS_CFG_TS_EN;
0517     wr32(IGC_RXPBS, val);
0518 
0519     for (i = 0; i < adapter->num_rx_queues; i++) {
0520         val = rd32(IGC_SRRCTL(i));
0521         /* FIXME: For now, only support retrieving RX timestamps from
0522          * timer 0.
0523          */
0524         val |= IGC_SRRCTL_TIMER1SEL(0) | IGC_SRRCTL_TIMER0SEL(0) |
0525                IGC_SRRCTL_TIMESTAMP;
0526         wr32(IGC_SRRCTL(i), val);
0527     }
0528 
0529     val = IGC_TSYNCRXCTL_ENABLED | IGC_TSYNCRXCTL_TYPE_ALL |
0530           IGC_TSYNCRXCTL_RXSYNSIG;
0531     wr32(IGC_TSYNCRXCTL, val);
0532 }
0533 
0534 static void igc_ptp_disable_tx_timestamp(struct igc_adapter *adapter)
0535 {
0536     struct igc_hw *hw = &adapter->hw;
0537 
0538     wr32(IGC_TSYNCTXCTL, 0);
0539 }
0540 
0541 static void igc_ptp_enable_tx_timestamp(struct igc_adapter *adapter)
0542 {
0543     struct igc_hw *hw = &adapter->hw;
0544 
0545     wr32(IGC_TSYNCTXCTL, IGC_TSYNCTXCTL_ENABLED | IGC_TSYNCTXCTL_TXSYNSIG);
0546 
0547     /* Read TXSTMP registers to discard any timestamp previously stored. */
0548     rd32(IGC_TXSTMPL);
0549     rd32(IGC_TXSTMPH);
0550 }
0551 
0552 /**
0553  * igc_ptp_set_timestamp_mode - setup hardware for timestamping
0554  * @adapter: networking device structure
0555  * @config: hwtstamp configuration
0556  *
0557  * Return: 0 in case of success, negative errno code otherwise.
0558  */
0559 static int igc_ptp_set_timestamp_mode(struct igc_adapter *adapter,
0560                       struct hwtstamp_config *config)
0561 {
0562     switch (config->tx_type) {
0563     case HWTSTAMP_TX_OFF:
0564         igc_ptp_disable_tx_timestamp(adapter);
0565         break;
0566     case HWTSTAMP_TX_ON:
0567         igc_ptp_enable_tx_timestamp(adapter);
0568         break;
0569     default:
0570         return -ERANGE;
0571     }
0572 
0573     switch (config->rx_filter) {
0574     case HWTSTAMP_FILTER_NONE:
0575         igc_ptp_disable_rx_timestamp(adapter);
0576         break;
0577     case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
0578     case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
0579     case HWTSTAMP_FILTER_PTP_V2_EVENT:
0580     case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
0581     case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
0582     case HWTSTAMP_FILTER_PTP_V2_SYNC:
0583     case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
0584     case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
0585     case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
0586     case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
0587     case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
0588     case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
0589     case HWTSTAMP_FILTER_NTP_ALL:
0590     case HWTSTAMP_FILTER_ALL:
0591         igc_ptp_enable_rx_timestamp(adapter);
0592         config->rx_filter = HWTSTAMP_FILTER_ALL;
0593         break;
0594     default:
0595         return -ERANGE;
0596     }
0597 
0598     return 0;
0599 }
0600 
0601 static void igc_ptp_tx_timeout(struct igc_adapter *adapter)
0602 {
0603     struct igc_hw *hw = &adapter->hw;
0604 
0605     dev_kfree_skb_any(adapter->ptp_tx_skb);
0606     adapter->ptp_tx_skb = NULL;
0607     adapter->tx_hwtstamp_timeouts++;
0608     clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
0609     /* Clear the tx valid bit in TSYNCTXCTL register to enable interrupt. */
0610     rd32(IGC_TXSTMPH);
0611     netdev_warn(adapter->netdev, "Tx timestamp timeout\n");
0612 }
0613 
0614 void igc_ptp_tx_hang(struct igc_adapter *adapter)
0615 {
0616     bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
0617                           IGC_PTP_TX_TIMEOUT);
0618 
0619     if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
0620         return;
0621 
0622     /* If we haven't received a timestamp within the timeout, it is
0623      * reasonable to assume that it will never occur, so we can unlock the
0624      * timestamp bit when this occurs.
0625      */
0626     if (timeout) {
0627         cancel_work_sync(&adapter->ptp_tx_work);
0628         igc_ptp_tx_timeout(adapter);
0629     }
0630 }
0631 
0632 /**
0633  * igc_ptp_tx_hwtstamp - utility function which checks for TX time stamp
0634  * @adapter: Board private structure
0635  *
0636  * If we were asked to do hardware stamping and such a time stamp is
0637  * available, then it must have been for this skb here because we only
0638  * allow only one such packet into the queue.
0639  */
0640 static void igc_ptp_tx_hwtstamp(struct igc_adapter *adapter)
0641 {
0642     struct sk_buff *skb = adapter->ptp_tx_skb;
0643     struct skb_shared_hwtstamps shhwtstamps;
0644     struct igc_hw *hw = &adapter->hw;
0645     int adjust = 0;
0646     u64 regval;
0647 
0648     if (WARN_ON_ONCE(!skb))
0649         return;
0650 
0651     regval = rd32(IGC_TXSTMPL);
0652     regval |= (u64)rd32(IGC_TXSTMPH) << 32;
0653     igc_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
0654 
0655     switch (adapter->link_speed) {
0656     case SPEED_10:
0657         adjust = IGC_I225_TX_LATENCY_10;
0658         break;
0659     case SPEED_100:
0660         adjust = IGC_I225_TX_LATENCY_100;
0661         break;
0662     case SPEED_1000:
0663         adjust = IGC_I225_TX_LATENCY_1000;
0664         break;
0665     case SPEED_2500:
0666         adjust = IGC_I225_TX_LATENCY_2500;
0667         break;
0668     }
0669 
0670     shhwtstamps.hwtstamp =
0671         ktime_add_ns(shhwtstamps.hwtstamp, adjust);
0672 
0673     /* Clear the lock early before calling skb_tstamp_tx so that
0674      * applications are not woken up before the lock bit is clear. We use
0675      * a copy of the skb pointer to ensure other threads can't change it
0676      * while we're notifying the stack.
0677      */
0678     adapter->ptp_tx_skb = NULL;
0679     clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
0680 
0681     /* Notify the stack and free the skb after we've unlocked */
0682     skb_tstamp_tx(skb, &shhwtstamps);
0683     dev_kfree_skb_any(skb);
0684 }
0685 
0686 /**
0687  * igc_ptp_tx_work
0688  * @work: pointer to work struct
0689  *
0690  * This work function polls the TSYNCTXCTL valid bit to determine when a
0691  * timestamp has been taken for the current stored skb.
0692  */
0693 static void igc_ptp_tx_work(struct work_struct *work)
0694 {
0695     struct igc_adapter *adapter = container_of(work, struct igc_adapter,
0696                            ptp_tx_work);
0697     struct igc_hw *hw = &adapter->hw;
0698     u32 tsynctxctl;
0699 
0700     if (!test_bit(__IGC_PTP_TX_IN_PROGRESS, &adapter->state))
0701         return;
0702 
0703     tsynctxctl = rd32(IGC_TSYNCTXCTL);
0704     if (WARN_ON_ONCE(!(tsynctxctl & IGC_TSYNCTXCTL_TXTT_0)))
0705         return;
0706 
0707     igc_ptp_tx_hwtstamp(adapter);
0708 }
0709 
0710 /**
0711  * igc_ptp_set_ts_config - set hardware time stamping config
0712  * @netdev: network interface device structure
0713  * @ifr: interface request data
0714  *
0715  **/
0716 int igc_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
0717 {
0718     struct igc_adapter *adapter = netdev_priv(netdev);
0719     struct hwtstamp_config config;
0720     int err;
0721 
0722     if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
0723         return -EFAULT;
0724 
0725     err = igc_ptp_set_timestamp_mode(adapter, &config);
0726     if (err)
0727         return err;
0728 
0729     /* save these settings for future reference */
0730     memcpy(&adapter->tstamp_config, &config,
0731            sizeof(adapter->tstamp_config));
0732 
0733     return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
0734         -EFAULT : 0;
0735 }
0736 
0737 /**
0738  * igc_ptp_get_ts_config - get hardware time stamping config
0739  * @netdev: network interface device structure
0740  * @ifr: interface request data
0741  *
0742  * Get the hwtstamp_config settings to return to the user. Rather than attempt
0743  * to deconstruct the settings from the registers, just return a shadow copy
0744  * of the last known settings.
0745  **/
0746 int igc_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
0747 {
0748     struct igc_adapter *adapter = netdev_priv(netdev);
0749     struct hwtstamp_config *config = &adapter->tstamp_config;
0750 
0751     return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
0752         -EFAULT : 0;
0753 }
0754 
0755 /* The two conditions below must be met for cross timestamping via
0756  * PCIe PTM:
0757  *
0758  * 1. We have an way to convert the timestamps in the PTM messages
0759  *    to something related to the system clocks (right now, only
0760  *    X86 systems with support for the Always Running Timer allow that);
0761  *
0762  * 2. We have PTM enabled in the path from the device to the PCIe root port.
0763  */
0764 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
0765 {
0766     if (!IS_ENABLED(CONFIG_X86_TSC))
0767         return false;
0768 
0769     /* FIXME: it was noticed that enabling support for PCIe PTM in
0770      * some i225-V models could cause lockups when bringing the
0771      * interface up/down. There should be no downsides to
0772      * disabling crosstimestamping support for i225-V, as it
0773      * doesn't have any PTP support. That way we gain some time
0774      * while root causing the issue.
0775      */
0776     if (adapter->pdev->device == IGC_DEV_ID_I225_V)
0777         return false;
0778 
0779     return pcie_ptm_enabled(adapter->pdev);
0780 }
0781 
0782 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
0783 {
0784 #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
0785     return convert_art_ns_to_tsc(tstamp);
0786 #else
0787     return (struct system_counterval_t) { };
0788 #endif
0789 }
0790 
0791 static void igc_ptm_log_error(struct igc_adapter *adapter, u32 ptm_stat)
0792 {
0793     struct net_device *netdev = adapter->netdev;
0794 
0795     switch (ptm_stat) {
0796     case IGC_PTM_STAT_RET_ERR:
0797         netdev_err(netdev, "PTM Error: Root port timeout\n");
0798         break;
0799     case IGC_PTM_STAT_BAD_PTM_RES:
0800         netdev_err(netdev, "PTM Error: Bad response, PTM Response Data expected\n");
0801         break;
0802     case IGC_PTM_STAT_T4M1_OVFL:
0803         netdev_err(netdev, "PTM Error: T4 minus T1 overflow\n");
0804         break;
0805     case IGC_PTM_STAT_ADJUST_1ST:
0806         netdev_err(netdev, "PTM Error: 1588 timer adjusted during first PTM cycle\n");
0807         break;
0808     case IGC_PTM_STAT_ADJUST_CYC:
0809         netdev_err(netdev, "PTM Error: 1588 timer adjusted during non-first PTM cycle\n");
0810         break;
0811     default:
0812         netdev_err(netdev, "PTM Error: Unknown error (%#x)\n", ptm_stat);
0813         break;
0814     }
0815 }
0816 
0817 static int igc_phc_get_syncdevicetime(ktime_t *device,
0818                       struct system_counterval_t *system,
0819                       void *ctx)
0820 {
0821     u32 stat, t2_curr_h, t2_curr_l, ctrl;
0822     struct igc_adapter *adapter = ctx;
0823     struct igc_hw *hw = &adapter->hw;
0824     int err, count = 100;
0825     ktime_t t1, t2_curr;
0826 
0827     /* Get a snapshot of system clocks to use as historic value. */
0828     ktime_get_snapshot(&adapter->snapshot);
0829 
0830     do {
0831         /* Doing this in a loop because in the event of a
0832          * badly timed (ha!) system clock adjustment, we may
0833          * get PTM errors from the PCI root, but these errors
0834          * are transitory. Repeating the process returns valid
0835          * data eventually.
0836          */
0837 
0838         /* To "manually" start the PTM cycle we need to clear and
0839          * then set again the TRIG bit.
0840          */
0841         ctrl = rd32(IGC_PTM_CTRL);
0842         ctrl &= ~IGC_PTM_CTRL_TRIG;
0843         wr32(IGC_PTM_CTRL, ctrl);
0844         ctrl |= IGC_PTM_CTRL_TRIG;
0845         wr32(IGC_PTM_CTRL, ctrl);
0846 
0847         /* The cycle only starts "for real" when software notifies
0848          * that it has read the registers, this is done by setting
0849          * VALID bit.
0850          */
0851         wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
0852 
0853         err = readx_poll_timeout(rd32, IGC_PTM_STAT, stat,
0854                      stat, IGC_PTM_STAT_SLEEP,
0855                      IGC_PTM_STAT_TIMEOUT);
0856         if (err < 0) {
0857             netdev_err(adapter->netdev, "Timeout reading IGC_PTM_STAT register\n");
0858             return err;
0859         }
0860 
0861         if ((stat & IGC_PTM_STAT_VALID) == IGC_PTM_STAT_VALID)
0862             break;
0863 
0864         if (stat & ~IGC_PTM_STAT_VALID) {
0865             /* An error occurred, log it. */
0866             igc_ptm_log_error(adapter, stat);
0867             /* The STAT register is write-1-to-clear (W1C),
0868              * so write the previous error status to clear it.
0869              */
0870             wr32(IGC_PTM_STAT, stat);
0871             continue;
0872         }
0873     } while (--count);
0874 
0875     if (!count) {
0876         netdev_err(adapter->netdev, "Exceeded number of tries for PTM cycle\n");
0877         return -ETIMEDOUT;
0878     }
0879 
0880     t1 = ktime_set(rd32(IGC_PTM_T1_TIM0_H), rd32(IGC_PTM_T1_TIM0_L));
0881 
0882     t2_curr_l = rd32(IGC_PTM_CURR_T2_L);
0883     t2_curr_h = rd32(IGC_PTM_CURR_T2_H);
0884 
0885     /* FIXME: When the register that tells the endianness of the
0886      * PTM registers are implemented, check them here and add the
0887      * appropriate conversion.
0888      */
0889     t2_curr_h = swab32(t2_curr_h);
0890 
0891     t2_curr = ((s64)t2_curr_h << 32 | t2_curr_l);
0892 
0893     *device = t1;
0894     *system = igc_device_tstamp_to_system(t2_curr);
0895 
0896     return 0;
0897 }
0898 
0899 static int igc_ptp_getcrosststamp(struct ptp_clock_info *ptp,
0900                   struct system_device_crosststamp *cts)
0901 {
0902     struct igc_adapter *adapter = container_of(ptp, struct igc_adapter,
0903                            ptp_caps);
0904 
0905     return get_device_system_crosststamp(igc_phc_get_syncdevicetime,
0906                          adapter, &adapter->snapshot, cts);
0907 }
0908 
0909 /**
0910  * igc_ptp_init - Initialize PTP functionality
0911  * @adapter: Board private structure
0912  *
0913  * This function is called at device probe to initialize the PTP
0914  * functionality.
0915  */
0916 void igc_ptp_init(struct igc_adapter *adapter)
0917 {
0918     struct net_device *netdev = adapter->netdev;
0919     struct igc_hw *hw = &adapter->hw;
0920     int i;
0921 
0922     switch (hw->mac.type) {
0923     case igc_i225:
0924         for (i = 0; i < IGC_N_SDP; i++) {
0925             struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
0926 
0927             snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
0928             ppd->index = i;
0929             ppd->func = PTP_PF_NONE;
0930         }
0931         snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
0932         adapter->ptp_caps.owner = THIS_MODULE;
0933         adapter->ptp_caps.max_adj = 62499999;
0934         adapter->ptp_caps.adjfine = igc_ptp_adjfine_i225;
0935         adapter->ptp_caps.adjtime = igc_ptp_adjtime_i225;
0936         adapter->ptp_caps.gettimex64 = igc_ptp_gettimex64_i225;
0937         adapter->ptp_caps.settime64 = igc_ptp_settime_i225;
0938         adapter->ptp_caps.enable = igc_ptp_feature_enable_i225;
0939         adapter->ptp_caps.pps = 1;
0940         adapter->ptp_caps.pin_config = adapter->sdp_config;
0941         adapter->ptp_caps.n_ext_ts = IGC_N_EXTTS;
0942         adapter->ptp_caps.n_per_out = IGC_N_PEROUT;
0943         adapter->ptp_caps.n_pins = IGC_N_SDP;
0944         adapter->ptp_caps.verify = igc_ptp_verify_pin;
0945 
0946         if (!igc_is_crosststamp_supported(adapter))
0947             break;
0948 
0949         adapter->ptp_caps.getcrosststamp = igc_ptp_getcrosststamp;
0950         break;
0951     default:
0952         adapter->ptp_clock = NULL;
0953         return;
0954     }
0955 
0956     spin_lock_init(&adapter->tmreg_lock);
0957     INIT_WORK(&adapter->ptp_tx_work, igc_ptp_tx_work);
0958 
0959     adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
0960     adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
0961 
0962     adapter->prev_ptp_time = ktime_to_timespec64(ktime_get_real());
0963     adapter->ptp_reset_start = ktime_get();
0964 
0965     adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
0966                         &adapter->pdev->dev);
0967     if (IS_ERR(adapter->ptp_clock)) {
0968         adapter->ptp_clock = NULL;
0969         netdev_err(netdev, "ptp_clock_register failed\n");
0970     } else if (adapter->ptp_clock) {
0971         netdev_info(netdev, "PHC added\n");
0972         adapter->ptp_flags |= IGC_PTP_ENABLED;
0973     }
0974 }
0975 
0976 static void igc_ptp_time_save(struct igc_adapter *adapter)
0977 {
0978     igc_ptp_read(adapter, &adapter->prev_ptp_time);
0979     adapter->ptp_reset_start = ktime_get();
0980 }
0981 
0982 static void igc_ptp_time_restore(struct igc_adapter *adapter)
0983 {
0984     struct timespec64 ts = adapter->prev_ptp_time;
0985     ktime_t delta;
0986 
0987     delta = ktime_sub(ktime_get(), adapter->ptp_reset_start);
0988 
0989     timespec64_add_ns(&ts, ktime_to_ns(delta));
0990 
0991     igc_ptp_write_i225(adapter, &ts);
0992 }
0993 
0994 static void igc_ptm_stop(struct igc_adapter *adapter)
0995 {
0996     struct igc_hw *hw = &adapter->hw;
0997     u32 ctrl;
0998 
0999     ctrl = rd32(IGC_PTM_CTRL);
1000     ctrl &= ~IGC_PTM_CTRL_EN;
1001 
1002     wr32(IGC_PTM_CTRL, ctrl);
1003 }
1004 
1005 /**
1006  * igc_ptp_suspend - Disable PTP work items and prepare for suspend
1007  * @adapter: Board private structure
1008  *
1009  * This function stops the overflow check work and PTP Tx timestamp work, and
1010  * will prepare the device for OS suspend.
1011  */
1012 void igc_ptp_suspend(struct igc_adapter *adapter)
1013 {
1014     if (!(adapter->ptp_flags & IGC_PTP_ENABLED))
1015         return;
1016 
1017     cancel_work_sync(&adapter->ptp_tx_work);
1018     dev_kfree_skb_any(adapter->ptp_tx_skb);
1019     adapter->ptp_tx_skb = NULL;
1020     clear_bit_unlock(__IGC_PTP_TX_IN_PROGRESS, &adapter->state);
1021 
1022     if (pci_device_is_present(adapter->pdev)) {
1023         igc_ptp_time_save(adapter);
1024         igc_ptm_stop(adapter);
1025     }
1026 }
1027 
1028 /**
1029  * igc_ptp_stop - Disable PTP device and stop the overflow check.
1030  * @adapter: Board private structure.
1031  *
1032  * This function stops the PTP support and cancels the delayed work.
1033  **/
1034 void igc_ptp_stop(struct igc_adapter *adapter)
1035 {
1036     igc_ptp_suspend(adapter);
1037 
1038     if (adapter->ptp_clock) {
1039         ptp_clock_unregister(adapter->ptp_clock);
1040         netdev_info(adapter->netdev, "PHC removed\n");
1041         adapter->ptp_flags &= ~IGC_PTP_ENABLED;
1042     }
1043 }
1044 
1045 /**
1046  * igc_ptp_reset - Re-enable the adapter for PTP following a reset.
1047  * @adapter: Board private structure.
1048  *
1049  * This function handles the reset work required to re-enable the PTP device.
1050  **/
1051 void igc_ptp_reset(struct igc_adapter *adapter)
1052 {
1053     struct igc_hw *hw = &adapter->hw;
1054     u32 cycle_ctrl, ctrl;
1055     unsigned long flags;
1056     u32 timadj;
1057 
1058     /* reset the tstamp_config */
1059     igc_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1060 
1061     spin_lock_irqsave(&adapter->tmreg_lock, flags);
1062 
1063     switch (adapter->hw.mac.type) {
1064     case igc_i225:
1065         timadj = rd32(IGC_TIMADJ);
1066         timadj |= IGC_TIMADJ_ADJUST_METH;
1067         wr32(IGC_TIMADJ, timadj);
1068 
1069         wr32(IGC_TSAUXC, 0x0);
1070         wr32(IGC_TSSDP, 0x0);
1071         wr32(IGC_TSIM,
1072              IGC_TSICR_INTERRUPTS |
1073              (adapter->pps_sys_wrap_on ? IGC_TSICR_SYS_WRAP : 0));
1074         wr32(IGC_IMS, IGC_IMS_TS);
1075 
1076         if (!igc_is_crosststamp_supported(adapter))
1077             break;
1078 
1079         wr32(IGC_PCIE_DIG_DELAY, IGC_PCIE_DIG_DELAY_DEFAULT);
1080         wr32(IGC_PCIE_PHY_DELAY, IGC_PCIE_PHY_DELAY_DEFAULT);
1081 
1082         cycle_ctrl = IGC_PTM_CYCLE_CTRL_CYC_TIME(IGC_PTM_CYC_TIME_DEFAULT);
1083 
1084         wr32(IGC_PTM_CYCLE_CTRL, cycle_ctrl);
1085 
1086         ctrl = IGC_PTM_CTRL_EN |
1087             IGC_PTM_CTRL_START_NOW |
1088             IGC_PTM_CTRL_SHRT_CYC(IGC_PTM_SHORT_CYC_DEFAULT) |
1089             IGC_PTM_CTRL_PTM_TO(IGC_PTM_TIMEOUT_DEFAULT) |
1090             IGC_PTM_CTRL_TRIG;
1091 
1092         wr32(IGC_PTM_CTRL, ctrl);
1093 
1094         /* Force the first cycle to run. */
1095         wr32(IGC_PTM_STAT, IGC_PTM_STAT_VALID);
1096 
1097         break;
1098     default:
1099         /* No work to do. */
1100         goto out;
1101     }
1102 
1103     /* Re-initialize the timer. */
1104     if (hw->mac.type == igc_i225) {
1105         igc_ptp_time_restore(adapter);
1106     } else {
1107         timecounter_init(&adapter->tc, &adapter->cc,
1108                  ktime_to_ns(ktime_get_real()));
1109     }
1110 out:
1111     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1112 
1113     wrfl();
1114 }
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!