intel/igc/igc_mac.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c)  2018 Intel Corporation */
0003
0004 #include <linux/pci.h>
0005 #include <linux/delay.h>
0006
0007 #include "igc_mac.h"
0008 #include "igc_hw.h"
0009
0010 /**
0011  * igc_disable_pcie_master - Disables PCI-express master access
0012  * @hw: pointer to the HW structure
0013  *
0014  * Returns 0 (0) if successful, else returns -10
0015  * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
0016  * the master requests to be disabled.
0017  *
0018  * Disables PCI-Express master access and verifies there are no pending
0019  * requests.
0020  */
0021 s32 igc_disable_pcie_master(struct igc_hw *hw)
0022 {
0023     s32 timeout = MASTER_DISABLE_TIMEOUT;
0024     s32 ret_val = 0;
0025     u32 ctrl;
0026
0027     ctrl = rd32(IGC_CTRL);
0028     ctrl |= IGC_CTRL_GIO_MASTER_DISABLE;
0029     wr32(IGC_CTRL, ctrl);
0030
0031     while (timeout) {
0032         if (!(rd32(IGC_STATUS) &
0033             IGC_STATUS_GIO_MASTER_ENABLE))
0034             break;
0035         usleep_range(2000, 3000);
0036         timeout--;
0037     }
0038
0039     if (!timeout) {
0040         hw_dbg("Master requests are pending.\n");
0041         ret_val = -IGC_ERR_MASTER_REQUESTS_PENDING;
0042         goto out;
0043     }
0044
0045 out:
0046     return ret_val;
0047 }
0048
0049 /**
0050  * igc_init_rx_addrs - Initialize receive addresses
0051  * @hw: pointer to the HW structure
0052  * @rar_count: receive address registers
0053  *
0054  * Setup the receive address registers by setting the base receive address
0055  * register to the devices MAC address and clearing all the other receive
0056  * address registers to 0.
0057  */
0058 void igc_init_rx_addrs(struct igc_hw *hw, u16 rar_count)
0059 {
0060     u8 mac_addr[ETH_ALEN] = {0};
0061     u32 i;
0062
0063     /* Setup the receive address */
0064     hw_dbg("Programming MAC Address into RAR[0]\n");
0065
0066     hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
0067
0068     /* Zero out the other (rar_entry_count - 1) receive addresses */
0069     hw_dbg("Clearing RAR[1-%u]\n", rar_count - 1);
0070     for (i = 1; i < rar_count; i++)
0071         hw->mac.ops.rar_set(hw, mac_addr, i);
0072 }
0073
0074 /**
0075  * igc_set_fc_watermarks - Set flow control high/low watermarks
0076  * @hw: pointer to the HW structure
0077  *
0078  * Sets the flow control high/low threshold (watermark) registers.  If
0079  * flow control XON frame transmission is enabled, then set XON frame
0080  * transmission as well.
0081  */
0082 static s32 igc_set_fc_watermarks(struct igc_hw *hw)
0083 {
0084     u32 fcrtl = 0, fcrth = 0;
0085
0086     /* Set the flow control receive threshold registers.  Normally,
0087      * these registers will be set to a default threshold that may be
0088      * adjusted later by the driver's runtime code.  However, if the
0089      * ability to transmit pause frames is not enabled, then these
0090      * registers will be set to 0.
0091      */
0092     if (hw->fc.current_mode & igc_fc_tx_pause) {
0093         /* We need to set up the Receive Threshold high and low water
0094          * marks as well as (optionally) enabling the transmission of
0095          * XON frames.
0096          */
0097         fcrtl = hw->fc.low_water;
0098         if (hw->fc.send_xon)
0099             fcrtl |= IGC_FCRTL_XONE;
0100
0101         fcrth = hw->fc.high_water;
0102     }
0103     wr32(IGC_FCRTL, fcrtl);
0104     wr32(IGC_FCRTH, fcrth);
0105
0106     return 0;
0107 }
0108
0109 /**
0110  * igc_setup_link - Setup flow control and link settings
0111  * @hw: pointer to the HW structure
0112  *
0113  * Determines which flow control settings to use, then configures flow
0114  * control.  Calls the appropriate media-specific link configuration
0115  * function.  Assuming the adapter has a valid link partner, a valid link
0116  * should be established.  Assumes the hardware has previously been reset
0117  * and the transmitter and receiver are not enabled.
0118  */
0119 s32 igc_setup_link(struct igc_hw *hw)
0120 {
0121     s32 ret_val = 0;
0122
0123     /* In the case of the phy reset being blocked, we already have a link.
0124      * We do not need to set it up again.
0125      */
0126     if (igc_check_reset_block(hw))
0127         goto out;
0128
0129     /* If requested flow control is set to default, set flow control
0130      * to the both 'rx' and 'tx' pause frames.
0131      */
0132     if (hw->fc.requested_mode == igc_fc_default)
0133         hw->fc.requested_mode = igc_fc_full;
0134
0135     /* We want to save off the original Flow Control configuration just
0136      * in case we get disconnected and then reconnected into a different
0137      * hub or switch with different Flow Control capabilities.
0138      */
0139     hw->fc.current_mode = hw->fc.requested_mode;
0140
0141     hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
0142
0143     /* Call the necessary media_type subroutine to configure the link. */
0144     ret_val = hw->mac.ops.setup_physical_interface(hw);
0145     if (ret_val)
0146         goto out;
0147
0148     /* Initialize the flow control address, type, and PAUSE timer
0149      * registers to their default values.  This is done even if flow
0150      * control is disabled, because it does not hurt anything to
0151      * initialize these registers.
0152      */
0153     hw_dbg("Initializing the Flow Control address, type and timer regs\n");
0154     wr32(IGC_FCT, FLOW_CONTROL_TYPE);
0155     wr32(IGC_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
0156     wr32(IGC_FCAL, FLOW_CONTROL_ADDRESS_LOW);
0157
0158     wr32(IGC_FCTTV, hw->fc.pause_time);
0159
0160     ret_val = igc_set_fc_watermarks(hw);
0161
0162 out:
0163     return ret_val;
0164 }
0165
0166 /**
0167  * igc_force_mac_fc - Force the MAC's flow control settings
0168  * @hw: pointer to the HW structure
0169  *
0170  * Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
0171  * device control register to reflect the adapter settings.  TFCE and RFCE
0172  * need to be explicitly set by software when a copper PHY is used because
0173  * autonegotiation is managed by the PHY rather than the MAC.  Software must
0174  * also configure these bits when link is forced on a fiber connection.
0175  */
0176 s32 igc_force_mac_fc(struct igc_hw *hw)
0177 {
0178     s32 ret_val = 0;
0179     u32 ctrl;
0180
0181     ctrl = rd32(IGC_CTRL);
0182
0183     /* Because we didn't get link via the internal auto-negotiation
0184      * mechanism (we either forced link or we got link via PHY
0185      * auto-neg), we have to manually enable/disable transmit an
0186      * receive flow control.
0187      *
0188      * The "Case" statement below enables/disable flow control
0189      * according to the "hw->fc.current_mode" parameter.
0190      *
0191      * The possible values of the "fc" parameter are:
0192      *      0:  Flow control is completely disabled
0193      *      1:  Rx flow control is enabled (we can receive pause
0194      *          frames but not send pause frames).
0195      *      2:  Tx flow control is enabled (we can send pause frames
0196      *          but we do not receive pause frames).
0197      *      3:  Both Rx and TX flow control (symmetric) is enabled.
0198      *  other:  No other values should be possible at this point.
0199      */
0200     hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
0201
0202     switch (hw->fc.current_mode) {
0203     case igc_fc_none:
0204         ctrl &= (~(IGC_CTRL_TFCE | IGC_CTRL_RFCE));
0205         break;
0206     case igc_fc_rx_pause:
0207         ctrl &= (~IGC_CTRL_TFCE);
0208         ctrl |= IGC_CTRL_RFCE;
0209         break;
0210     case igc_fc_tx_pause:
0211         ctrl &= (~IGC_CTRL_RFCE);
0212         ctrl |= IGC_CTRL_TFCE;
0213         break;
0214     case igc_fc_full:
0215         ctrl |= (IGC_CTRL_TFCE | IGC_CTRL_RFCE);
0216         break;
0217     default:
0218         hw_dbg("Flow control param set incorrectly\n");
0219         ret_val = -IGC_ERR_CONFIG;
0220         goto out;
0221     }
0222
0223     wr32(IGC_CTRL, ctrl);
0224
0225 out:
0226     return ret_val;
0227 }
0228
0229 /**
0230  * igc_clear_hw_cntrs_base - Clear base hardware counters
0231  * @hw: pointer to the HW structure
0232  *
0233  * Clears the base hardware counters by reading the counter registers.
0234  */
0235 void igc_clear_hw_cntrs_base(struct igc_hw *hw)
0236 {
0237     rd32(IGC_CRCERRS);
0238     rd32(IGC_MPC);
0239     rd32(IGC_SCC);
0240     rd32(IGC_ECOL);
0241     rd32(IGC_MCC);
0242     rd32(IGC_LATECOL);
0243     rd32(IGC_COLC);
0244     rd32(IGC_RERC);
0245     rd32(IGC_DC);
0246     rd32(IGC_RLEC);
0247     rd32(IGC_XONRXC);
0248     rd32(IGC_XONTXC);
0249     rd32(IGC_XOFFRXC);
0250     rd32(IGC_XOFFTXC);
0251     rd32(IGC_FCRUC);
0252     rd32(IGC_GPRC);
0253     rd32(IGC_BPRC);
0254     rd32(IGC_MPRC);
0255     rd32(IGC_GPTC);
0256     rd32(IGC_GORCL);
0257     rd32(IGC_GORCH);
0258     rd32(IGC_GOTCL);
0259     rd32(IGC_GOTCH);
0260     rd32(IGC_RNBC);
0261     rd32(IGC_RUC);
0262     rd32(IGC_RFC);
0263     rd32(IGC_ROC);
0264     rd32(IGC_RJC);
0265     rd32(IGC_TORL);
0266     rd32(IGC_TORH);
0267     rd32(IGC_TOTL);
0268     rd32(IGC_TOTH);
0269     rd32(IGC_TPR);
0270     rd32(IGC_TPT);
0271     rd32(IGC_MPTC);
0272     rd32(IGC_BPTC);
0273
0274     rd32(IGC_PRC64);
0275     rd32(IGC_PRC127);
0276     rd32(IGC_PRC255);
0277     rd32(IGC_PRC511);
0278     rd32(IGC_PRC1023);
0279     rd32(IGC_PRC1522);
0280     rd32(IGC_PTC64);
0281     rd32(IGC_PTC127);
0282     rd32(IGC_PTC255);
0283     rd32(IGC_PTC511);
0284     rd32(IGC_PTC1023);
0285     rd32(IGC_PTC1522);
0286
0287     rd32(IGC_ALGNERRC);
0288     rd32(IGC_RXERRC);
0289     rd32(IGC_TNCRS);
0290     rd32(IGC_HTDPMC);
0291     rd32(IGC_TSCTC);
0292
0293     rd32(IGC_MGTPRC);
0294     rd32(IGC_MGTPDC);
0295     rd32(IGC_MGTPTC);
0296
0297     rd32(IGC_IAC);
0298
0299     rd32(IGC_RPTHC);
0300     rd32(IGC_TLPIC);
0301     rd32(IGC_RLPIC);
0302     rd32(IGC_HGPTC);
0303     rd32(IGC_RXDMTC);
0304     rd32(IGC_HGORCL);
0305     rd32(IGC_HGORCH);
0306     rd32(IGC_HGOTCL);
0307     rd32(IGC_HGOTCH);
0308     rd32(IGC_LENERRS);
0309 }
0310
0311 /**
0312  * igc_rar_set - Set receive address register
0313  * @hw: pointer to the HW structure
0314  * @addr: pointer to the receive address
0315  * @index: receive address array register
0316  *
0317  * Sets the receive address array register at index to the address passed
0318  * in by addr.
0319  */
0320 void igc_rar_set(struct igc_hw *hw, u8 *addr, u32 index)
0321 {
0322     u32 rar_low, rar_high;
0323
0324     /* HW expects these in little endian so we reverse the byte order
0325      * from network order (big endian) to little endian
0326      */
0327     rar_low = ((u32)addr[0] |
0328            ((u32)addr[1] << 8) |
0329            ((u32)addr[2] << 16) | ((u32)addr[3] << 24));
0330
0331     rar_high = ((u32)addr[4] | ((u32)addr[5] << 8));
0332
0333     /* If MAC address zero, no need to set the AV bit */
0334     if (rar_low || rar_high)
0335         rar_high |= IGC_RAH_AV;
0336
0337     /* Some bridges will combine consecutive 32-bit writes into
0338      * a single burst write, which will malfunction on some parts.
0339      * The flushes avoid this.
0340      */
0341     wr32(IGC_RAL(index), rar_low);
0342     wrfl();
0343     wr32(IGC_RAH(index), rar_high);
0344     wrfl();
0345 }
0346
0347 /**
0348  * igc_check_for_copper_link - Check for link (Copper)
0349  * @hw: pointer to the HW structure
0350  *
0351  * Checks to see of the link status of the hardware has changed.  If a
0352  * change in link status has been detected, then we read the PHY registers
0353  * to get the current speed/duplex if link exists.
0354  */
0355 s32 igc_check_for_copper_link(struct igc_hw *hw)
0356 {
0357     struct igc_mac_info *mac = &hw->mac;
0358     bool link = false;
0359     s32 ret_val;
0360
0361     /* We only want to go out to the PHY registers to see if Auto-Neg
0362      * has completed and/or if our link status has changed.  The
0363      * get_link_status flag is set upon receiving a Link Status
0364      * Change or Rx Sequence Error interrupt.
0365      */
0366     if (!mac->get_link_status) {
0367         ret_val = 0;
0368         goto out;
0369     }
0370
0371     /* First we want to see if the MII Status Register reports
0372      * link.  If so, then we want to get the current speed/duplex
0373      * of the PHY.
0374      */
0375     ret_val = igc_phy_has_link(hw, 1, 0, &link);
0376     if (ret_val)
0377         goto out;
0378
0379     if (!link)
0380         goto out; /* No link detected */
0381
0382     mac->get_link_status = false;
0383
0384     /* Check if there was DownShift, must be checked
0385      * immediately after link-up
0386      */
0387     igc_check_downshift(hw);
0388
0389     /* If we are forcing speed/duplex, then we simply return since
0390      * we have already determined whether we have link or not.
0391      */
0392     if (!mac->autoneg) {
0393         ret_val = -IGC_ERR_CONFIG;
0394         goto out;
0395     }
0396
0397     /* Auto-Neg is enabled.  Auto Speed Detection takes care
0398      * of MAC speed/duplex configuration.  So we only need to
0399      * configure Collision Distance in the MAC.
0400      */
0401     igc_config_collision_dist(hw);
0402
0403     /* Configure Flow Control now that Auto-Neg has completed.
0404      * First, we need to restore the desired flow control
0405      * settings because we may have had to re-autoneg with a
0406      * different link partner.
0407      */
0408     ret_val = igc_config_fc_after_link_up(hw);
0409     if (ret_val)
0410         hw_dbg("Error configuring flow control\n");
0411
0412 out:
0413     /* Now that we are aware of our link settings, we can set the LTR
0414      * thresholds.
0415      */
0416     ret_val = igc_set_ltr_i225(hw, link);
0417
0418     return ret_val;
0419 }
0420
0421 /**
0422  * igc_config_collision_dist - Configure collision distance
0423  * @hw: pointer to the HW structure
0424  *
0425  * Configures the collision distance to the default value and is used
0426  * during link setup. Currently no func pointer exists and all
0427  * implementations are handled in the generic version of this function.
0428  */
0429 void igc_config_collision_dist(struct igc_hw *hw)
0430 {
0431     u32 tctl;
0432
0433     tctl = rd32(IGC_TCTL);
0434
0435     tctl &= ~IGC_TCTL_COLD;
0436     tctl |= IGC_COLLISION_DISTANCE << IGC_COLD_SHIFT;
0437
0438     wr32(IGC_TCTL, tctl);
0439     wrfl();
0440 }
0441
0442 /**
0443  * igc_config_fc_after_link_up - Configures flow control after link
0444  * @hw: pointer to the HW structure
0445  *
0446  * Checks the status of auto-negotiation after link up to ensure that the
0447  * speed and duplex were not forced.  If the link needed to be forced, then
0448  * flow control needs to be forced also.  If auto-negotiation is enabled
0449  * and did not fail, then we configure flow control based on our link
0450  * partner.
0451  */
0452 s32 igc_config_fc_after_link_up(struct igc_hw *hw)
0453 {
0454     u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
0455     struct igc_mac_info *mac = &hw->mac;
0456     u16 speed, duplex;
0457     s32 ret_val = 0;
0458
0459     /* Check for the case where we have fiber media and auto-neg failed
0460      * so we had to force link.  In this case, we need to force the
0461      * configuration of the MAC to match the "fc" parameter.
0462      */
0463     if (mac->autoneg_failed)
0464         ret_val = igc_force_mac_fc(hw);
0465
0466     if (ret_val) {
0467         hw_dbg("Error forcing flow control settings\n");
0468         goto out;
0469     }
0470
0471     /* Check for the case where we have copper media and auto-neg is
0472      * enabled.  In this case, we need to check and see if Auto-Neg
0473      * has completed, and if so, how the PHY and link partner has
0474      * flow control configured.
0475      */
0476     if (mac->autoneg) {
0477         /* Read the MII Status Register and check to see if AutoNeg
0478          * has completed.  We read this twice because this reg has
0479          * some "sticky" (latched) bits.
0480          */
0481         ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
0482                            &mii_status_reg);
0483         if (ret_val)
0484             goto out;
0485         ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
0486                            &mii_status_reg);
0487         if (ret_val)
0488             goto out;
0489
0490         if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
0491             hw_dbg("Copper PHY and Auto Neg has not completed.\n");
0492             goto out;
0493         }
0494
0495         /* The AutoNeg process has completed, so we now need to
0496          * read both the Auto Negotiation Advertisement
0497          * Register (Address 4) and the Auto_Negotiation Base
0498          * Page Ability Register (Address 5) to determine how
0499          * flow control was negotiated.
0500          */
0501         ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
0502                            &mii_nway_adv_reg);
0503         if (ret_val)
0504             goto out;
0505         ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
0506                            &mii_nway_lp_ability_reg);
0507         if (ret_val)
0508             goto out;
0509         /* Two bits in the Auto Negotiation Advertisement Register
0510          * (Address 4) and two bits in the Auto Negotiation Base
0511          * Page Ability Register (Address 5) determine flow control
0512          * for both the PHY and the link partner.  The following
0513          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
0514          * 1999, describes these PAUSE resolution bits and how flow
0515          * control is determined based upon these settings.
0516          * NOTE:  DC = Don't Care
0517          *
0518          *   LOCAL DEVICE  |   LINK PARTNER
0519          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
0520          *-------|---------|-------|---------|--------------------
0521          *   0   |    0    |  DC   |   DC    | igc_fc_none
0522          *   0   |    1    |   0   |   DC    | igc_fc_none
0523          *   0   |    1    |   1   |    0    | igc_fc_none
0524          *   0   |    1    |   1   |    1    | igc_fc_tx_pause
0525          *   1   |    0    |   0   |   DC    | igc_fc_none
0526          *   1   |   DC    |   1   |   DC    | igc_fc_full
0527          *   1   |    1    |   0   |    0    | igc_fc_none
0528          *   1   |    1    |   0   |    1    | igc_fc_rx_pause
0529          *
0530          * Are both PAUSE bits set to 1?  If so, this implies
0531          * Symmetric Flow Control is enabled at both ends.  The
0532          * ASM_DIR bits are irrelevant per the spec.
0533          *
0534          * For Symmetric Flow Control:
0535          *
0536          *   LOCAL DEVICE  |   LINK PARTNER
0537          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
0538          *-------|---------|-------|---------|--------------------
0539          *   1   |   DC    |   1   |   DC    | IGC_fc_full
0540          *
0541          */
0542         if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
0543             (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
0544             /* Now we need to check if the user selected RX ONLY
0545              * of pause frames.  In this case, we had to advertise
0546              * FULL flow control because we could not advertise RX
0547              * ONLY. Hence, we must now check to see if we need to
0548              * turn OFF  the TRANSMISSION of PAUSE frames.
0549              */
0550             if (hw->fc.requested_mode == igc_fc_full) {
0551                 hw->fc.current_mode = igc_fc_full;
0552                 hw_dbg("Flow Control = FULL.\n");
0553             } else {
0554                 hw->fc.current_mode = igc_fc_rx_pause;
0555                 hw_dbg("Flow Control = RX PAUSE frames only.\n");
0556             }
0557         }
0558
0559         /* For receiving PAUSE frames ONLY.
0560          *
0561          *   LOCAL DEVICE  |   LINK PARTNER
0562          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
0563          *-------|---------|-------|---------|--------------------
0564          *   0   |    1    |   1   |    1    | igc_fc_tx_pause
0565          */
0566         else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
0567              (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
0568              (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
0569              (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
0570             hw->fc.current_mode = igc_fc_tx_pause;
0571             hw_dbg("Flow Control = TX PAUSE frames only.\n");
0572         }
0573         /* For transmitting PAUSE frames ONLY.
0574          *
0575          *   LOCAL DEVICE  |   LINK PARTNER
0576          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
0577          *-------|---------|-------|---------|--------------------
0578          *   1   |    1    |   0   |    1    | igc_fc_rx_pause
0579          */
0580         else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
0581              (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
0582              !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
0583              (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
0584             hw->fc.current_mode = igc_fc_rx_pause;
0585             hw_dbg("Flow Control = RX PAUSE frames only.\n");
0586         }
0587         /* Per the IEEE spec, at this point flow control should be
0588          * disabled.  However, we want to consider that we could
0589          * be connected to a legacy switch that doesn't advertise
0590          * desired flow control, but can be forced on the link
0591          * partner.  So if we advertised no flow control, that is
0592          * what we will resolve to.  If we advertised some kind of
0593          * receive capability (Rx Pause Only or Full Flow Control)
0594          * and the link partner advertised none, we will configure
0595          * ourselves to enable Rx Flow Control only.  We can do
0596          * this safely for two reasons:  If the link partner really
0597          * didn't want flow control enabled, and we enable Rx, no
0598          * harm done since we won't be receiving any PAUSE frames
0599          * anyway.  If the intent on the link partner was to have
0600          * flow control enabled, then by us enabling RX only, we
0601          * can at least receive pause frames and process them.
0602          * This is a good idea because in most cases, since we are
0603          * predominantly a server NIC, more times than not we will
0604          * be asked to delay transmission of packets than asking
0605          * our link partner to pause transmission of frames.
0606          */
0607         else if ((hw->fc.requested_mode == igc_fc_none) ||
0608              (hw->fc.requested_mode == igc_fc_tx_pause) ||
0609              (hw->fc.strict_ieee)) {
0610             hw->fc.current_mode = igc_fc_none;
0611             hw_dbg("Flow Control = NONE.\n");
0612         } else {
0613             hw->fc.current_mode = igc_fc_rx_pause;
0614             hw_dbg("Flow Control = RX PAUSE frames only.\n");
0615         }
0616
0617         /* Now we need to do one last check...  If we auto-
0618          * negotiated to HALF DUPLEX, flow control should not be
0619          * enabled per IEEE 802.3 spec.
0620          */
0621         ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
0622         if (ret_val) {
0623             hw_dbg("Error getting link speed and duplex\n");
0624             goto out;
0625         }
0626
0627         if (duplex == HALF_DUPLEX)
0628             hw->fc.current_mode = igc_fc_none;
0629
0630         /* Now we call a subroutine to actually force the MAC
0631          * controller to use the correct flow control settings.
0632          */
0633         ret_val = igc_force_mac_fc(hw);
0634         if (ret_val) {
0635             hw_dbg("Error forcing flow control settings\n");
0636             goto out;
0637         }
0638     }
0639
0640 out:
0641     return ret_val;
0642 }
0643
0644 /**
0645  * igc_get_auto_rd_done - Check for auto read completion
0646  * @hw: pointer to the HW structure
0647  *
0648  * Check EEPROM for Auto Read done bit.
0649  */
0650 s32 igc_get_auto_rd_done(struct igc_hw *hw)
0651 {
0652     s32 ret_val = 0;
0653     s32 i = 0;
0654
0655     while (i < AUTO_READ_DONE_TIMEOUT) {
0656         if (rd32(IGC_EECD) & IGC_EECD_AUTO_RD)
0657             break;
0658         usleep_range(1000, 2000);
0659         i++;
0660     }
0661
0662     if (i == AUTO_READ_DONE_TIMEOUT) {
0663         hw_dbg("Auto read by HW from NVM has not completed.\n");
0664         ret_val = -IGC_ERR_RESET;
0665         goto out;
0666     }
0667
0668 out:
0669     return ret_val;
0670 }
0671
0672 /**
0673  * igc_get_speed_and_duplex_copper - Retrieve current speed/duplex
0674  * @hw: pointer to the HW structure
0675  * @speed: stores the current speed
0676  * @duplex: stores the current duplex
0677  *
0678  * Read the status register for the current speed/duplex and store the current
0679  * speed and duplex for copper connections.
0680  */
0681 s32 igc_get_speed_and_duplex_copper(struct igc_hw *hw, u16 *speed,
0682                     u16 *duplex)
0683 {
0684     u32 status;
0685
0686     status = rd32(IGC_STATUS);
0687     if (status & IGC_STATUS_SPEED_1000) {
0688         /* For I225, STATUS will indicate 1G speed in both 1 Gbps
0689          * and 2.5 Gbps link modes. An additional bit is used
0690          * to differentiate between 1 Gbps and 2.5 Gbps.
0691          */
0692         if (hw->mac.type == igc_i225 &&
0693             (status & IGC_STATUS_SPEED_2500)) {
0694             *speed = SPEED_2500;
0695             hw_dbg("2500 Mbs, ");
0696         } else {
0697             *speed = SPEED_1000;
0698             hw_dbg("1000 Mbs, ");
0699         }
0700     } else if (status & IGC_STATUS_SPEED_100) {
0701         *speed = SPEED_100;
0702         hw_dbg("100 Mbs, ");
0703     } else {
0704         *speed = SPEED_10;
0705         hw_dbg("10 Mbs, ");
0706     }
0707
0708     if (status & IGC_STATUS_FD) {
0709         *duplex = FULL_DUPLEX;
0710         hw_dbg("Full Duplex\n");
0711     } else {
0712         *duplex = HALF_DUPLEX;
0713         hw_dbg("Half Duplex\n");
0714     }
0715
0716     return 0;
0717 }
0718
0719 /**
0720  * igc_put_hw_semaphore - Release hardware semaphore
0721  * @hw: pointer to the HW structure
0722  *
0723  * Release hardware semaphore used to access the PHY or NVM
0724  */
0725 void igc_put_hw_semaphore(struct igc_hw *hw)
0726 {
0727     u32 swsm;
0728
0729     swsm = rd32(IGC_SWSM);
0730
0731     swsm &= ~(IGC_SWSM_SMBI | IGC_SWSM_SWESMBI);
0732
0733     wr32(IGC_SWSM, swsm);
0734 }
0735
0736 /**
0737  * igc_enable_mng_pass_thru - Enable processing of ARP's
0738  * @hw: pointer to the HW structure
0739  *
0740  * Verifies the hardware needs to leave interface enabled so that frames can
0741  * be directed to and from the management interface.
0742  */
0743 bool igc_enable_mng_pass_thru(struct igc_hw *hw)
0744 {
0745     bool ret_val = false;
0746     u32 fwsm, factps;
0747     u32 manc;
0748
0749     if (!hw->mac.asf_firmware_present)
0750         goto out;
0751
0752     manc = rd32(IGC_MANC);
0753
0754     if (!(manc & IGC_MANC_RCV_TCO_EN))
0755         goto out;
0756
0757     if (hw->mac.arc_subsystem_valid) {
0758         fwsm = rd32(IGC_FWSM);
0759         factps = rd32(IGC_FACTPS);
0760
0761         if (!(factps & IGC_FACTPS_MNGCG) &&
0762             ((fwsm & IGC_FWSM_MODE_MASK) ==
0763             (igc_mng_mode_pt << IGC_FWSM_MODE_SHIFT))) {
0764             ret_val = true;
0765             goto out;
0766         }
0767     } else {
0768         if ((manc & IGC_MANC_SMBUS_EN) &&
0769             !(manc & IGC_MANC_ASF_EN)) {
0770             ret_val = true;
0771             goto out;
0772         }
0773     }
0774
0775 out:
0776     return ret_val;
0777 }
0778
0779 /**
0780  *  igc_hash_mc_addr - Generate a multicast hash value
0781  *  @hw: pointer to the HW structure
0782  *  @mc_addr: pointer to a multicast address
0783  *
0784  *  Generates a multicast address hash value which is used to determine
0785  *  the multicast filter table array address and new table value.  See
0786  *  igc_mta_set()
0787  **/
0788 static u32 igc_hash_mc_addr(struct igc_hw *hw, u8 *mc_addr)
0789 {
0790     u32 hash_value, hash_mask;
0791     u8 bit_shift = 0;
0792
0793     /* Register count multiplied by bits per register */
0794     hash_mask = (hw->mac.mta_reg_count * 32) - 1;
0795
0796     /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
0797      * where 0xFF would still fall within the hash mask.
0798      */
0799     while (hash_mask >> bit_shift != 0xFF)
0800         bit_shift++;
0801
0802     /* The portion of the address that is used for the hash table
0803      * is determined by the mc_filter_type setting.
0804      * The algorithm is such that there is a total of 8 bits of shifting.
0805      * The bit_shift for a mc_filter_type of 0 represents the number of
0806      * left-shifts where the MSB of mc_addr[5] would still fall within
0807      * the hash_mask.  Case 0 does this exactly.  Since there are a total
0808      * of 8 bits of shifting, then mc_addr[4] will shift right the
0809      * remaining number of bits. Thus 8 - bit_shift.  The rest of the
0810      * cases are a variation of this algorithm...essentially raising the
0811      * number of bits to shift mc_addr[5] left, while still keeping the
0812      * 8-bit shifting total.
0813      *
0814      * For example, given the following Destination MAC Address and an
0815      * MTA register count of 128 (thus a 4096-bit vector and 0xFFF mask),
0816      * we can see that the bit_shift for case 0 is 4.  These are the hash
0817      * values resulting from each mc_filter_type...
0818      * [0] [1] [2] [3] [4] [5]
0819      * 01  AA  00  12  34  56
0820      * LSB                 MSB
0821      *
0822      * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
0823      * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
0824      * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
0825      * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
0826      */
0827     switch (hw->mac.mc_filter_type) {
0828     default:
0829     case 0:
0830         break;
0831     case 1:
0832         bit_shift += 1;
0833         break;
0834     case 2:
0835         bit_shift += 2;
0836         break;
0837     case 3:
0838         bit_shift += 4;
0839         break;
0840     }
0841
0842     hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
0843                   (((u16)mc_addr[5]) << bit_shift)));
0844
0845     return hash_value;
0846 }
0847
0848 /**
0849  *  igc_update_mc_addr_list - Update Multicast addresses
0850  *  @hw: pointer to the HW structure
0851  *  @mc_addr_list: array of multicast addresses to program
0852  *  @mc_addr_count: number of multicast addresses to program
0853  *
0854  *  Updates entire Multicast Table Array.
0855  *  The caller must have a packed mc_addr_list of multicast addresses.
0856  **/
0857 void igc_update_mc_addr_list(struct igc_hw *hw,
0858                  u8 *mc_addr_list, u32 mc_addr_count)
0859 {
0860     u32 hash_value, hash_bit, hash_reg;
0861     int i;
0862
0863     /* clear mta_shadow */
0864     memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
0865
0866     /* update mta_shadow from mc_addr_list */
0867     for (i = 0; (u32)i < mc_addr_count; i++) {
0868         hash_value = igc_hash_mc_addr(hw, mc_addr_list);
0869
0870         hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
0871         hash_bit = hash_value & 0x1F;
0872
0873         hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
0874         mc_addr_list += ETH_ALEN;
0875     }
0876
0877     /* replace the entire MTA table */
0878     for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
0879         array_wr32(IGC_MTA, i, hw->mac.mta_shadow[i]);
0880     wrfl();
0881 }