intel/igc/igc_dump.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c)  2018 Intel Corporation */
0003
0004 #include "igc.h"
0005
0006 struct igc_reg_info {
0007     u32 ofs;
0008     char *name;
0009 };
0010
0011 static const struct igc_reg_info igc_reg_info_tbl[] = {
0012     /* General Registers */
0013     {IGC_CTRL, "CTRL"},
0014     {IGC_STATUS, "STATUS"},
0015     {IGC_CTRL_EXT, "CTRL_EXT"},
0016     {IGC_MDIC, "MDIC"},
0017
0018     /* Interrupt Registers */
0019     {IGC_ICR, "ICR"},
0020
0021     /* RX Registers */
0022     {IGC_RCTL, "RCTL"},
0023     {IGC_RDLEN(0), "RDLEN"},
0024     {IGC_RDH(0), "RDH"},
0025     {IGC_RDT(0), "RDT"},
0026     {IGC_RXDCTL(0), "RXDCTL"},
0027     {IGC_RDBAL(0), "RDBAL"},
0028     {IGC_RDBAH(0), "RDBAH"},
0029
0030     /* TX Registers */
0031     {IGC_TCTL, "TCTL"},
0032     {IGC_TDBAL(0), "TDBAL"},
0033     {IGC_TDBAH(0), "TDBAH"},
0034     {IGC_TDLEN(0), "TDLEN"},
0035     {IGC_TDH(0), "TDH"},
0036     {IGC_TDT(0), "TDT"},
0037     {IGC_TXDCTL(0), "TXDCTL"},
0038
0039     /* List Terminator */
0040     {}
0041 };
0042
0043 /* igc_regdump - register printout routine */
0044 static void igc_regdump(struct igc_hw *hw, struct igc_reg_info *reginfo)
0045 {
0046     struct net_device *dev = igc_get_hw_dev(hw);
0047     int n = 0;
0048     char rname[16];
0049     u32 regs[8];
0050
0051     switch (reginfo->ofs) {
0052     case IGC_RDLEN(0):
0053         for (n = 0; n < 4; n++)
0054             regs[n] = rd32(IGC_RDLEN(n));
0055         break;
0056     case IGC_RDH(0):
0057         for (n = 0; n < 4; n++)
0058             regs[n] = rd32(IGC_RDH(n));
0059         break;
0060     case IGC_RDT(0):
0061         for (n = 0; n < 4; n++)
0062             regs[n] = rd32(IGC_RDT(n));
0063         break;
0064     case IGC_RXDCTL(0):
0065         for (n = 0; n < 4; n++)
0066             regs[n] = rd32(IGC_RXDCTL(n));
0067         break;
0068     case IGC_RDBAL(0):
0069         for (n = 0; n < 4; n++)
0070             regs[n] = rd32(IGC_RDBAL(n));
0071         break;
0072     case IGC_RDBAH(0):
0073         for (n = 0; n < 4; n++)
0074             regs[n] = rd32(IGC_RDBAH(n));
0075         break;
0076     case IGC_TDBAL(0):
0077         for (n = 0; n < 4; n++)
0078             regs[n] = rd32(IGC_TDBAL(n));
0079         break;
0080     case IGC_TDBAH(0):
0081         for (n = 0; n < 4; n++)
0082             regs[n] = rd32(IGC_TDBAH(n));
0083         break;
0084     case IGC_TDLEN(0):
0085         for (n = 0; n < 4; n++)
0086             regs[n] = rd32(IGC_TDLEN(n));
0087         break;
0088     case IGC_TDH(0):
0089         for (n = 0; n < 4; n++)
0090             regs[n] = rd32(IGC_TDH(n));
0091         break;
0092     case IGC_TDT(0):
0093         for (n = 0; n < 4; n++)
0094             regs[n] = rd32(IGC_TDT(n));
0095         break;
0096     case IGC_TXDCTL(0):
0097         for (n = 0; n < 4; n++)
0098             regs[n] = rd32(IGC_TXDCTL(n));
0099         break;
0100     default:
0101         netdev_info(dev, "%-15s %08x\n", reginfo->name,
0102                 rd32(reginfo->ofs));
0103         return;
0104     }
0105
0106     snprintf(rname, 16, "%s%s", reginfo->name, "[0-3]");
0107     netdev_info(dev, "%-15s %08x %08x %08x %08x\n", rname, regs[0], regs[1],
0108             regs[2], regs[3]);
0109 }
0110
0111 /* igc_rings_dump - Tx-rings and Rx-rings */
0112 void igc_rings_dump(struct igc_adapter *adapter)
0113 {
0114     struct net_device *netdev = adapter->netdev;
0115     struct my_u0 { __le64 a; __le64 b; } *u0;
0116     union igc_adv_tx_desc *tx_desc;
0117     union igc_adv_rx_desc *rx_desc;
0118     struct igc_ring *tx_ring;
0119     struct igc_ring *rx_ring;
0120     u32 staterr;
0121     u16 i, n;
0122
0123     if (!netif_msg_hw(adapter))
0124         return;
0125
0126     netdev_info(netdev, "Device info: state %016lX trans_start %016lX\n",
0127             netdev->state, dev_trans_start(netdev));
0128
0129     /* Print TX Ring Summary */
0130     if (!netif_running(netdev))
0131         goto exit;
0132
0133     netdev_info(netdev, "TX Rings Summary\n");
0134     netdev_info(netdev, "Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
0135     for (n = 0; n < adapter->num_tx_queues; n++) {
0136         struct igc_tx_buffer *buffer_info;
0137
0138         tx_ring = adapter->tx_ring[n];
0139         buffer_info = &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
0140
0141         netdev_info(netdev, "%5d %5X %5X %016llX %04X %p %016llX\n",
0142                 n, tx_ring->next_to_use, tx_ring->next_to_clean,
0143                 (u64)dma_unmap_addr(buffer_info, dma),
0144                 dma_unmap_len(buffer_info, len),
0145                 buffer_info->next_to_watch,
0146                 (u64)buffer_info->time_stamp);
0147     }
0148
0149     /* Print TX Rings */
0150     if (!netif_msg_tx_done(adapter))
0151         goto rx_ring_summary;
0152
0153     netdev_info(netdev, "TX Rings Dump\n");
0154
0155     /* Transmit Descriptor Formats
0156      *
0157      * Advanced Transmit Descriptor
0158      *   +--------------------------------------------------------------+
0159      * 0 |         Buffer Address [63:0]                                |
0160      *   +--------------------------------------------------------------+
0161      * 8 | PAYLEN  | PORTS  |CC|IDX | STA | DCMD  |DTYP|MAC|RSV| DTALEN |
0162      *   +--------------------------------------------------------------+
0163      *   63      46 45    40 39 38 36 35 32 31   24             15       0
0164      */
0165
0166     for (n = 0; n < adapter->num_tx_queues; n++) {
0167         tx_ring = adapter->tx_ring[n];
0168         netdev_info(netdev, "------------------------------------\n");
0169         netdev_info(netdev, "TX QUEUE INDEX = %d\n",
0170                 tx_ring->queue_index);
0171         netdev_info(netdev, "------------------------------------\n");
0172         netdev_info(netdev, "T [desc]     [address 63:0  ] [PlPOCIStDDM Ln] [bi->dma       ] leng  ntw timestamp        bi->skb\n");
0173
0174         for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
0175             const char *next_desc;
0176             struct igc_tx_buffer *buffer_info;
0177
0178             tx_desc = IGC_TX_DESC(tx_ring, i);
0179             buffer_info = &tx_ring->tx_buffer_info[i];
0180             u0 = (struct my_u0 *)tx_desc;
0181             if (i == tx_ring->next_to_use &&
0182                 i == tx_ring->next_to_clean)
0183                 next_desc = " NTC/U";
0184             else if (i == tx_ring->next_to_use)
0185                 next_desc = " NTU";
0186             else if (i == tx_ring->next_to_clean)
0187                 next_desc = " NTC";
0188             else
0189                 next_desc = "";
0190
0191             netdev_info(netdev, "T [0x%03X]    %016llX %016llX %016llX %04X  %p %016llX %p%s\n",
0192                     i, le64_to_cpu(u0->a),
0193                     le64_to_cpu(u0->b),
0194                     (u64)dma_unmap_addr(buffer_info, dma),
0195                     dma_unmap_len(buffer_info, len),
0196                     buffer_info->next_to_watch,
0197                     (u64)buffer_info->time_stamp,
0198                     buffer_info->skb, next_desc);
0199
0200             if (netif_msg_pktdata(adapter) && buffer_info->skb)
0201                 print_hex_dump(KERN_INFO, "",
0202                            DUMP_PREFIX_ADDRESS,
0203                            16, 1, buffer_info->skb->data,
0204                            dma_unmap_len(buffer_info, len),
0205                            true);
0206         }
0207     }
0208
0209     /* Print RX Rings Summary */
0210 rx_ring_summary:
0211     netdev_info(netdev, "RX Rings Summary\n");
0212     netdev_info(netdev, "Queue [NTU] [NTC]\n");
0213     for (n = 0; n < adapter->num_rx_queues; n++) {
0214         rx_ring = adapter->rx_ring[n];
0215         netdev_info(netdev, "%5d %5X %5X\n", n, rx_ring->next_to_use,
0216                 rx_ring->next_to_clean);
0217     }
0218
0219     /* Print RX Rings */
0220     if (!netif_msg_rx_status(adapter))
0221         goto exit;
0222
0223     netdev_info(netdev, "RX Rings Dump\n");
0224
0225     /* Advanced Receive Descriptor (Read) Format
0226      *    63                                           1        0
0227      *    +-----------------------------------------------------+
0228      *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
0229      *    +----------------------------------------------+------+
0230      *  8 |       Header Buffer Address [63:1]           |  DD  |
0231      *    +-----------------------------------------------------+
0232      *
0233      *
0234      * Advanced Receive Descriptor (Write-Back) Format
0235      *
0236      *   63       48 47    32 31  30      21 20 17 16   4 3     0
0237      *   +------------------------------------------------------+
0238      * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
0239      *   | Checksum   Ident  |   |           |    | Type | Type |
0240      *   +------------------------------------------------------+
0241      * 8 | VLAN Tag | Length | Extended Error | Extended Status |
0242      *   +------------------------------------------------------+
0243      *   63       48 47    32 31            20 19               0
0244      */
0245
0246     for (n = 0; n < adapter->num_rx_queues; n++) {
0247         rx_ring = adapter->rx_ring[n];
0248         netdev_info(netdev, "------------------------------------\n");
0249         netdev_info(netdev, "RX QUEUE INDEX = %d\n",
0250                 rx_ring->queue_index);
0251         netdev_info(netdev, "------------------------------------\n");
0252         netdev_info(netdev, "R  [desc]      [ PktBuf     A0] [  HeadBuf   DD] [bi->dma       ] [bi->skb] <-- Adv Rx Read format\n");
0253         netdev_info(netdev, "RWB[desc]      [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
0254
0255         for (i = 0; i < rx_ring->count; i++) {
0256             const char *next_desc;
0257             struct igc_rx_buffer *buffer_info;
0258
0259             buffer_info = &rx_ring->rx_buffer_info[i];
0260             rx_desc = IGC_RX_DESC(rx_ring, i);
0261             u0 = (struct my_u0 *)rx_desc;
0262             staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
0263
0264             if (i == rx_ring->next_to_use)
0265                 next_desc = " NTU";
0266             else if (i == rx_ring->next_to_clean)
0267                 next_desc = " NTC";
0268             else
0269                 next_desc = "";
0270
0271             if (staterr & IGC_RXD_STAT_DD) {
0272                 /* Descriptor Done */
0273                 netdev_info(netdev, "%s[0x%03X]     %016llX %016llX ---------------- %s\n",
0274                         "RWB", i,
0275                         le64_to_cpu(u0->a),
0276                         le64_to_cpu(u0->b),
0277                         next_desc);
0278             } else {
0279                 netdev_info(netdev, "%s[0x%03X]     %016llX %016llX %016llX %s\n",
0280                         "R  ", i,
0281                         le64_to_cpu(u0->a),
0282                         le64_to_cpu(u0->b),
0283                         (u64)buffer_info->dma,
0284                         next_desc);
0285
0286                 if (netif_msg_pktdata(adapter) &&
0287                     buffer_info->dma && buffer_info->page) {
0288                     print_hex_dump(KERN_INFO, "",
0289                                DUMP_PREFIX_ADDRESS,
0290                                16, 1,
0291                                page_address
0292                                (buffer_info->page) +
0293                                buffer_info->page_offset,
0294                                igc_rx_bufsz(rx_ring),
0295                                true);
0296                 }
0297             }
0298         }
0299     }
0300
0301 exit:
0302     return;
0303 }
0304
0305 /* igc_regs_dump - registers dump */
0306 void igc_regs_dump(struct igc_adapter *adapter)
0307 {
0308     struct igc_hw *hw = &adapter->hw;
0309     struct igc_reg_info *reginfo;
0310
0311     /* Print Registers */
0312     netdev_info(adapter->netdev, "Register Dump\n");
0313     netdev_info(adapter->netdev, "Register Name   Value\n");
0314     for (reginfo = (struct igc_reg_info *)igc_reg_info_tbl;
0315          reginfo->name; reginfo++) {
0316         igc_regdump(hw, reginfo);
0317     }
0318 }