intel/igc/igc_diag.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c)  2020 Intel Corporation */
0003
0004 bool igc_reg_test(struct igc_adapter *adapter, u64 *data);
0005 bool igc_eeprom_test(struct igc_adapter *adapter, u64 *data);
0006 bool igc_link_test(struct igc_adapter *adapter, u64 *data);
0007
0008 struct igc_reg_test {
0009     u16 reg;
0010     u8 array_len;
0011     u8 test_type;
0012     u32 mask;
0013     u32 write;
0014 };
0015
0016 /* In the hardware, registers are laid out either singly, in arrays
0017  * spaced 0x40 bytes apart, or in contiguous tables.  We assume
0018  * most tests take place on arrays or single registers (handled
0019  * as a single-element array) and special-case the tables.
0020  * Table tests are always pattern tests.
0021  *
0022  * We also make provision for some required setup steps by specifying
0023  * registers to be written without any read-back testing.
0024  */
0025
0026 #define PATTERN_TEST    1
0027 #define SET_READ_TEST   2
0028 #define TABLE32_TEST    3
0029 #define TABLE64_TEST_LO 4
0030 #define TABLE64_TEST_HI 5