intel/igc/igc_base.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c)  2018 Intel Corporation */
0003
0004 #ifndef _IGC_BASE_H_
0005 #define _IGC_BASE_H_
0006
0007 /* forward declaration */
0008 void igc_rx_fifo_flush_base(struct igc_hw *hw);
0009 void igc_power_down_phy_copper_base(struct igc_hw *hw);
0010
0011 /* Transmit Descriptor - Advanced */
0012 union igc_adv_tx_desc {
0013     struct {
0014         __le64 buffer_addr;    /* Address of descriptor's data buf */
0015         __le32 cmd_type_len;
0016         __le32 olinfo_status;
0017     } read;
0018     struct {
0019         __le64 rsvd;       /* Reserved */
0020         __le32 nxtseq_seed;
0021         __le32 status;
0022     } wb;
0023 };
0024
0025 /* Context descriptors */
0026 struct igc_adv_tx_context_desc {
0027     __le32 vlan_macip_lens;
0028     __le32 launch_time;
0029     __le32 type_tucmd_mlhl;
0030     __le32 mss_l4len_idx;
0031 };
0032
0033 /* Adv Transmit Descriptor Config Masks */
0034 #define IGC_ADVTXD_MAC_TSTAMP   0x00080000 /* IEEE1588 Timestamp packet */
0035 #define IGC_ADVTXD_DTYP_CTXT    0x00200000 /* Advanced Context Descriptor */
0036 #define IGC_ADVTXD_DTYP_DATA    0x00300000 /* Advanced Data Descriptor */
0037 #define IGC_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
0038 #define IGC_ADVTXD_DCMD_IFCS    0x02000000 /* Insert FCS (Ethernet CRC) */
0039 #define IGC_ADVTXD_DCMD_RS  0x08000000 /* Report Status */
0040 #define IGC_ADVTXD_DCMD_DEXT    0x20000000 /* Descriptor extension (1=Adv) */
0041 #define IGC_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
0042 #define IGC_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
0043 #define IGC_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
0044
0045 #define IGC_RAR_ENTRIES     16
0046
0047 /* Receive Descriptor - Advanced */
0048 union igc_adv_rx_desc {
0049     struct {
0050         __le64 pkt_addr; /* Packet buffer address */
0051         __le64 hdr_addr; /* Header buffer address */
0052     } read;
0053     struct {
0054         struct {
0055             union {
0056                 __le32 data;
0057                 struct {
0058                     __le16 pkt_info; /*RSS type, Pkt type*/
0059                     /* Split Header, header buffer len */
0060                     __le16 hdr_info;
0061                 } hs_rss;
0062             } lo_dword;
0063             union {
0064                 __le32 rss; /* RSS Hash */
0065                 struct {
0066                     __le16 ip_id; /* IP id */
0067                     __le16 csum; /* Packet Checksum */
0068                 } csum_ip;
0069             } hi_dword;
0070         } lower;
0071         struct {
0072             __le32 status_error; /* ext status/error */
0073             __le16 length; /* Packet length */
0074             __le16 vlan; /* VLAN tag */
0075         } upper;
0076     } wb;  /* writeback */
0077 };
0078
0079 /* Additional Transmit Descriptor Control definitions */
0080 #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */
0081 #define IGC_TXDCTL_SWFLUSH  0x04000000 /* Transmit Software Flush */
0082
0083 /* Additional Receive Descriptor Control definitions */
0084 #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */
0085 #define IGC_RXDCTL_SWFLUSH      0x04000000 /* Receive Software Flush */
0086
0087 /* SRRCTL bit definitions */
0088 #define IGC_SRRCTL_BSIZEPKT_SHIFT       10 /* Shift _right_ */
0089 #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT       2  /* Shift _left_ */
0090 #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF  0x02000000
0091
0092 #endif /* _IGC_BASE_H */