intel/igbvf/vf.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2009 - 2018 Intel Corporation. */
0003
0004 #ifndef _E1000_VF_H_
0005 #define _E1000_VF_H_
0006
0007 #include <linux/pci.h>
0008 #include <linux/delay.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/if_ether.h>
0011
0012 #include "regs.h"
0013 #include "defines.h"
0014
0015 struct e1000_hw;
0016
0017 #define E1000_DEV_ID_82576_VF       0x10CA
0018 #define E1000_DEV_ID_I350_VF        0x1520
0019 #define E1000_REVISION_0    0
0020 #define E1000_REVISION_1    1
0021 #define E1000_REVISION_2    2
0022 #define E1000_REVISION_3    3
0023 #define E1000_REVISION_4    4
0024
0025 #define E1000_FUNC_0    0
0026 #define E1000_FUNC_1    1
0027
0028 /* Receive Address Register Count
0029  * Number of high/low register pairs in the RAR.  The RAR (Receive Address
0030  * Registers) holds the directed and multicast addresses that we monitor.
0031  * These entries are also used for MAC-based filtering.
0032  */
0033 #define E1000_RAR_ENTRIES_VF    1
0034
0035 /* Receive Descriptor - Advanced */
0036 union e1000_adv_rx_desc {
0037     struct {
0038         __le64 pkt_addr; /* Packet buffer address */
0039         __le64 hdr_addr; /* Header buffer address */
0040     } read;
0041     struct {
0042         struct {
0043             union {
0044                 __le32 data;
0045                 struct {
0046                     __le16 pkt_info; /* RSS/Packet type */
0047                     /* Split Header, hdr buffer length */
0048                     __le16 hdr_info;
0049                 } hs_rss;
0050             } lo_dword;
0051             union {
0052                 __le32 rss; /* RSS Hash */
0053                 struct {
0054                     __le16 ip_id; /* IP id */
0055                     __le16 csum;  /* Packet Checksum */
0056                 } csum_ip;
0057             } hi_dword;
0058         } lower;
0059         struct {
0060             __le32 status_error; /* ext status/error */
0061             __le16 length; /* Packet length */
0062             __le16 vlan; /* VLAN tag */
0063         } upper;
0064     } wb;  /* writeback */
0065 };
0066
0067 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
0068 #define E1000_RXDADV_HDRBUFLEN_SHIFT    5
0069
0070 /* Transmit Descriptor - Advanced */
0071 union e1000_adv_tx_desc {
0072     struct {
0073         __le64 buffer_addr; /* Address of descriptor's data buf */
0074         __le32 cmd_type_len;
0075         __le32 olinfo_status;
0076     } read;
0077     struct {
0078         __le64 rsvd; /* Reserved */
0079         __le32 nxtseq_seed;
0080         __le32 status;
0081     } wb;
0082 };
0083
0084 /* Adv Transmit Descriptor Config Masks */
0085 #define E1000_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Descriptor */
0086 #define E1000_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
0087 #define E1000_ADVTXD_DCMD_EOP   0x01000000 /* End of Packet */
0088 #define E1000_ADVTXD_DCMD_IFCS  0x02000000 /* Insert FCS (Ethernet CRC) */
0089 #define E1000_ADVTXD_DCMD_RS    0x08000000 /* Report Status */
0090 #define E1000_ADVTXD_DCMD_DEXT  0x20000000 /* Descriptor extension (1=Adv) */
0091 #define E1000_ADVTXD_DCMD_VLE   0x40000000 /* VLAN pkt enable */
0092 #define E1000_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
0093 #define E1000_ADVTXD_PAYLEN_SHIFT   14 /* Adv desc PAYLEN shift */
0094
0095 /* Context descriptors */
0096 struct e1000_adv_tx_context_desc {
0097     __le32 vlan_macip_lens;
0098     __le32 seqnum_seed;
0099     __le32 type_tucmd_mlhl;
0100     __le32 mss_l4len_idx;
0101 };
0102
0103 #define E1000_ADVTXD_MACLEN_SHIFT   9  /* Adv ctxt desc mac len shift */
0104 #define E1000_ADVTXD_TUCMD_IPV4     0x00000400 /* IP Packet Type: 1=IPv4 */
0105 #define E1000_ADVTXD_TUCMD_L4T_TCP  0x00000800 /* L4 Packet TYPE of TCP */
0106 #define E1000_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 packet TYPE of SCTP */
0107 #define E1000_ADVTXD_L4LEN_SHIFT    8  /* Adv ctxt L4LEN shift */
0108 #define E1000_ADVTXD_MSS_SHIFT      16 /* Adv ctxt MSS shift */
0109
0110 enum e1000_mac_type {
0111     e1000_undefined = 0,
0112     e1000_vfadapt,
0113     e1000_vfadapt_i350,
0114     e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
0115 };
0116
0117 struct e1000_vf_stats {
0118     u64 base_gprc;
0119     u64 base_gptc;
0120     u64 base_gorc;
0121     u64 base_gotc;
0122     u64 base_mprc;
0123     u64 base_gotlbc;
0124     u64 base_gptlbc;
0125     u64 base_gorlbc;
0126     u64 base_gprlbc;
0127
0128     u32 last_gprc;
0129     u32 last_gptc;
0130     u32 last_gorc;
0131     u32 last_gotc;
0132     u32 last_mprc;
0133     u32 last_gotlbc;
0134     u32 last_gptlbc;
0135     u32 last_gorlbc;
0136     u32 last_gprlbc;
0137
0138     u64 gprc;
0139     u64 gptc;
0140     u64 gorc;
0141     u64 gotc;
0142     u64 mprc;
0143     u64 gotlbc;
0144     u64 gptlbc;
0145     u64 gorlbc;
0146     u64 gprlbc;
0147 };
0148
0149 #include "mbx.h"
0150
0151 struct e1000_mac_operations {
0152     /* Function pointers for the MAC. */
0153     s32  (*init_params)(struct e1000_hw *);
0154     s32  (*check_for_link)(struct e1000_hw *);
0155     void (*clear_vfta)(struct e1000_hw *);
0156     s32  (*get_bus_info)(struct e1000_hw *);
0157     s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
0158     void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32, u32, u32);
0159     s32  (*set_uc_addr)(struct e1000_hw *, u32, u8 *);
0160     s32  (*reset_hw)(struct e1000_hw *);
0161     s32  (*init_hw)(struct e1000_hw *);
0162     s32  (*setup_link)(struct e1000_hw *);
0163     void (*write_vfta)(struct e1000_hw *, u32, u32);
0164     void (*mta_set)(struct e1000_hw *, u32);
0165     void (*rar_set)(struct e1000_hw *, u8*, u32);
0166     s32  (*read_mac_addr)(struct e1000_hw *);
0167     s32  (*set_vfta)(struct e1000_hw *, u16, bool);
0168 };
0169
0170 struct e1000_mac_info {
0171     struct e1000_mac_operations ops;
0172     u8 addr[6];
0173     u8 perm_addr[6];
0174
0175     enum e1000_mac_type type;
0176
0177     u16 mta_reg_count;
0178     u16 rar_entry_count;
0179
0180     bool get_link_status;
0181 };
0182
0183 struct e1000_mbx_operations {
0184     s32 (*init_params)(struct e1000_hw *hw);
0185     s32 (*read)(struct e1000_hw *, u32 *, u16);
0186     s32 (*write)(struct e1000_hw *, u32 *, u16);
0187     s32 (*read_posted)(struct e1000_hw *, u32 *, u16);
0188     s32 (*write_posted)(struct e1000_hw *, u32 *, u16);
0189     s32 (*check_for_msg)(struct e1000_hw *);
0190     s32 (*check_for_ack)(struct e1000_hw *);
0191     s32 (*check_for_rst)(struct e1000_hw *);
0192 };
0193
0194 struct e1000_mbx_stats {
0195     u32 msgs_tx;
0196     u32 msgs_rx;
0197
0198     u32 acks;
0199     u32 reqs;
0200     u32 rsts;
0201 };
0202
0203 struct e1000_mbx_info {
0204     struct e1000_mbx_operations ops;
0205     struct e1000_mbx_stats stats;
0206     u32 timeout;
0207     u32 usec_delay;
0208     u16 size;
0209 };
0210
0211 struct e1000_dev_spec_vf {
0212     u32 vf_number;
0213     u32 v2p_mailbox;
0214 };
0215
0216 struct e1000_hw {
0217     void *back;
0218
0219     u8 __iomem *hw_addr;
0220     u8 __iomem *flash_address;
0221     unsigned long io_base;
0222
0223     struct e1000_mac_info  mac;
0224     struct e1000_mbx_info mbx;
0225     spinlock_t mbx_lock;        /* serializes mailbox ops */
0226
0227     union {
0228         struct e1000_dev_spec_vf vf;
0229     } dev_spec;
0230
0231     u16 device_id;
0232     u16 subsystem_vendor_id;
0233     u16 subsystem_device_id;
0234     u16 vendor_id;
0235
0236     u8  revision_id;
0237 };
0238
0239 /* These functions must be implemented by drivers */
0240 void e1000_rlpml_set_vf(struct e1000_hw *, u16);
0241 void e1000_init_function_pointers_vf(struct e1000_hw *hw);
0242
0243 #endif /* _E1000_VF_H_ */