intel/igbvf/defines.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 1999 - 2018 Intel Corporation. */
0003
0004 #ifndef _E1000_DEFINES_H_
0005 #define _E1000_DEFINES_H_
0006
0007 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
0008 #define REQ_TX_DESCRIPTOR_MULTIPLE  8
0009 #define REQ_RX_DESCRIPTOR_MULTIPLE  8
0010
0011 /* IVAR valid bit */
0012 #define E1000_IVAR_VALID    0x80
0013
0014 /* Receive Descriptor bit definitions */
0015 #define E1000_RXD_STAT_DD   0x01    /* Descriptor Done */
0016 #define E1000_RXD_STAT_EOP  0x02    /* End of Packet */
0017 #define E1000_RXD_STAT_IXSM 0x04    /* Ignore checksum */
0018 #define E1000_RXD_STAT_VP   0x08    /* IEEE VLAN Packet */
0019 #define E1000_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
0020 #define E1000_RXD_STAT_TCPCS    0x20    /* TCP xsum calculated */
0021 #define E1000_RXD_STAT_IPCS 0x40    /* IP xsum calculated */
0022 #define E1000_RXD_ERR_SE    0x02    /* Symbol Error */
0023 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF  /* VLAN ID is in lower 12 bits */
0024
0025 #define E1000_RXDEXT_STATERR_LB 0x00040000
0026 #define E1000_RXDEXT_STATERR_CE 0x01000000
0027 #define E1000_RXDEXT_STATERR_SE 0x02000000
0028 #define E1000_RXDEXT_STATERR_SEQ    0x04000000
0029 #define E1000_RXDEXT_STATERR_CXE    0x10000000
0030 #define E1000_RXDEXT_STATERR_TCPE   0x20000000
0031 #define E1000_RXDEXT_STATERR_IPE    0x40000000
0032 #define E1000_RXDEXT_STATERR_RXE    0x80000000
0033
0034 /* Same mask, but for extended and packet split descriptors */
0035 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \
0036     E1000_RXDEXT_STATERR_CE  | \
0037     E1000_RXDEXT_STATERR_SE  | \
0038     E1000_RXDEXT_STATERR_SEQ | \
0039     E1000_RXDEXT_STATERR_CXE | \
0040     E1000_RXDEXT_STATERR_RXE)
0041
0042 /* Device Control */
0043 #define E1000_CTRL_RST      0x04000000  /* Global reset */
0044
0045 /* Device Status */
0046 #define E1000_STATUS_FD     0x00000001      /* Full duplex.0=half,1=full */
0047 #define E1000_STATUS_LU     0x00000002      /* Link up.0=no,1=link */
0048 #define E1000_STATUS_TXOFF  0x00000010      /* transmission paused */
0049 #define E1000_STATUS_SPEED_10   0x00000000      /* Speed 10Mb/s */
0050 #define E1000_STATUS_SPEED_100  0x00000040      /* Speed 100Mb/s */
0051 #define E1000_STATUS_SPEED_1000 0x00000080      /* Speed 1000Mb/s */
0052
0053 #define SPEED_10    10
0054 #define SPEED_100   100
0055 #define SPEED_1000  1000
0056 #define HALF_DUPLEX 1
0057 #define FULL_DUPLEX 2
0058
0059 /* Transmit Descriptor bit definitions */
0060 #define E1000_TXD_POPTS_IXSM    0x01       /* Insert IP checksum */
0061 #define E1000_TXD_POPTS_TXSM    0x02       /* Insert TCP/UDP checksum */
0062 #define E1000_TXD_CMD_DEXT  0x20000000 /* Desc extension (0 = legacy) */
0063 #define E1000_TXD_STAT_DD   0x00000001 /* Desc Done */
0064
0065 #define MAX_JUMBO_FRAME_SIZE        0x3F00
0066 #define MAX_STD_JUMBO_FRAME_SIZE    9216
0067
0068 /* 802.1q VLAN Packet Size */
0069 #define VLAN_TAG_SIZE       4    /* 802.3ac tag (not DMA'd) */
0070
0071 /* Error Codes */
0072 #define E1000_SUCCESS       0
0073 #define E1000_ERR_CONFIG    3
0074 #define E1000_ERR_MAC_INIT  5
0075 #define E1000_ERR_MBX       15
0076
0077 /* SRRCTL bit definitions */
0078 #define E1000_SRRCTL_BSIZEPKT_SHIFT     10 /* Shift _right_ */
0079 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK      0x00000F00
0080 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT     2  /* Shift _left_ */
0081 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF    0x02000000
0082 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS  0x0A000000
0083 #define E1000_SRRCTL_DESCTYPE_MASK      0x0E000000
0084 #define E1000_SRRCTL_DROP_EN            0x80000000
0085
0086 #define E1000_SRRCTL_BSIZEPKT_MASK  0x0000007F
0087 #define E1000_SRRCTL_BSIZEHDR_MASK  0x00003F00
0088
0089 /* Additional Descriptor Control definitions */
0090 #define E1000_TXDCTL_QUEUE_ENABLE   0x02000000 /* Enable specific Tx Que */
0091 #define E1000_RXDCTL_QUEUE_ENABLE   0x02000000 /* Enable specific Rx Que */
0092
0093 /* Direct Cache Access (DCA) definitions */
0094 #define E1000_DCA_TXCTRL_TX_WB_RO_EN    BIT(11) /* Tx Desc writeback RO bit */
0095
0096 #define E1000_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
0097
0098 #endif /* _E1000_DEFINES_H_ */