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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Copyright (C) 2011 Richard Cochran <richardcochran@gmail.com> */
0003 
0004 #include <linux/module.h>
0005 #include <linux/device.h>
0006 #include <linux/pci.h>
0007 #include <linux/ptp_classify.h>
0008 
0009 #include "igb.h"
0010 
0011 #define INCVALUE_MASK       0x7fffffff
0012 #define ISGN            0x80000000
0013 
0014 /* The 82580 timesync updates the system timer every 8ns by 8ns,
0015  * and this update value cannot be reprogrammed.
0016  *
0017  * Neither the 82576 nor the 82580 offer registers wide enough to hold
0018  * nanoseconds time values for very long. For the 82580, SYSTIM always
0019  * counts nanoseconds, but the upper 24 bits are not available. The
0020  * frequency is adjusted by changing the 32 bit fractional nanoseconds
0021  * register, TIMINCA.
0022  *
0023  * For the 82576, the SYSTIM register time unit is affect by the
0024  * choice of the 24 bit TININCA:IV (incvalue) field. Five bits of this
0025  * field are needed to provide the nominal 16 nanosecond period,
0026  * leaving 19 bits for fractional nanoseconds.
0027  *
0028  * We scale the NIC clock cycle by a large factor so that relatively
0029  * small clock corrections can be added or subtracted at each clock
0030  * tick. The drawbacks of a large factor are a) that the clock
0031  * register overflows more quickly (not such a big deal) and b) that
0032  * the increment per tick has to fit into 24 bits.  As a result we
0033  * need to use a shift of 19 so we can fit a value of 16 into the
0034  * TIMINCA register.
0035  *
0036  *
0037  *             SYSTIMH            SYSTIML
0038  *        +--------------+   +---+---+------+
0039  *  82576 |      32      |   | 8 | 5 |  19  |
0040  *        +--------------+   +---+---+------+
0041  *         \________ 45 bits _______/  fract
0042  *
0043  *        +----------+---+   +--------------+
0044  *  82580 |    24    | 8 |   |      32      |
0045  *        +----------+---+   +--------------+
0046  *          reserved  \______ 40 bits _____/
0047  *
0048  *
0049  * The 45 bit 82576 SYSTIM overflows every
0050  *   2^45 * 10^-9 / 3600 = 9.77 hours.
0051  *
0052  * The 40 bit 82580 SYSTIM overflows every
0053  *   2^40 * 10^-9 /  60  = 18.3 minutes.
0054  *
0055  * SYSTIM is converted to real time using a timecounter. As
0056  * timecounter_cyc2time() allows old timestamps, the timecounter needs
0057  * to be updated at least once per half of the SYSTIM interval.
0058  * Scheduling of delayed work is not very accurate, and also the NIC
0059  * clock can be adjusted to run up to 6% faster and the system clock
0060  * up to 10% slower, so we aim for 6 minutes to be sure the actual
0061  * interval in the NIC time is shorter than 9.16 minutes.
0062  */
0063 
0064 #define IGB_SYSTIM_OVERFLOW_PERIOD  (HZ * 60 * 6)
0065 #define IGB_PTP_TX_TIMEOUT      (HZ * 15)
0066 #define INCPERIOD_82576         BIT(E1000_TIMINCA_16NS_SHIFT)
0067 #define INCVALUE_82576_MASK     GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
0068 #define INCVALUE_82576          (16u << IGB_82576_TSYNC_SHIFT)
0069 #define IGB_NBITS_82580         40
0070 
0071 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
0072 static void igb_ptp_sdp_init(struct igb_adapter *adapter);
0073 
0074 /* SYSTIM read access for the 82576 */
0075 static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
0076 {
0077     struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
0078     struct e1000_hw *hw = &igb->hw;
0079     u64 val;
0080     u32 lo, hi;
0081 
0082     lo = rd32(E1000_SYSTIML);
0083     hi = rd32(E1000_SYSTIMH);
0084 
0085     val = ((u64) hi) << 32;
0086     val |= lo;
0087 
0088     return val;
0089 }
0090 
0091 /* SYSTIM read access for the 82580 */
0092 static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
0093 {
0094     struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
0095     struct e1000_hw *hw = &igb->hw;
0096     u32 lo, hi;
0097     u64 val;
0098 
0099     /* The timestamp latches on lowest register read. For the 82580
0100      * the lowest register is SYSTIMR instead of SYSTIML.  However we only
0101      * need to provide nanosecond resolution, so we just ignore it.
0102      */
0103     rd32(E1000_SYSTIMR);
0104     lo = rd32(E1000_SYSTIML);
0105     hi = rd32(E1000_SYSTIMH);
0106 
0107     val = ((u64) hi) << 32;
0108     val |= lo;
0109 
0110     return val;
0111 }
0112 
0113 /* SYSTIM read access for I210/I211 */
0114 static void igb_ptp_read_i210(struct igb_adapter *adapter,
0115                   struct timespec64 *ts)
0116 {
0117     struct e1000_hw *hw = &adapter->hw;
0118     u32 sec, nsec;
0119 
0120     /* The timestamp latches on lowest register read. For I210/I211, the
0121      * lowest register is SYSTIMR. Since we only need to provide nanosecond
0122      * resolution, we can ignore it.
0123      */
0124     rd32(E1000_SYSTIMR);
0125     nsec = rd32(E1000_SYSTIML);
0126     sec = rd32(E1000_SYSTIMH);
0127 
0128     ts->tv_sec = sec;
0129     ts->tv_nsec = nsec;
0130 }
0131 
0132 static void igb_ptp_write_i210(struct igb_adapter *adapter,
0133                    const struct timespec64 *ts)
0134 {
0135     struct e1000_hw *hw = &adapter->hw;
0136 
0137     /* Writing the SYSTIMR register is not necessary as it only provides
0138      * sub-nanosecond resolution.
0139      */
0140     wr32(E1000_SYSTIML, ts->tv_nsec);
0141     wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
0142 }
0143 
0144 /**
0145  * igb_ptp_systim_to_hwtstamp - convert system time value to hw timestamp
0146  * @adapter: board private structure
0147  * @hwtstamps: timestamp structure to update
0148  * @systim: unsigned 64bit system time value.
0149  *
0150  * We need to convert the system time value stored in the RX/TXSTMP registers
0151  * into a hwtstamp which can be used by the upper level timestamping functions.
0152  *
0153  * The 'tmreg_lock' spinlock is used to protect the consistency of the
0154  * system time value. This is needed because reading the 64 bit time
0155  * value involves reading two (or three) 32 bit registers. The first
0156  * read latches the value. Ditto for writing.
0157  *
0158  * In addition, here have extended the system time with an overflow
0159  * counter in software.
0160  **/
0161 static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
0162                        struct skb_shared_hwtstamps *hwtstamps,
0163                        u64 systim)
0164 {
0165     unsigned long flags;
0166     u64 ns;
0167 
0168     memset(hwtstamps, 0, sizeof(*hwtstamps));
0169 
0170     switch (adapter->hw.mac.type) {
0171     case e1000_82576:
0172     case e1000_82580:
0173     case e1000_i354:
0174     case e1000_i350:
0175         spin_lock_irqsave(&adapter->tmreg_lock, flags);
0176         ns = timecounter_cyc2time(&adapter->tc, systim);
0177         spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
0178 
0179         hwtstamps->hwtstamp = ns_to_ktime(ns);
0180         break;
0181     case e1000_i210:
0182     case e1000_i211:
0183         /* Upper 32 bits contain s, lower 32 bits contain ns. */
0184         hwtstamps->hwtstamp = ktime_set(systim >> 32,
0185                         systim & 0xFFFFFFFF);
0186         break;
0187     default:
0188         break;
0189     }
0190 }
0191 
0192 /* PTP clock operations */
0193 static int igb_ptp_adjfine_82576(struct ptp_clock_info *ptp, long scaled_ppm)
0194 {
0195     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0196                            ptp_caps);
0197     struct e1000_hw *hw = &igb->hw;
0198     int neg_adj = 0;
0199     u64 rate;
0200     u32 incvalue;
0201 
0202     if (scaled_ppm < 0) {
0203         neg_adj = 1;
0204         scaled_ppm = -scaled_ppm;
0205     }
0206 
0207     incvalue = INCVALUE_82576;
0208     rate = mul_u64_u64_div_u64(incvalue, (u64)scaled_ppm,
0209                    1000000ULL << 16);
0210 
0211     if (neg_adj)
0212         incvalue -= rate;
0213     else
0214         incvalue += rate;
0215 
0216     wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
0217 
0218     return 0;
0219 }
0220 
0221 static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
0222 {
0223     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0224                            ptp_caps);
0225     struct e1000_hw *hw = &igb->hw;
0226     int neg_adj = 0;
0227     u64 rate;
0228     u32 inca;
0229 
0230     if (scaled_ppm < 0) {
0231         neg_adj = 1;
0232         scaled_ppm = -scaled_ppm;
0233     }
0234     rate = scaled_ppm;
0235     rate <<= 13;
0236     rate = div_u64(rate, 15625);
0237 
0238     inca = rate & INCVALUE_MASK;
0239     if (neg_adj)
0240         inca |= ISGN;
0241 
0242     wr32(E1000_TIMINCA, inca);
0243 
0244     return 0;
0245 }
0246 
0247 static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
0248 {
0249     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0250                            ptp_caps);
0251     unsigned long flags;
0252 
0253     spin_lock_irqsave(&igb->tmreg_lock, flags);
0254     timecounter_adjtime(&igb->tc, delta);
0255     spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0256 
0257     return 0;
0258 }
0259 
0260 static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
0261 {
0262     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0263                            ptp_caps);
0264     unsigned long flags;
0265     struct timespec64 now, then = ns_to_timespec64(delta);
0266 
0267     spin_lock_irqsave(&igb->tmreg_lock, flags);
0268 
0269     igb_ptp_read_i210(igb, &now);
0270     now = timespec64_add(now, then);
0271     igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
0272 
0273     spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0274 
0275     return 0;
0276 }
0277 
0278 static int igb_ptp_gettimex_82576(struct ptp_clock_info *ptp,
0279                   struct timespec64 *ts,
0280                   struct ptp_system_timestamp *sts)
0281 {
0282     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0283                            ptp_caps);
0284     struct e1000_hw *hw = &igb->hw;
0285     unsigned long flags;
0286     u32 lo, hi;
0287     u64 ns;
0288 
0289     spin_lock_irqsave(&igb->tmreg_lock, flags);
0290 
0291     ptp_read_system_prets(sts);
0292     lo = rd32(E1000_SYSTIML);
0293     ptp_read_system_postts(sts);
0294     hi = rd32(E1000_SYSTIMH);
0295 
0296     ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo);
0297 
0298     spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0299 
0300     *ts = ns_to_timespec64(ns);
0301 
0302     return 0;
0303 }
0304 
0305 static int igb_ptp_gettimex_82580(struct ptp_clock_info *ptp,
0306                   struct timespec64 *ts,
0307                   struct ptp_system_timestamp *sts)
0308 {
0309     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0310                            ptp_caps);
0311     struct e1000_hw *hw = &igb->hw;
0312     unsigned long flags;
0313     u32 lo, hi;
0314     u64 ns;
0315 
0316     spin_lock_irqsave(&igb->tmreg_lock, flags);
0317 
0318     ptp_read_system_prets(sts);
0319     rd32(E1000_SYSTIMR);
0320     ptp_read_system_postts(sts);
0321     lo = rd32(E1000_SYSTIML);
0322     hi = rd32(E1000_SYSTIMH);
0323 
0324     ns = timecounter_cyc2time(&igb->tc, ((u64)hi << 32) | lo);
0325 
0326     spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0327 
0328     *ts = ns_to_timespec64(ns);
0329 
0330     return 0;
0331 }
0332 
0333 static int igb_ptp_gettimex_i210(struct ptp_clock_info *ptp,
0334                  struct timespec64 *ts,
0335                  struct ptp_system_timestamp *sts)
0336 {
0337     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0338                            ptp_caps);
0339     struct e1000_hw *hw = &igb->hw;
0340     unsigned long flags;
0341 
0342     spin_lock_irqsave(&igb->tmreg_lock, flags);
0343 
0344     ptp_read_system_prets(sts);
0345     rd32(E1000_SYSTIMR);
0346     ptp_read_system_postts(sts);
0347     ts->tv_nsec = rd32(E1000_SYSTIML);
0348     ts->tv_sec = rd32(E1000_SYSTIMH);
0349 
0350     spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0351 
0352     return 0;
0353 }
0354 
0355 static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
0356                  const struct timespec64 *ts)
0357 {
0358     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0359                            ptp_caps);
0360     unsigned long flags;
0361     u64 ns;
0362 
0363     ns = timespec64_to_ns(ts);
0364 
0365     spin_lock_irqsave(&igb->tmreg_lock, flags);
0366 
0367     timecounter_init(&igb->tc, &igb->cc, ns);
0368 
0369     spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0370 
0371     return 0;
0372 }
0373 
0374 static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
0375                 const struct timespec64 *ts)
0376 {
0377     struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
0378                            ptp_caps);
0379     unsigned long flags;
0380 
0381     spin_lock_irqsave(&igb->tmreg_lock, flags);
0382 
0383     igb_ptp_write_i210(igb, ts);
0384 
0385     spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0386 
0387     return 0;
0388 }
0389 
0390 static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
0391 {
0392     u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
0393     static const u32 mask[IGB_N_SDP] = {
0394         E1000_CTRL_SDP0_DIR,
0395         E1000_CTRL_SDP1_DIR,
0396         E1000_CTRL_EXT_SDP2_DIR,
0397         E1000_CTRL_EXT_SDP3_DIR,
0398     };
0399 
0400     if (input)
0401         *ptr &= ~mask[pin];
0402     else
0403         *ptr |= mask[pin];
0404 }
0405 
0406 static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
0407 {
0408     static const u32 aux0_sel_sdp[IGB_N_SDP] = {
0409         AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
0410     };
0411     static const u32 aux1_sel_sdp[IGB_N_SDP] = {
0412         AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
0413     };
0414     static const u32 ts_sdp_en[IGB_N_SDP] = {
0415         TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
0416     };
0417     struct e1000_hw *hw = &igb->hw;
0418     u32 ctrl, ctrl_ext, tssdp = 0;
0419 
0420     ctrl = rd32(E1000_CTRL);
0421     ctrl_ext = rd32(E1000_CTRL_EXT);
0422     tssdp = rd32(E1000_TSSDP);
0423 
0424     igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
0425 
0426     /* Make sure this pin is not enabled as an output. */
0427     tssdp &= ~ts_sdp_en[pin];
0428 
0429     if (chan == 1) {
0430         tssdp &= ~AUX1_SEL_SDP3;
0431         tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
0432     } else {
0433         tssdp &= ~AUX0_SEL_SDP3;
0434         tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
0435     }
0436 
0437     wr32(E1000_TSSDP, tssdp);
0438     wr32(E1000_CTRL, ctrl);
0439     wr32(E1000_CTRL_EXT, ctrl_ext);
0440 }
0441 
0442 static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
0443 {
0444     static const u32 aux0_sel_sdp[IGB_N_SDP] = {
0445         AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
0446     };
0447     static const u32 aux1_sel_sdp[IGB_N_SDP] = {
0448         AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
0449     };
0450     static const u32 ts_sdp_en[IGB_N_SDP] = {
0451         TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
0452     };
0453     static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
0454         TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
0455         TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
0456     };
0457     static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
0458         TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
0459         TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
0460     };
0461     static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
0462         TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
0463         TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
0464     };
0465     static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
0466         TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
0467         TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
0468     };
0469     static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
0470         TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
0471         TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
0472     };
0473     struct e1000_hw *hw = &igb->hw;
0474     u32 ctrl, ctrl_ext, tssdp = 0;
0475 
0476     ctrl = rd32(E1000_CTRL);
0477     ctrl_ext = rd32(E1000_CTRL_EXT);
0478     tssdp = rd32(E1000_TSSDP);
0479 
0480     igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
0481 
0482     /* Make sure this pin is not enabled as an input. */
0483     if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
0484         tssdp &= ~AUX0_TS_SDP_EN;
0485 
0486     if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
0487         tssdp &= ~AUX1_TS_SDP_EN;
0488 
0489     tssdp &= ~ts_sdp_sel_clr[pin];
0490     if (freq) {
0491         if (chan == 1)
0492             tssdp |= ts_sdp_sel_fc1[pin];
0493         else
0494             tssdp |= ts_sdp_sel_fc0[pin];
0495     } else {
0496         if (chan == 1)
0497             tssdp |= ts_sdp_sel_tt1[pin];
0498         else
0499             tssdp |= ts_sdp_sel_tt0[pin];
0500     }
0501     tssdp |= ts_sdp_en[pin];
0502 
0503     wr32(E1000_TSSDP, tssdp);
0504     wr32(E1000_CTRL, ctrl);
0505     wr32(E1000_CTRL_EXT, ctrl_ext);
0506 }
0507 
0508 static int igb_ptp_feature_enable_82580(struct ptp_clock_info *ptp,
0509                     struct ptp_clock_request *rq, int on)
0510 {
0511     struct igb_adapter *igb =
0512         container_of(ptp, struct igb_adapter, ptp_caps);
0513     u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, systiml,
0514         systimh, level_mask, level, rem;
0515     struct e1000_hw *hw = &igb->hw;
0516     struct timespec64 ts, start;
0517     unsigned long flags;
0518     u64 systim, now;
0519     int pin = -1;
0520     s64 ns;
0521 
0522     switch (rq->type) {
0523     case PTP_CLK_REQ_EXTTS:
0524         /* Reject requests with unsupported flags */
0525         if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
0526                     PTP_RISING_EDGE |
0527                     PTP_FALLING_EDGE |
0528                     PTP_STRICT_FLAGS))
0529             return -EOPNOTSUPP;
0530 
0531         if (on) {
0532             pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
0533                        rq->extts.index);
0534             if (pin < 0)
0535                 return -EBUSY;
0536         }
0537         if (rq->extts.index == 1) {
0538             tsauxc_mask = TSAUXC_EN_TS1;
0539             tsim_mask = TSINTR_AUTT1;
0540         } else {
0541             tsauxc_mask = TSAUXC_EN_TS0;
0542             tsim_mask = TSINTR_AUTT0;
0543         }
0544         spin_lock_irqsave(&igb->tmreg_lock, flags);
0545         tsauxc = rd32(E1000_TSAUXC);
0546         tsim = rd32(E1000_TSIM);
0547         if (on) {
0548             igb_pin_extts(igb, rq->extts.index, pin);
0549             tsauxc |= tsauxc_mask;
0550             tsim |= tsim_mask;
0551         } else {
0552             tsauxc &= ~tsauxc_mask;
0553             tsim &= ~tsim_mask;
0554         }
0555         wr32(E1000_TSAUXC, tsauxc);
0556         wr32(E1000_TSIM, tsim);
0557         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0558         return 0;
0559 
0560     case PTP_CLK_REQ_PEROUT:
0561         /* Reject requests with unsupported flags */
0562         if (rq->perout.flags)
0563             return -EOPNOTSUPP;
0564 
0565         if (on) {
0566             pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
0567                        rq->perout.index);
0568             if (pin < 0)
0569                 return -EBUSY;
0570         }
0571         ts.tv_sec = rq->perout.period.sec;
0572         ts.tv_nsec = rq->perout.period.nsec;
0573         ns = timespec64_to_ns(&ts);
0574         ns = ns >> 1;
0575         if (on && ns < 8LL)
0576             return -EINVAL;
0577         ts = ns_to_timespec64(ns);
0578         if (rq->perout.index == 1) {
0579             tsauxc_mask = TSAUXC_EN_TT1;
0580             tsim_mask = TSINTR_TT1;
0581             trgttiml = E1000_TRGTTIML1;
0582             trgttimh = E1000_TRGTTIMH1;
0583         } else {
0584             tsauxc_mask = TSAUXC_EN_TT0;
0585             tsim_mask = TSINTR_TT0;
0586             trgttiml = E1000_TRGTTIML0;
0587             trgttimh = E1000_TRGTTIMH0;
0588         }
0589         spin_lock_irqsave(&igb->tmreg_lock, flags);
0590         tsauxc = rd32(E1000_TSAUXC);
0591         tsim = rd32(E1000_TSIM);
0592         if (rq->perout.index == 1) {
0593             tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
0594             tsim &= ~TSINTR_TT1;
0595         } else {
0596             tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
0597             tsim &= ~TSINTR_TT0;
0598         }
0599         if (on) {
0600             int i = rq->perout.index;
0601 
0602             /* read systim registers in sequence */
0603             rd32(E1000_SYSTIMR);
0604             systiml = rd32(E1000_SYSTIML);
0605             systimh = rd32(E1000_SYSTIMH);
0606             systim = (((u64)(systimh & 0xFF)) << 32) | ((u64)systiml);
0607             now = timecounter_cyc2time(&igb->tc, systim);
0608 
0609             if (pin < 2) {
0610                 level_mask = (i == 1) ? 0x80000 : 0x40000;
0611                 level = (rd32(E1000_CTRL) & level_mask) ? 1 : 0;
0612             } else {
0613                 level_mask = (i == 1) ? 0x80 : 0x40;
0614                 level = (rd32(E1000_CTRL_EXT) & level_mask) ? 1 : 0;
0615             }
0616 
0617             div_u64_rem(now, ns, &rem);
0618             systim = systim + (ns - rem);
0619 
0620             /* synchronize pin level with rising/falling edges */
0621             div_u64_rem(now, ns << 1, &rem);
0622             if (rem < ns) {
0623                 /* first half of period */
0624                 if (level == 0) {
0625                     /* output is already low, skip this period */
0626                     systim += ns;
0627                 }
0628             } else {
0629                 /* second half of period */
0630                 if (level == 1) {
0631                     /* output is already high, skip this period */
0632                     systim += ns;
0633                 }
0634             }
0635 
0636             start = ns_to_timespec64(systim + (ns - rem));
0637             igb_pin_perout(igb, i, pin, 0);
0638             igb->perout[i].start.tv_sec = start.tv_sec;
0639             igb->perout[i].start.tv_nsec = start.tv_nsec;
0640             igb->perout[i].period.tv_sec = ts.tv_sec;
0641             igb->perout[i].period.tv_nsec = ts.tv_nsec;
0642 
0643             wr32(trgttiml, (u32)systim);
0644             wr32(trgttimh, ((u32)(systim >> 32)) & 0xFF);
0645             tsauxc |= tsauxc_mask;
0646             tsim |= tsim_mask;
0647         }
0648         wr32(E1000_TSAUXC, tsauxc);
0649         wr32(E1000_TSIM, tsim);
0650         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0651         return 0;
0652 
0653     case PTP_CLK_REQ_PPS:
0654         return -EOPNOTSUPP;
0655     }
0656 
0657     return -EOPNOTSUPP;
0658 }
0659 
0660 static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
0661                        struct ptp_clock_request *rq, int on)
0662 {
0663     struct igb_adapter *igb =
0664         container_of(ptp, struct igb_adapter, ptp_caps);
0665     struct e1000_hw *hw = &igb->hw;
0666     u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
0667     unsigned long flags;
0668     struct timespec64 ts;
0669     int use_freq = 0, pin = -1;
0670     s64 ns;
0671 
0672     switch (rq->type) {
0673     case PTP_CLK_REQ_EXTTS:
0674         /* Reject requests with unsupported flags */
0675         if (rq->extts.flags & ~(PTP_ENABLE_FEATURE |
0676                     PTP_RISING_EDGE |
0677                     PTP_FALLING_EDGE |
0678                     PTP_STRICT_FLAGS))
0679             return -EOPNOTSUPP;
0680 
0681         /* Reject requests failing to enable both edges. */
0682         if ((rq->extts.flags & PTP_STRICT_FLAGS) &&
0683             (rq->extts.flags & PTP_ENABLE_FEATURE) &&
0684             (rq->extts.flags & PTP_EXTTS_EDGES) != PTP_EXTTS_EDGES)
0685             return -EOPNOTSUPP;
0686 
0687         if (on) {
0688             pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
0689                        rq->extts.index);
0690             if (pin < 0)
0691                 return -EBUSY;
0692         }
0693         if (rq->extts.index == 1) {
0694             tsauxc_mask = TSAUXC_EN_TS1;
0695             tsim_mask = TSINTR_AUTT1;
0696         } else {
0697             tsauxc_mask = TSAUXC_EN_TS0;
0698             tsim_mask = TSINTR_AUTT0;
0699         }
0700         spin_lock_irqsave(&igb->tmreg_lock, flags);
0701         tsauxc = rd32(E1000_TSAUXC);
0702         tsim = rd32(E1000_TSIM);
0703         if (on) {
0704             igb_pin_extts(igb, rq->extts.index, pin);
0705             tsauxc |= tsauxc_mask;
0706             tsim |= tsim_mask;
0707         } else {
0708             tsauxc &= ~tsauxc_mask;
0709             tsim &= ~tsim_mask;
0710         }
0711         wr32(E1000_TSAUXC, tsauxc);
0712         wr32(E1000_TSIM, tsim);
0713         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0714         return 0;
0715 
0716     case PTP_CLK_REQ_PEROUT:
0717         /* Reject requests with unsupported flags */
0718         if (rq->perout.flags)
0719             return -EOPNOTSUPP;
0720 
0721         if (on) {
0722             pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
0723                        rq->perout.index);
0724             if (pin < 0)
0725                 return -EBUSY;
0726         }
0727         ts.tv_sec = rq->perout.period.sec;
0728         ts.tv_nsec = rq->perout.period.nsec;
0729         ns = timespec64_to_ns(&ts);
0730         ns = ns >> 1;
0731         if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
0732                (ns == 250000000LL) || (ns == 500000000LL))) {
0733             if (ns < 8LL)
0734                 return -EINVAL;
0735             use_freq = 1;
0736         }
0737         ts = ns_to_timespec64(ns);
0738         if (rq->perout.index == 1) {
0739             if (use_freq) {
0740                 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
0741                 tsim_mask = 0;
0742             } else {
0743                 tsauxc_mask = TSAUXC_EN_TT1;
0744                 tsim_mask = TSINTR_TT1;
0745             }
0746             trgttiml = E1000_TRGTTIML1;
0747             trgttimh = E1000_TRGTTIMH1;
0748             freqout = E1000_FREQOUT1;
0749         } else {
0750             if (use_freq) {
0751                 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
0752                 tsim_mask = 0;
0753             } else {
0754                 tsauxc_mask = TSAUXC_EN_TT0;
0755                 tsim_mask = TSINTR_TT0;
0756             }
0757             trgttiml = E1000_TRGTTIML0;
0758             trgttimh = E1000_TRGTTIMH0;
0759             freqout = E1000_FREQOUT0;
0760         }
0761         spin_lock_irqsave(&igb->tmreg_lock, flags);
0762         tsauxc = rd32(E1000_TSAUXC);
0763         tsim = rd32(E1000_TSIM);
0764         if (rq->perout.index == 1) {
0765             tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
0766             tsim &= ~TSINTR_TT1;
0767         } else {
0768             tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
0769             tsim &= ~TSINTR_TT0;
0770         }
0771         if (on) {
0772             int i = rq->perout.index;
0773             igb_pin_perout(igb, i, pin, use_freq);
0774             igb->perout[i].start.tv_sec = rq->perout.start.sec;
0775             igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
0776             igb->perout[i].period.tv_sec = ts.tv_sec;
0777             igb->perout[i].period.tv_nsec = ts.tv_nsec;
0778             wr32(trgttimh, rq->perout.start.sec);
0779             wr32(trgttiml, rq->perout.start.nsec);
0780             if (use_freq)
0781                 wr32(freqout, ns);
0782             tsauxc |= tsauxc_mask;
0783             tsim |= tsim_mask;
0784         }
0785         wr32(E1000_TSAUXC, tsauxc);
0786         wr32(E1000_TSIM, tsim);
0787         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0788         return 0;
0789 
0790     case PTP_CLK_REQ_PPS:
0791         spin_lock_irqsave(&igb->tmreg_lock, flags);
0792         tsim = rd32(E1000_TSIM);
0793         if (on)
0794             tsim |= TSINTR_SYS_WRAP;
0795         else
0796             tsim &= ~TSINTR_SYS_WRAP;
0797         igb->pps_sys_wrap_on = !!on;
0798         wr32(E1000_TSIM, tsim);
0799         spin_unlock_irqrestore(&igb->tmreg_lock, flags);
0800         return 0;
0801     }
0802 
0803     return -EOPNOTSUPP;
0804 }
0805 
0806 static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
0807                   struct ptp_clock_request *rq, int on)
0808 {
0809     return -EOPNOTSUPP;
0810 }
0811 
0812 static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
0813                   enum ptp_pin_function func, unsigned int chan)
0814 {
0815     switch (func) {
0816     case PTP_PF_NONE:
0817     case PTP_PF_EXTTS:
0818     case PTP_PF_PEROUT:
0819         break;
0820     case PTP_PF_PHYSYNC:
0821         return -1;
0822     }
0823     return 0;
0824 }
0825 
0826 /**
0827  * igb_ptp_tx_work
0828  * @work: pointer to work struct
0829  *
0830  * This work function polls the TSYNCTXCTL valid bit to determine when a
0831  * timestamp has been taken for the current stored skb.
0832  **/
0833 static void igb_ptp_tx_work(struct work_struct *work)
0834 {
0835     struct igb_adapter *adapter = container_of(work, struct igb_adapter,
0836                            ptp_tx_work);
0837     struct e1000_hw *hw = &adapter->hw;
0838     u32 tsynctxctl;
0839 
0840     if (!adapter->ptp_tx_skb)
0841         return;
0842 
0843     if (time_is_before_jiffies(adapter->ptp_tx_start +
0844                    IGB_PTP_TX_TIMEOUT)) {
0845         dev_kfree_skb_any(adapter->ptp_tx_skb);
0846         adapter->ptp_tx_skb = NULL;
0847         clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
0848         adapter->tx_hwtstamp_timeouts++;
0849         /* Clear the tx valid bit in TSYNCTXCTL register to enable
0850          * interrupt
0851          */
0852         rd32(E1000_TXSTMPH);
0853         dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
0854         return;
0855     }
0856 
0857     tsynctxctl = rd32(E1000_TSYNCTXCTL);
0858     if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
0859         igb_ptp_tx_hwtstamp(adapter);
0860     else
0861         /* reschedule to check later */
0862         schedule_work(&adapter->ptp_tx_work);
0863 }
0864 
0865 static void igb_ptp_overflow_check(struct work_struct *work)
0866 {
0867     struct igb_adapter *igb =
0868         container_of(work, struct igb_adapter, ptp_overflow_work.work);
0869     struct timespec64 ts;
0870     u64 ns;
0871 
0872     /* Update the timecounter */
0873     ns = timecounter_read(&igb->tc);
0874 
0875     ts = ns_to_timespec64(ns);
0876     pr_debug("igb overflow check at %lld.%09lu\n",
0877          (long long) ts.tv_sec, ts.tv_nsec);
0878 
0879     schedule_delayed_work(&igb->ptp_overflow_work,
0880                   IGB_SYSTIM_OVERFLOW_PERIOD);
0881 }
0882 
0883 /**
0884  * igb_ptp_rx_hang - detect error case when Rx timestamp registers latched
0885  * @adapter: private network adapter structure
0886  *
0887  * This watchdog task is scheduled to detect error case where hardware has
0888  * dropped an Rx packet that was timestamped when the ring is full. The
0889  * particular error is rare but leaves the device in a state unable to timestamp
0890  * any future packets.
0891  **/
0892 void igb_ptp_rx_hang(struct igb_adapter *adapter)
0893 {
0894     struct e1000_hw *hw = &adapter->hw;
0895     u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
0896     unsigned long rx_event;
0897 
0898     /* Other hardware uses per-packet timestamps */
0899     if (hw->mac.type != e1000_82576)
0900         return;
0901 
0902     /* If we don't have a valid timestamp in the registers, just update the
0903      * timeout counter and exit
0904      */
0905     if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
0906         adapter->last_rx_ptp_check = jiffies;
0907         return;
0908     }
0909 
0910     /* Determine the most recent watchdog or rx_timestamp event */
0911     rx_event = adapter->last_rx_ptp_check;
0912     if (time_after(adapter->last_rx_timestamp, rx_event))
0913         rx_event = adapter->last_rx_timestamp;
0914 
0915     /* Only need to read the high RXSTMP register to clear the lock */
0916     if (time_is_before_jiffies(rx_event + 5 * HZ)) {
0917         rd32(E1000_RXSTMPH);
0918         adapter->last_rx_ptp_check = jiffies;
0919         adapter->rx_hwtstamp_cleared++;
0920         dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
0921     }
0922 }
0923 
0924 /**
0925  * igb_ptp_tx_hang - detect error case where Tx timestamp never finishes
0926  * @adapter: private network adapter structure
0927  */
0928 void igb_ptp_tx_hang(struct igb_adapter *adapter)
0929 {
0930     struct e1000_hw *hw = &adapter->hw;
0931     bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
0932                           IGB_PTP_TX_TIMEOUT);
0933 
0934     if (!adapter->ptp_tx_skb)
0935         return;
0936 
0937     if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
0938         return;
0939 
0940     /* If we haven't received a timestamp within the timeout, it is
0941      * reasonable to assume that it will never occur, so we can unlock the
0942      * timestamp bit when this occurs.
0943      */
0944     if (timeout) {
0945         cancel_work_sync(&adapter->ptp_tx_work);
0946         dev_kfree_skb_any(adapter->ptp_tx_skb);
0947         adapter->ptp_tx_skb = NULL;
0948         clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
0949         adapter->tx_hwtstamp_timeouts++;
0950         /* Clear the tx valid bit in TSYNCTXCTL register to enable
0951          * interrupt
0952          */
0953         rd32(E1000_TXSTMPH);
0954         dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
0955     }
0956 }
0957 
0958 /**
0959  * igb_ptp_tx_hwtstamp - utility function which checks for TX time stamp
0960  * @adapter: Board private structure.
0961  *
0962  * If we were asked to do hardware stamping and such a time stamp is
0963  * available, then it must have been for this skb here because we only
0964  * allow only one such packet into the queue.
0965  **/
0966 static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
0967 {
0968     struct sk_buff *skb = adapter->ptp_tx_skb;
0969     struct e1000_hw *hw = &adapter->hw;
0970     struct skb_shared_hwtstamps shhwtstamps;
0971     u64 regval;
0972     int adjust = 0;
0973 
0974     regval = rd32(E1000_TXSTMPL);
0975     regval |= (u64)rd32(E1000_TXSTMPH) << 32;
0976 
0977     igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
0978     /* adjust timestamp for the TX latency based on link speed */
0979     if (adapter->hw.mac.type == e1000_i210) {
0980         switch (adapter->link_speed) {
0981         case SPEED_10:
0982             adjust = IGB_I210_TX_LATENCY_10;
0983             break;
0984         case SPEED_100:
0985             adjust = IGB_I210_TX_LATENCY_100;
0986             break;
0987         case SPEED_1000:
0988             adjust = IGB_I210_TX_LATENCY_1000;
0989             break;
0990         }
0991     }
0992 
0993     shhwtstamps.hwtstamp =
0994         ktime_add_ns(shhwtstamps.hwtstamp, adjust);
0995 
0996     /* Clear the lock early before calling skb_tstamp_tx so that
0997      * applications are not woken up before the lock bit is clear. We use
0998      * a copy of the skb pointer to ensure other threads can't change it
0999      * while we're notifying the stack.
1000      */
1001     adapter->ptp_tx_skb = NULL;
1002     clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1003 
1004     /* Notify the stack and free the skb after we've unlocked */
1005     skb_tstamp_tx(skb, &shhwtstamps);
1006     dev_kfree_skb_any(skb);
1007 }
1008 
1009 /**
1010  * igb_ptp_rx_pktstamp - retrieve Rx per packet timestamp
1011  * @q_vector: Pointer to interrupt specific structure
1012  * @va: Pointer to address containing Rx buffer
1013  * @timestamp: Pointer where timestamp will be stored
1014  *
1015  * This function is meant to retrieve a timestamp from the first buffer of an
1016  * incoming frame.  The value is stored in little endian format starting on
1017  * byte 8
1018  *
1019  * Returns: The timestamp header length or 0 if not available
1020  **/
1021 int igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
1022             ktime_t *timestamp)
1023 {
1024     struct igb_adapter *adapter = q_vector->adapter;
1025     struct skb_shared_hwtstamps ts;
1026     __le64 *regval = (__le64 *)va;
1027     int adjust = 0;
1028 
1029     if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1030         return 0;
1031 
1032     /* The timestamp is recorded in little endian format.
1033      * DWORD: 0        1        2        3
1034      * Field: Reserved Reserved SYSTIML  SYSTIMH
1035      */
1036 
1037     /* check reserved dwords are zero, be/le doesn't matter for zero */
1038     if (regval[0])
1039         return 0;
1040 
1041     igb_ptp_systim_to_hwtstamp(adapter, &ts, le64_to_cpu(regval[1]));
1042 
1043     /* adjust timestamp for the RX latency based on link speed */
1044     if (adapter->hw.mac.type == e1000_i210) {
1045         switch (adapter->link_speed) {
1046         case SPEED_10:
1047             adjust = IGB_I210_RX_LATENCY_10;
1048             break;
1049         case SPEED_100:
1050             adjust = IGB_I210_RX_LATENCY_100;
1051             break;
1052         case SPEED_1000:
1053             adjust = IGB_I210_RX_LATENCY_1000;
1054             break;
1055         }
1056     }
1057 
1058     *timestamp = ktime_sub_ns(ts.hwtstamp, adjust);
1059 
1060     return IGB_TS_HDR_LEN;
1061 }
1062 
1063 /**
1064  * igb_ptp_rx_rgtstamp - retrieve Rx timestamp stored in register
1065  * @q_vector: Pointer to interrupt specific structure
1066  * @skb: Buffer containing timestamp and packet
1067  *
1068  * This function is meant to retrieve a timestamp from the internal registers
1069  * of the adapter and store it in the skb.
1070  **/
1071 void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector, struct sk_buff *skb)
1072 {
1073     struct igb_adapter *adapter = q_vector->adapter;
1074     struct e1000_hw *hw = &adapter->hw;
1075     int adjust = 0;
1076     u64 regval;
1077 
1078     if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1079         return;
1080 
1081     /* If this bit is set, then the RX registers contain the time stamp. No
1082      * other packet will be time stamped until we read these registers, so
1083      * read the registers to make them available again. Because only one
1084      * packet can be time stamped at a time, we know that the register
1085      * values must belong to this one here and therefore we don't need to
1086      * compare any of the additional attributes stored for it.
1087      *
1088      * If nothing went wrong, then it should have a shared tx_flags that we
1089      * can turn into a skb_shared_hwtstamps.
1090      */
1091     if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
1092         return;
1093 
1094     regval = rd32(E1000_RXSTMPL);
1095     regval |= (u64)rd32(E1000_RXSTMPH) << 32;
1096 
1097     igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
1098 
1099     /* adjust timestamp for the RX latency based on link speed */
1100     if (adapter->hw.mac.type == e1000_i210) {
1101         switch (adapter->link_speed) {
1102         case SPEED_10:
1103             adjust = IGB_I210_RX_LATENCY_10;
1104             break;
1105         case SPEED_100:
1106             adjust = IGB_I210_RX_LATENCY_100;
1107             break;
1108         case SPEED_1000:
1109             adjust = IGB_I210_RX_LATENCY_1000;
1110             break;
1111         }
1112     }
1113     skb_hwtstamps(skb)->hwtstamp =
1114         ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
1115 
1116     /* Update the last_rx_timestamp timer in order to enable watchdog check
1117      * for error case of latched timestamp on a dropped packet.
1118      */
1119     adapter->last_rx_timestamp = jiffies;
1120 }
1121 
1122 /**
1123  * igb_ptp_get_ts_config - get hardware time stamping config
1124  * @netdev: netdev struct
1125  * @ifr: interface struct
1126  *
1127  * Get the hwtstamp_config settings to return to the user. Rather than attempt
1128  * to deconstruct the settings from the registers, just return a shadow copy
1129  * of the last known settings.
1130  **/
1131 int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
1132 {
1133     struct igb_adapter *adapter = netdev_priv(netdev);
1134     struct hwtstamp_config *config = &adapter->tstamp_config;
1135 
1136     return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
1137         -EFAULT : 0;
1138 }
1139 
1140 /**
1141  * igb_ptp_set_timestamp_mode - setup hardware for timestamping
1142  * @adapter: networking device structure
1143  * @config: hwtstamp configuration
1144  *
1145  * Outgoing time stamping can be enabled and disabled. Play nice and
1146  * disable it when requested, although it shouldn't case any overhead
1147  * when no packet needs it. At most one packet in the queue may be
1148  * marked for time stamping, otherwise it would be impossible to tell
1149  * for sure to which packet the hardware time stamp belongs.
1150  *
1151  * Incoming time stamping has to be configured via the hardware
1152  * filters. Not all combinations are supported, in particular event
1153  * type has to be specified. Matching the kind of event packet is
1154  * not supported, with the exception of "all V2 events regardless of
1155  * level 2 or 4".
1156  */
1157 static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
1158                       struct hwtstamp_config *config)
1159 {
1160     struct e1000_hw *hw = &adapter->hw;
1161     u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
1162     u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1163     u32 tsync_rx_cfg = 0;
1164     bool is_l4 = false;
1165     bool is_l2 = false;
1166     u32 regval;
1167 
1168     switch (config->tx_type) {
1169     case HWTSTAMP_TX_OFF:
1170         tsync_tx_ctl = 0;
1171         break;
1172     case HWTSTAMP_TX_ON:
1173         break;
1174     default:
1175         return -ERANGE;
1176     }
1177 
1178     switch (config->rx_filter) {
1179     case HWTSTAMP_FILTER_NONE:
1180         tsync_rx_ctl = 0;
1181         break;
1182     case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1183         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
1184         tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
1185         is_l4 = true;
1186         break;
1187     case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1188         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
1189         tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
1190         is_l4 = true;
1191         break;
1192     case HWTSTAMP_FILTER_PTP_V2_EVENT:
1193     case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1194     case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1195     case HWTSTAMP_FILTER_PTP_V2_SYNC:
1196     case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1197     case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1198     case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1199     case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1200     case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1201         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
1202         config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1203         is_l2 = true;
1204         is_l4 = true;
1205         break;
1206     case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1207     case HWTSTAMP_FILTER_NTP_ALL:
1208     case HWTSTAMP_FILTER_ALL:
1209         /* 82576 cannot timestamp all packets, which it needs to do to
1210          * support both V1 Sync and Delay_Req messages
1211          */
1212         if (hw->mac.type != e1000_82576) {
1213             tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1214             config->rx_filter = HWTSTAMP_FILTER_ALL;
1215             break;
1216         }
1217         fallthrough;
1218     default:
1219         config->rx_filter = HWTSTAMP_FILTER_NONE;
1220         return -ERANGE;
1221     }
1222 
1223     if (hw->mac.type == e1000_82575) {
1224         if (tsync_rx_ctl | tsync_tx_ctl)
1225             return -EINVAL;
1226         return 0;
1227     }
1228 
1229     /* Per-packet timestamping only works if all packets are
1230      * timestamped, so enable timestamping in all packets as
1231      * long as one Rx filter was configured.
1232      */
1233     if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1234         tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1235         tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1236         config->rx_filter = HWTSTAMP_FILTER_ALL;
1237         is_l2 = true;
1238         is_l4 = true;
1239 
1240         if ((hw->mac.type == e1000_i210) ||
1241             (hw->mac.type == e1000_i211)) {
1242             regval = rd32(E1000_RXPBS);
1243             regval |= E1000_RXPBS_CFG_TS_EN;
1244             wr32(E1000_RXPBS, regval);
1245         }
1246     }
1247 
1248     /* enable/disable TX */
1249     regval = rd32(E1000_TSYNCTXCTL);
1250     regval &= ~E1000_TSYNCTXCTL_ENABLED;
1251     regval |= tsync_tx_ctl;
1252     wr32(E1000_TSYNCTXCTL, regval);
1253 
1254     /* enable/disable RX */
1255     regval = rd32(E1000_TSYNCRXCTL);
1256     regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1257     regval |= tsync_rx_ctl;
1258     wr32(E1000_TSYNCRXCTL, regval);
1259 
1260     /* define which PTP packets are time stamped */
1261     wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1262 
1263     /* define ethertype filter for timestamped packets */
1264     if (is_l2)
1265         wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1266              (E1000_ETQF_FILTER_ENABLE | /* enable filter */
1267               E1000_ETQF_1588 | /* enable timestamping */
1268               ETH_P_1588));     /* 1588 eth protocol type */
1269     else
1270         wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1271 
1272     /* L4 Queue Filter[3]: filter by destination port and protocol */
1273     if (is_l4) {
1274         u32 ftqf = (IPPROTO_UDP /* UDP */
1275             | E1000_FTQF_VF_BP /* VF not compared */
1276             | E1000_FTQF_1588_TIME_STAMP /* Enable Timestamping */
1277             | E1000_FTQF_MASK); /* mask all inputs */
1278         ftqf &= ~E1000_FTQF_MASK_PROTO_BP; /* enable protocol check */
1279 
1280         wr32(E1000_IMIR(3), (__force unsigned int)htons(PTP_EV_PORT));
1281         wr32(E1000_IMIREXT(3),
1282              (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1283         if (hw->mac.type == e1000_82576) {
1284             /* enable source port check */
1285             wr32(E1000_SPQF(3), (__force unsigned int)htons(PTP_EV_PORT));
1286             ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1287         }
1288         wr32(E1000_FTQF(3), ftqf);
1289     } else {
1290         wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1291     }
1292     wrfl();
1293 
1294     /* clear TX/RX time stamp registers, just to be sure */
1295     regval = rd32(E1000_TXSTMPL);
1296     regval = rd32(E1000_TXSTMPH);
1297     regval = rd32(E1000_RXSTMPL);
1298     regval = rd32(E1000_RXSTMPH);
1299 
1300     return 0;
1301 }
1302 
1303 /**
1304  * igb_ptp_set_ts_config - set hardware time stamping config
1305  * @netdev: netdev struct
1306  * @ifr: interface struct
1307  *
1308  **/
1309 int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1310 {
1311     struct igb_adapter *adapter = netdev_priv(netdev);
1312     struct hwtstamp_config config;
1313     int err;
1314 
1315     if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1316         return -EFAULT;
1317 
1318     err = igb_ptp_set_timestamp_mode(adapter, &config);
1319     if (err)
1320         return err;
1321 
1322     /* save these settings for future reference */
1323     memcpy(&adapter->tstamp_config, &config,
1324            sizeof(adapter->tstamp_config));
1325 
1326     return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1327         -EFAULT : 0;
1328 }
1329 
1330 /**
1331  * igb_ptp_init - Initialize PTP functionality
1332  * @adapter: Board private structure
1333  *
1334  * This function is called at device probe to initialize the PTP
1335  * functionality.
1336  */
1337 void igb_ptp_init(struct igb_adapter *adapter)
1338 {
1339     struct e1000_hw *hw = &adapter->hw;
1340     struct net_device *netdev = adapter->netdev;
1341 
1342     switch (hw->mac.type) {
1343     case e1000_82576:
1344         snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1345         adapter->ptp_caps.owner = THIS_MODULE;
1346         adapter->ptp_caps.max_adj = 999999881;
1347         adapter->ptp_caps.n_ext_ts = 0;
1348         adapter->ptp_caps.pps = 0;
1349         adapter->ptp_caps.adjfine = igb_ptp_adjfine_82576;
1350         adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1351         adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82576;
1352         adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1353         adapter->ptp_caps.enable = igb_ptp_feature_enable;
1354         adapter->cc.read = igb_ptp_read_82576;
1355         adapter->cc.mask = CYCLECOUNTER_MASK(64);
1356         adapter->cc.mult = 1;
1357         adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1358         adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1359         break;
1360     case e1000_82580:
1361     case e1000_i354:
1362     case e1000_i350:
1363         igb_ptp_sdp_init(adapter);
1364         snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1365         adapter->ptp_caps.owner = THIS_MODULE;
1366         adapter->ptp_caps.max_adj = 62499999;
1367         adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1368         adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1369         adapter->ptp_caps.n_pins = IGB_N_SDP;
1370         adapter->ptp_caps.pps = 0;
1371         adapter->ptp_caps.pin_config = adapter->sdp_config;
1372         adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1373         adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1374         adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_82580;
1375         adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1376         adapter->ptp_caps.enable = igb_ptp_feature_enable_82580;
1377         adapter->ptp_caps.verify = igb_ptp_verify_pin;
1378         adapter->cc.read = igb_ptp_read_82580;
1379         adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1380         adapter->cc.mult = 1;
1381         adapter->cc.shift = 0;
1382         adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1383         break;
1384     case e1000_i210:
1385     case e1000_i211:
1386         igb_ptp_sdp_init(adapter);
1387         snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1388         adapter->ptp_caps.owner = THIS_MODULE;
1389         adapter->ptp_caps.max_adj = 62499999;
1390         adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1391         adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1392         adapter->ptp_caps.n_pins = IGB_N_SDP;
1393         adapter->ptp_caps.pps = 1;
1394         adapter->ptp_caps.pin_config = adapter->sdp_config;
1395         adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1396         adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1397         adapter->ptp_caps.gettimex64 = igb_ptp_gettimex_i210;
1398         adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1399         adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1400         adapter->ptp_caps.verify = igb_ptp_verify_pin;
1401         break;
1402     default:
1403         adapter->ptp_clock = NULL;
1404         return;
1405     }
1406 
1407     spin_lock_init(&adapter->tmreg_lock);
1408     INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1409 
1410     if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1411         INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1412                   igb_ptp_overflow_check);
1413 
1414     adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1415     adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1416 
1417     igb_ptp_reset(adapter);
1418 
1419     adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1420                         &adapter->pdev->dev);
1421     if (IS_ERR(adapter->ptp_clock)) {
1422         adapter->ptp_clock = NULL;
1423         dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1424     } else if (adapter->ptp_clock) {
1425         dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1426              adapter->netdev->name);
1427         adapter->ptp_flags |= IGB_PTP_ENABLED;
1428     }
1429 }
1430 
1431 /**
1432  * igb_ptp_sdp_init - utility function which inits the SDP config structs
1433  * @adapter: Board private structure.
1434  **/
1435 void igb_ptp_sdp_init(struct igb_adapter *adapter)
1436 {
1437     int i;
1438 
1439     for (i = 0; i < IGB_N_SDP; i++) {
1440         struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1441 
1442         snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1443         ppd->index = i;
1444         ppd->func = PTP_PF_NONE;
1445     }
1446 }
1447 
1448 /**
1449  * igb_ptp_suspend - Disable PTP work items and prepare for suspend
1450  * @adapter: Board private structure
1451  *
1452  * This function stops the overflow check work and PTP Tx timestamp work, and
1453  * will prepare the device for OS suspend.
1454  */
1455 void igb_ptp_suspend(struct igb_adapter *adapter)
1456 {
1457     if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1458         return;
1459 
1460     if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1461         cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1462 
1463     cancel_work_sync(&adapter->ptp_tx_work);
1464     if (adapter->ptp_tx_skb) {
1465         dev_kfree_skb_any(adapter->ptp_tx_skb);
1466         adapter->ptp_tx_skb = NULL;
1467         clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1468     }
1469 }
1470 
1471 /**
1472  * igb_ptp_stop - Disable PTP device and stop the overflow check.
1473  * @adapter: Board private structure.
1474  *
1475  * This function stops the PTP support and cancels the delayed work.
1476  **/
1477 void igb_ptp_stop(struct igb_adapter *adapter)
1478 {
1479     igb_ptp_suspend(adapter);
1480 
1481     if (adapter->ptp_clock) {
1482         ptp_clock_unregister(adapter->ptp_clock);
1483         dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1484              adapter->netdev->name);
1485         adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1486     }
1487 }
1488 
1489 /**
1490  * igb_ptp_reset - Re-enable the adapter for PTP following a reset.
1491  * @adapter: Board private structure.
1492  *
1493  * This function handles the reset work required to re-enable the PTP device.
1494  **/
1495 void igb_ptp_reset(struct igb_adapter *adapter)
1496 {
1497     struct e1000_hw *hw = &adapter->hw;
1498     unsigned long flags;
1499 
1500     /* reset the tstamp_config */
1501     igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1502 
1503     spin_lock_irqsave(&adapter->tmreg_lock, flags);
1504 
1505     switch (adapter->hw.mac.type) {
1506     case e1000_82576:
1507         /* Dial the nominal frequency. */
1508         wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1509         break;
1510     case e1000_82580:
1511     case e1000_i354:
1512     case e1000_i350:
1513     case e1000_i210:
1514     case e1000_i211:
1515         wr32(E1000_TSAUXC, 0x0);
1516         wr32(E1000_TSSDP, 0x0);
1517         wr32(E1000_TSIM,
1518              TSYNC_INTERRUPTS |
1519              (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1520         wr32(E1000_IMS, E1000_IMS_TS);
1521         break;
1522     default:
1523         /* No work to do. */
1524         goto out;
1525     }
1526 
1527     /* Re-initialize the timer. */
1528     if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1529         struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1530 
1531         igb_ptp_write_i210(adapter, &ts);
1532     } else {
1533         timecounter_init(&adapter->tc, &adapter->cc,
1534                  ktime_to_ns(ktime_get_real()));
1535     }
1536 out:
1537     spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1538 
1539     wrfl();
1540 
1541     if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1542         schedule_delayed_work(&adapter->ptp_overflow_work,
1543                       IGB_SYSTIM_OVERFLOW_PERIOD);
1544 }
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