intel/igb/e1000_phy.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2007 - 2018 Intel Corporation. */
0003
0004 #ifndef _E1000_PHY_H_
0005 #define _E1000_PHY_H_
0006
0007 enum e1000_ms_type {
0008     e1000_ms_hw_default = 0,
0009     e1000_ms_force_master,
0010     e1000_ms_force_slave,
0011     e1000_ms_auto
0012 };
0013
0014 enum e1000_smart_speed {
0015     e1000_smart_speed_default = 0,
0016     e1000_smart_speed_on,
0017     e1000_smart_speed_off
0018 };
0019
0020 s32  igb_check_downshift(struct e1000_hw *hw);
0021 s32  igb_check_reset_block(struct e1000_hw *hw);
0022 s32  igb_copper_link_setup_igp(struct e1000_hw *hw);
0023 s32  igb_copper_link_setup_m88(struct e1000_hw *hw);
0024 s32  igb_copper_link_setup_m88_gen2(struct e1000_hw *hw);
0025 s32  igb_phy_force_speed_duplex_igp(struct e1000_hw *hw);
0026 s32  igb_phy_force_speed_duplex_m88(struct e1000_hw *hw);
0027 s32  igb_get_cable_length_m88(struct e1000_hw *hw);
0028 s32  igb_get_cable_length_m88_gen2(struct e1000_hw *hw);
0029 s32  igb_get_cable_length_igp_2(struct e1000_hw *hw);
0030 s32  igb_get_phy_id(struct e1000_hw *hw);
0031 s32  igb_get_phy_info_igp(struct e1000_hw *hw);
0032 s32  igb_get_phy_info_m88(struct e1000_hw *hw);
0033 s32  igb_phy_sw_reset(struct e1000_hw *hw);
0034 s32  igb_phy_hw_reset(struct e1000_hw *hw);
0035 s32  igb_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
0036 s32  igb_set_d3_lplu_state(struct e1000_hw *hw, bool active);
0037 s32  igb_setup_copper_link(struct e1000_hw *hw);
0038 s32  igb_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
0039 s32  igb_phy_has_link(struct e1000_hw *hw, u32 iterations,
0040                 u32 usec_interval, bool *success);
0041 void igb_power_up_phy_copper(struct e1000_hw *hw);
0042 void igb_power_down_phy_copper(struct e1000_hw *hw);
0043 s32  igb_phy_init_script_igp3(struct e1000_hw *hw);
0044 s32  igb_initialize_M88E1512_phy(struct e1000_hw *hw);
0045 s32  igb_initialize_M88E1543_phy(struct e1000_hw *hw);
0046 s32  igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
0047 s32  igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
0048 s32  igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
0049 s32  igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
0050 s32  igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
0051 s32  igb_copper_link_setup_82580(struct e1000_hw *hw);
0052 s32  igb_get_phy_info_82580(struct e1000_hw *hw);
0053 s32  igb_phy_force_speed_duplex_82580(struct e1000_hw *hw);
0054 s32  igb_get_cable_length_82580(struct e1000_hw *hw);
0055 s32  igb_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data);
0056 s32  igb_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data);
0057 s32  igb_check_polarity_m88(struct e1000_hw *hw);
0058
0059 /* IGP01E1000 Specific Registers */
0060 #define IGP01E1000_PHY_PORT_CONFIG        0x10 /* Port Config */
0061 #define IGP01E1000_PHY_PORT_STATUS        0x11 /* Status */
0062 #define IGP01E1000_PHY_PORT_CTRL          0x12 /* Control */
0063 #define IGP01E1000_PHY_LINK_HEALTH        0x13 /* PHY Link Health */
0064 #define IGP02E1000_PHY_POWER_MGMT         0x19 /* Power Management */
0065 #define IGP01E1000_PHY_PAGE_SELECT        0x1F /* Page Select */
0066 #define IGP01E1000_PHY_PCS_INIT_REG       0x00B4
0067 #define IGP01E1000_PHY_POLARITY_MASK      0x0078
0068 #define IGP01E1000_PSCR_AUTO_MDIX         0x1000
0069 #define IGP01E1000_PSCR_FORCE_MDI_MDIX    0x2000 /* 0=MDI, 1=MDIX */
0070 #define IGP01E1000_PSCFR_SMART_SPEED      0x0080
0071
0072 #define I82580_ADDR_REG                   16
0073 #define I82580_CFG_REG                    22
0074 #define I82580_CFG_ASSERT_CRS_ON_TX       BIT(15)
0075 #define I82580_CFG_ENABLE_DOWNSHIFT       (3u << 10) /* auto downshift 100/10 */
0076 #define I82580_CTRL_REG                   23
0077 #define I82580_CTRL_DOWNSHIFT_MASK        (7u << 10)
0078
0079 /* 82580 specific PHY registers */
0080 #define I82580_PHY_CTRL_2            18
0081 #define I82580_PHY_LBK_CTRL          19
0082 #define I82580_PHY_STATUS_2          26
0083 #define I82580_PHY_DIAG_STATUS       31
0084
0085 /* I82580 PHY Status 2 */
0086 #define I82580_PHY_STATUS2_REV_POLARITY   0x0400
0087 #define I82580_PHY_STATUS2_MDIX           0x0800
0088 #define I82580_PHY_STATUS2_SPEED_MASK     0x0300
0089 #define I82580_PHY_STATUS2_SPEED_1000MBPS 0x0200
0090 #define I82580_PHY_STATUS2_SPEED_100MBPS  0x0100
0091
0092 /* I82580 PHY Control 2 */
0093 #define I82580_PHY_CTRL2_MANUAL_MDIX      0x0200
0094 #define I82580_PHY_CTRL2_AUTO_MDI_MDIX    0x0400
0095 #define I82580_PHY_CTRL2_MDIX_CFG_MASK    0x0600
0096
0097 /* I82580 PHY Diagnostics Status */
0098 #define I82580_DSTATUS_CABLE_LENGTH       0x03FC
0099 #define I82580_DSTATUS_CABLE_LENGTH_SHIFT 2
0100
0101 /* 82580 PHY Power Management */
0102 #define E1000_82580_PHY_POWER_MGMT  0xE14
0103 #define E1000_82580_PM_SPD      0x0001 /* Smart Power Down */
0104 #define E1000_82580_PM_D0_LPLU      0x0002 /* For D0a states */
0105 #define E1000_82580_PM_D3_LPLU      0x0004 /* For all other states */
0106 #define E1000_82580_PM_GO_LINKD     0x0020 /* Go Link Disconnect */
0107
0108 /* Enable flexible speed on link-up */
0109 #define IGP02E1000_PM_D0_LPLU             0x0002 /* For D0a states */
0110 #define IGP02E1000_PM_D3_LPLU             0x0004 /* For all other states */
0111 #define IGP01E1000_PLHR_SS_DOWNGRADE      0x8000
0112 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
0113 #define IGP01E1000_PSSR_MDIX              0x0800
0114 #define IGP01E1000_PSSR_SPEED_MASK        0xC000
0115 #define IGP01E1000_PSSR_SPEED_1000MBPS    0xC000
0116 #define IGP02E1000_PHY_CHANNEL_NUM        4
0117 #define IGP02E1000_PHY_AGC_A              0x11B1
0118 #define IGP02E1000_PHY_AGC_B              0x12B1
0119 #define IGP02E1000_PHY_AGC_C              0x14B1
0120 #define IGP02E1000_PHY_AGC_D              0x18B1
0121 #define IGP02E1000_AGC_LENGTH_SHIFT       9   /* Course - 15:13, Fine - 12:9 */
0122 #define IGP02E1000_AGC_LENGTH_MASK        0x7F
0123 #define IGP02E1000_AGC_RANGE              15
0124
0125 #define E1000_CABLE_LENGTH_UNDEFINED      0xFF
0126
0127 /* SFP modules ID memory locations */
0128 #define E1000_SFF_IDENTIFIER_OFFSET 0x00
0129 #define E1000_SFF_IDENTIFIER_SFF    0x02
0130 #define E1000_SFF_IDENTIFIER_SFP    0x03
0131
0132 #define E1000_SFF_ETH_FLAGS_OFFSET  0x06
0133 /* Flags for SFP modules compatible with ETH up to 1Gb */
0134 struct e1000_sfp_flags {
0135     u8 e1000_base_sx:1;
0136     u8 e1000_base_lx:1;
0137     u8 e1000_base_cx:1;
0138     u8 e1000_base_t:1;
0139     u8 e100_base_lx:1;
0140     u8 e100_base_fx:1;
0141     u8 e10_base_bx10:1;
0142     u8 e10_base_px:1;
0143 };
0144
0145 #endif