intel/igb/e1000_i210.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2007 - 2018 Intel Corporation. */
0003
0004 #ifndef _E1000_I210_H_
0005 #define _E1000_I210_H_
0006
0007 s32 igb_acquire_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
0008 void igb_release_swfw_sync_i210(struct e1000_hw *hw, u16 mask);
0009 s32 igb_valid_led_default_i210(struct e1000_hw *hw, u16 *data);
0010 s32 igb_read_invm_version(struct e1000_hw *hw,
0011               struct e1000_fw_version *invm_ver);
0012 s32 igb_read_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 *data);
0013 s32 igb_write_xmdio_reg(struct e1000_hw *hw, u16 addr, u8 dev_addr, u16 data);
0014 s32 igb_init_nvm_params_i210(struct e1000_hw *hw);
0015 bool igb_get_flash_presence_i210(struct e1000_hw *hw);
0016 s32 igb_pll_workaround_i210(struct e1000_hw *hw);
0017 s32 igb_get_cfg_done_i210(struct e1000_hw *hw);
0018
0019 #define E1000_STM_OPCODE        0xDB00
0020 #define E1000_EEPROM_FLASH_SIZE_WORD    0x11
0021
0022 #define INVM_DWORD_TO_RECORD_TYPE(invm_dword) \
0023     (u8)((invm_dword) & 0x7)
0024 #define INVM_DWORD_TO_WORD_ADDRESS(invm_dword) \
0025     (u8)(((invm_dword) & 0x0000FE00) >> 9)
0026 #define INVM_DWORD_TO_WORD_DATA(invm_dword) \
0027     (u16)(((invm_dword) & 0xFFFF0000) >> 16)
0028
0029 enum E1000_INVM_STRUCTURE_TYPE {
0030     E1000_INVM_UNINITIALIZED_STRUCTURE      = 0x00,
0031     E1000_INVM_WORD_AUTOLOAD_STRUCTURE      = 0x01,
0032     E1000_INVM_CSR_AUTOLOAD_STRUCTURE       = 0x02,
0033     E1000_INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE  = 0x03,
0034     E1000_INVM_RSA_KEY_SHA256_STRUCTURE     = 0x04,
0035     E1000_INVM_INVALIDATED_STRUCTURE        = 0x0F,
0036 };
0037
0038 #define E1000_INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS   8
0039 #define E1000_INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1
0040 #define E1000_INVM_ULT_BYTES_SIZE           8
0041 #define E1000_INVM_RECORD_SIZE_IN_BYTES         4
0042 #define E1000_INVM_VER_FIELD_ONE            0x1FF8
0043 #define E1000_INVM_VER_FIELD_TWO            0x7FE000
0044 #define E1000_INVM_IMGTYPE_FIELD            0x1F800000
0045
0046 #define E1000_INVM_MAJOR_MASK       0x3F0
0047 #define E1000_INVM_MINOR_MASK       0xF
0048 #define E1000_INVM_MAJOR_SHIFT      4
0049
0050 #define ID_LED_DEFAULT_I210     ((ID_LED_OFF1_ON2  << 8) | \
0051                      (ID_LED_DEF1_DEF2 <<  4) | \
0052                      (ID_LED_OFF1_OFF2))
0053 #define ID_LED_DEFAULT_I210_SERDES  ((ID_LED_DEF1_DEF2 << 8) | \
0054                      (ID_LED_DEF1_DEF2 <<  4) | \
0055                      (ID_LED_OFF1_ON2))
0056
0057 /* NVM offset defaults for i211 device */
0058 #define NVM_INIT_CTRL_2_DEFAULT_I211    0X7243
0059 #define NVM_INIT_CTRL_4_DEFAULT_I211    0x00C1
0060 #define NVM_LED_1_CFG_DEFAULT_I211  0x0184
0061 #define NVM_LED_0_2_CFG_DEFAULT_I211    0x200C
0062
0063 /* PLL Defines */
0064 #define E1000_PCI_PMCSR         0x44
0065 #define E1000_PCI_PMCSR_D3      0x03
0066 #define E1000_MAX_PLL_TRIES     5
0067 #define E1000_PHY_PLL_UNCONF        0xFF
0068 #define E1000_PHY_PLL_FREQ_PAGE     0xFC
0069 #define E1000_PHY_PLL_FREQ_REG      0x000E
0070 #define E1000_INVM_DEFAULT_AL       0x202F
0071 #define E1000_INVM_AUTOLOAD     0x0A
0072 #define E1000_INVM_PLL_WO_VAL       0x0010
0073
0074 #endif