intel/igb/e1000_hw.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2007 - 2018 Intel Corporation. */
0003
0004 #ifndef _E1000_IGB_HW_H_
0005 #define _E1000_IGB_HW_H_
0006
0007 #include <linux/types.h>
0008 #include <linux/delay.h>
0009 #include <linux/io.h>
0010 #include <linux/netdevice.h>
0011
0012 #include "e1000_regs.h"
0013 #include "e1000_defines.h"
0014
0015 struct e1000_hw;
0016
0017 #define E1000_DEV_ID_82576          0x10C9
0018 #define E1000_DEV_ID_82576_FIBER        0x10E6
0019 #define E1000_DEV_ID_82576_SERDES       0x10E7
0020 #define E1000_DEV_ID_82576_QUAD_COPPER      0x10E8
0021 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2  0x1526
0022 #define E1000_DEV_ID_82576_NS           0x150A
0023 #define E1000_DEV_ID_82576_NS_SERDES        0x1518
0024 #define E1000_DEV_ID_82576_SERDES_QUAD      0x150D
0025 #define E1000_DEV_ID_82575EB_COPPER     0x10A7
0026 #define E1000_DEV_ID_82575EB_FIBER_SERDES   0x10A9
0027 #define E1000_DEV_ID_82575GB_QUAD_COPPER    0x10D6
0028 #define E1000_DEV_ID_82580_COPPER       0x150E
0029 #define E1000_DEV_ID_82580_FIBER        0x150F
0030 #define E1000_DEV_ID_82580_SERDES       0x1510
0031 #define E1000_DEV_ID_82580_SGMII        0x1511
0032 #define E1000_DEV_ID_82580_COPPER_DUAL      0x1516
0033 #define E1000_DEV_ID_82580_QUAD_FIBER       0x1527
0034 #define E1000_DEV_ID_DH89XXCC_SGMII     0x0438
0035 #define E1000_DEV_ID_DH89XXCC_SERDES        0x043A
0036 #define E1000_DEV_ID_DH89XXCC_BACKPLANE     0x043C
0037 #define E1000_DEV_ID_DH89XXCC_SFP       0x0440
0038 #define E1000_DEV_ID_I350_COPPER        0x1521
0039 #define E1000_DEV_ID_I350_FIBER         0x1522
0040 #define E1000_DEV_ID_I350_SERDES        0x1523
0041 #define E1000_DEV_ID_I350_SGMII         0x1524
0042 #define E1000_DEV_ID_I210_COPPER        0x1533
0043 #define E1000_DEV_ID_I210_FIBER         0x1536
0044 #define E1000_DEV_ID_I210_SERDES        0x1537
0045 #define E1000_DEV_ID_I210_SGMII         0x1538
0046 #define E1000_DEV_ID_I210_COPPER_FLASHLESS  0x157B
0047 #define E1000_DEV_ID_I210_SERDES_FLASHLESS  0x157C
0048 #define E1000_DEV_ID_I211_COPPER        0x1539
0049 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS   0x1F40
0050 #define E1000_DEV_ID_I354_SGMII         0x1F41
0051 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45
0052
0053 #define E1000_REVISION_2 2
0054 #define E1000_REVISION_4 4
0055
0056 #define E1000_FUNC_0     0
0057 #define E1000_FUNC_1     1
0058 #define E1000_FUNC_2     2
0059 #define E1000_FUNC_3     3
0060
0061 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0   0
0062 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1   3
0063 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2   6
0064 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3   9
0065
0066 enum e1000_mac_type {
0067     e1000_undefined = 0,
0068     e1000_82575,
0069     e1000_82576,
0070     e1000_82580,
0071     e1000_i350,
0072     e1000_i354,
0073     e1000_i210,
0074     e1000_i211,
0075     e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
0076 };
0077
0078 enum e1000_media_type {
0079     e1000_media_type_unknown = 0,
0080     e1000_media_type_copper = 1,
0081     e1000_media_type_fiber = 2,
0082     e1000_media_type_internal_serdes = 3,
0083     e1000_num_media_types
0084 };
0085
0086 enum e1000_nvm_type {
0087     e1000_nvm_unknown = 0,
0088     e1000_nvm_none,
0089     e1000_nvm_eeprom_spi,
0090     e1000_nvm_flash_hw,
0091     e1000_nvm_invm,
0092     e1000_nvm_flash_sw
0093 };
0094
0095 enum e1000_nvm_override {
0096     e1000_nvm_override_none = 0,
0097     e1000_nvm_override_spi_small,
0098     e1000_nvm_override_spi_large,
0099 };
0100
0101 enum e1000_phy_type {
0102     e1000_phy_unknown = 0,
0103     e1000_phy_none,
0104     e1000_phy_m88,
0105     e1000_phy_igp,
0106     e1000_phy_igp_2,
0107     e1000_phy_gg82563,
0108     e1000_phy_igp_3,
0109     e1000_phy_ife,
0110     e1000_phy_82580,
0111     e1000_phy_i210,
0112     e1000_phy_bcm54616,
0113 };
0114
0115 enum e1000_bus_type {
0116     e1000_bus_type_unknown = 0,
0117     e1000_bus_type_pci,
0118     e1000_bus_type_pcix,
0119     e1000_bus_type_pci_express,
0120     e1000_bus_type_reserved
0121 };
0122
0123 enum e1000_bus_speed {
0124     e1000_bus_speed_unknown = 0,
0125     e1000_bus_speed_33,
0126     e1000_bus_speed_66,
0127     e1000_bus_speed_100,
0128     e1000_bus_speed_120,
0129     e1000_bus_speed_133,
0130     e1000_bus_speed_2500,
0131     e1000_bus_speed_5000,
0132     e1000_bus_speed_reserved
0133 };
0134
0135 enum e1000_bus_width {
0136     e1000_bus_width_unknown = 0,
0137     e1000_bus_width_pcie_x1,
0138     e1000_bus_width_pcie_x2,
0139     e1000_bus_width_pcie_x4 = 4,
0140     e1000_bus_width_pcie_x8 = 8,
0141     e1000_bus_width_32,
0142     e1000_bus_width_64,
0143     e1000_bus_width_reserved
0144 };
0145
0146 enum e1000_1000t_rx_status {
0147     e1000_1000t_rx_status_not_ok = 0,
0148     e1000_1000t_rx_status_ok,
0149     e1000_1000t_rx_status_undefined = 0xFF
0150 };
0151
0152 enum e1000_rev_polarity {
0153     e1000_rev_polarity_normal = 0,
0154     e1000_rev_polarity_reversed,
0155     e1000_rev_polarity_undefined = 0xFF
0156 };
0157
0158 enum e1000_fc_mode {
0159     e1000_fc_none = 0,
0160     e1000_fc_rx_pause,
0161     e1000_fc_tx_pause,
0162     e1000_fc_full,
0163     e1000_fc_default = 0xFF
0164 };
0165
0166 /* Statistics counters collected by the MAC */
0167 struct e1000_hw_stats {
0168     u64 crcerrs;
0169     u64 algnerrc;
0170     u64 symerrs;
0171     u64 rxerrc;
0172     u64 mpc;
0173     u64 scc;
0174     u64 ecol;
0175     u64 mcc;
0176     u64 latecol;
0177     u64 colc;
0178     u64 dc;
0179     u64 tncrs;
0180     u64 sec;
0181     u64 cexterr;
0182     u64 rlec;
0183     u64 xonrxc;
0184     u64 xontxc;
0185     u64 xoffrxc;
0186     u64 xofftxc;
0187     u64 fcruc;
0188     u64 prc64;
0189     u64 prc127;
0190     u64 prc255;
0191     u64 prc511;
0192     u64 prc1023;
0193     u64 prc1522;
0194     u64 gprc;
0195     u64 bprc;
0196     u64 mprc;
0197     u64 gptc;
0198     u64 gorc;
0199     u64 gotc;
0200     u64 rnbc;
0201     u64 ruc;
0202     u64 rfc;
0203     u64 roc;
0204     u64 rjc;
0205     u64 mgprc;
0206     u64 mgpdc;
0207     u64 mgptc;
0208     u64 tor;
0209     u64 tot;
0210     u64 tpr;
0211     u64 tpt;
0212     u64 ptc64;
0213     u64 ptc127;
0214     u64 ptc255;
0215     u64 ptc511;
0216     u64 ptc1023;
0217     u64 ptc1522;
0218     u64 mptc;
0219     u64 bptc;
0220     u64 tsctc;
0221     u64 tsctfc;
0222     u64 iac;
0223     u64 icrxptc;
0224     u64 icrxatc;
0225     u64 ictxptc;
0226     u64 ictxatc;
0227     u64 ictxqec;
0228     u64 ictxqmtc;
0229     u64 icrxdmtc;
0230     u64 icrxoc;
0231     u64 cbtmpc;
0232     u64 htdpmc;
0233     u64 cbrdpc;
0234     u64 cbrmpc;
0235     u64 rpthc;
0236     u64 hgptc;
0237     u64 htcbdpc;
0238     u64 hgorc;
0239     u64 hgotc;
0240     u64 lenerrs;
0241     u64 scvpc;
0242     u64 hrmpc;
0243     u64 doosync;
0244     u64 o2bgptc;
0245     u64 o2bspc;
0246     u64 b2ospc;
0247     u64 b2ogprc;
0248 };
0249
0250 struct e1000_host_mng_dhcp_cookie {
0251     u32 signature;
0252     u8  status;
0253     u8  reserved0;
0254     u16 vlan_id;
0255     u32 reserved1;
0256     u16 reserved2;
0257     u8  reserved3;
0258     u8  checksum;
0259 };
0260
0261 /* Host Interface "Rev 1" */
0262 struct e1000_host_command_header {
0263     u8 command_id;
0264     u8 command_length;
0265     u8 command_options;
0266     u8 checksum;
0267 };
0268
0269 #define E1000_HI_MAX_DATA_LENGTH     252
0270 struct e1000_host_command_info {
0271     struct e1000_host_command_header command_header;
0272     u8 command_data[E1000_HI_MAX_DATA_LENGTH];
0273 };
0274
0275 /* Host Interface "Rev 2" */
0276 struct e1000_host_mng_command_header {
0277     u8  command_id;
0278     u8  checksum;
0279     u16 reserved1;
0280     u16 reserved2;
0281     u16 command_length;
0282 };
0283
0284 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
0285 struct e1000_host_mng_command_info {
0286     struct e1000_host_mng_command_header command_header;
0287     u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
0288 };
0289
0290 #include "e1000_mac.h"
0291 #include "e1000_phy.h"
0292 #include "e1000_nvm.h"
0293 #include "e1000_mbx.h"
0294
0295 struct e1000_mac_operations {
0296     s32 (*check_for_link)(struct e1000_hw *);
0297     s32 (*reset_hw)(struct e1000_hw *);
0298     s32 (*init_hw)(struct e1000_hw *);
0299     bool (*check_mng_mode)(struct e1000_hw *);
0300     s32 (*setup_physical_interface)(struct e1000_hw *);
0301     void (*rar_set)(struct e1000_hw *, u8 *, u32);
0302     s32 (*read_mac_addr)(struct e1000_hw *);
0303     s32 (*get_speed_and_duplex)(struct e1000_hw *, u16 *, u16 *);
0304     s32 (*acquire_swfw_sync)(struct e1000_hw *, u16);
0305     void (*release_swfw_sync)(struct e1000_hw *, u16);
0306 #ifdef CONFIG_IGB_HWMON
0307     s32 (*get_thermal_sensor_data)(struct e1000_hw *);
0308     s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
0309 #endif
0310     void (*write_vfta)(struct e1000_hw *, u32, u32);
0311 };
0312
0313 struct e1000_phy_operations {
0314     s32 (*acquire)(struct e1000_hw *);
0315     s32 (*check_polarity)(struct e1000_hw *);
0316     s32 (*check_reset_block)(struct e1000_hw *);
0317     s32 (*force_speed_duplex)(struct e1000_hw *);
0318     s32 (*get_cfg_done)(struct e1000_hw *hw);
0319     s32 (*get_cable_length)(struct e1000_hw *);
0320     s32 (*get_phy_info)(struct e1000_hw *);
0321     s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
0322     void (*release)(struct e1000_hw *);
0323     s32 (*reset)(struct e1000_hw *);
0324     s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
0325     s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
0326     s32 (*write_reg)(struct e1000_hw *, u32, u16);
0327     s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
0328     s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
0329 };
0330
0331 struct e1000_nvm_operations {
0332     s32 (*acquire)(struct e1000_hw *);
0333     s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
0334     void (*release)(struct e1000_hw *);
0335     s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
0336     s32 (*update)(struct e1000_hw *);
0337     s32 (*validate)(struct e1000_hw *);
0338     s32 (*valid_led_default)(struct e1000_hw *, u16 *);
0339 };
0340
0341 #define E1000_MAX_SENSORS       3
0342
0343 struct e1000_thermal_diode_data {
0344     u8 location;
0345     u8 temp;
0346     u8 caution_thresh;
0347     u8 max_op_thresh;
0348 };
0349
0350 struct e1000_thermal_sensor_data {
0351     struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
0352 };
0353
0354 struct e1000_info {
0355     s32 (*get_invariants)(struct e1000_hw *);
0356     struct e1000_mac_operations *mac_ops;
0357     const struct e1000_phy_operations *phy_ops;
0358     struct e1000_nvm_operations *nvm_ops;
0359 };
0360
0361 extern const struct e1000_info e1000_82575_info;
0362
0363 struct e1000_mac_info {
0364     struct e1000_mac_operations ops;
0365
0366     u8 addr[6];
0367     u8 perm_addr[6];
0368
0369     enum e1000_mac_type type;
0370
0371     u32 ledctl_default;
0372     u32 ledctl_mode1;
0373     u32 ledctl_mode2;
0374     u32 mc_filter_type;
0375     u32 txcw;
0376
0377     u16 mta_reg_count;
0378     u16 uta_reg_count;
0379
0380     /* Maximum size of the MTA register table in all supported adapters */
0381     #define MAX_MTA_REG 128
0382     u32 mta_shadow[MAX_MTA_REG];
0383     u16 rar_entry_count;
0384
0385     u8  forced_speed_duplex;
0386
0387     bool adaptive_ifs;
0388     bool arc_subsystem_valid;
0389     bool asf_firmware_present;
0390     bool autoneg;
0391     bool autoneg_failed;
0392     bool disable_hw_init_bits;
0393     bool get_link_status;
0394     bool ifs_params_forced;
0395     bool in_ifs_mode;
0396     bool report_tx_early;
0397     bool serdes_has_link;
0398     bool tx_pkt_filtering;
0399     struct e1000_thermal_sensor_data thermal_sensor_data;
0400 };
0401
0402 struct e1000_phy_info {
0403     struct e1000_phy_operations ops;
0404
0405     enum e1000_phy_type type;
0406
0407     enum e1000_1000t_rx_status local_rx;
0408     enum e1000_1000t_rx_status remote_rx;
0409     enum e1000_ms_type ms_type;
0410     enum e1000_ms_type original_ms_type;
0411     enum e1000_rev_polarity cable_polarity;
0412     enum e1000_smart_speed smart_speed;
0413
0414     u32 addr;
0415     u32 id;
0416     u32 reset_delay_us; /* in usec */
0417     u32 revision;
0418
0419     enum e1000_media_type media_type;
0420
0421     u16 autoneg_advertised;
0422     u16 autoneg_mask;
0423     u16 cable_length;
0424     u16 max_cable_length;
0425     u16 min_cable_length;
0426     u16 pair_length[4];
0427
0428     u8 mdix;
0429
0430     bool disable_polarity_correction;
0431     bool is_mdix;
0432     bool polarity_correction;
0433     bool reset_disable;
0434     bool speed_downgraded;
0435     bool autoneg_wait_to_complete;
0436 };
0437
0438 struct e1000_nvm_info {
0439     struct e1000_nvm_operations ops;
0440     enum e1000_nvm_type type;
0441     enum e1000_nvm_override override;
0442
0443     u32 flash_bank_size;
0444     u32 flash_base_addr;
0445
0446     u16 word_size;
0447     u16 delay_usec;
0448     u16 address_bits;
0449     u16 opcode_bits;
0450     u16 page_size;
0451 };
0452
0453 struct e1000_bus_info {
0454     enum e1000_bus_type type;
0455     enum e1000_bus_speed speed;
0456     enum e1000_bus_width width;
0457
0458     u32 snoop;
0459
0460     u16 func;
0461     u16 pci_cmd_word;
0462 };
0463
0464 struct e1000_fc_info {
0465     u32 high_water;     /* Flow control high-water mark */
0466     u32 low_water;      /* Flow control low-water mark */
0467     u16 pause_time;     /* Flow control pause timer */
0468     bool send_xon;      /* Flow control send XON */
0469     bool strict_ieee;   /* Strict IEEE mode */
0470     enum e1000_fc_mode current_mode; /* Type of flow control */
0471     enum e1000_fc_mode requested_mode;
0472 };
0473
0474 struct e1000_mbx_operations {
0475     s32 (*init_params)(struct e1000_hw *hw);
0476     s32 (*read)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id,
0477             bool unlock);
0478     s32 (*write)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id);
0479     s32 (*read_posted)(struct e1000_hw *hw, u32 *msg, u16 size, u16 mbx_id);
0480     s32 (*write_posted)(struct e1000_hw *hw, u32 *msg, u16 size,
0481                 u16 mbx_id);
0482     s32 (*check_for_msg)(struct e1000_hw *hw, u16 mbx_id);
0483     s32 (*check_for_ack)(struct e1000_hw *hw, u16 mbx_id);
0484     s32 (*check_for_rst)(struct e1000_hw *hw, u16 mbx_id);
0485     s32 (*unlock)(struct e1000_hw *hw, u16 mbx_id);
0486 };
0487
0488 struct e1000_mbx_stats {
0489     u32 msgs_tx;
0490     u32 msgs_rx;
0491
0492     u32 acks;
0493     u32 reqs;
0494     u32 rsts;
0495 };
0496
0497 struct e1000_mbx_info {
0498     struct e1000_mbx_operations ops;
0499     struct e1000_mbx_stats stats;
0500     u32 timeout;
0501     u32 usec_delay;
0502     u16 size;
0503 };
0504
0505 struct e1000_dev_spec_82575 {
0506     bool sgmii_active;
0507     bool global_device_reset;
0508     bool eee_disable;
0509     bool clear_semaphore_once;
0510     struct e1000_sfp_flags eth_flags;
0511     bool module_plugged;
0512     u8 media_port;
0513     bool media_changed;
0514     bool mas_capable;
0515 };
0516
0517 struct e1000_hw {
0518     void *back;
0519
0520     u8 __iomem *hw_addr;
0521     u8 __iomem *flash_address;
0522     unsigned long io_base;
0523
0524     struct e1000_mac_info  mac;
0525     struct e1000_fc_info   fc;
0526     struct e1000_phy_info  phy;
0527     struct e1000_nvm_info  nvm;
0528     struct e1000_bus_info  bus;
0529     struct e1000_mbx_info mbx;
0530     struct e1000_host_mng_dhcp_cookie mng_cookie;
0531
0532     union {
0533         struct e1000_dev_spec_82575 _82575;
0534     } dev_spec;
0535
0536     u16 device_id;
0537     u16 subsystem_vendor_id;
0538     u16 subsystem_device_id;
0539     u16 vendor_id;
0540
0541     u8  revision_id;
0542 };
0543
0544 struct net_device *igb_get_hw_dev(struct e1000_hw *hw);
0545 #define hw_dbg(format, arg...) \
0546     netdev_dbg(igb_get_hw_dev(hw), format, ##arg)
0547
0548 /* These functions must be implemented by drivers */
0549 s32 igb_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
0550 s32 igb_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
0551
0552 void igb_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
0553 void igb_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
0554 #endif /* _E1000_IGB_HW_H_ */