intel/ice/ice_sched.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2018, Intel Corporation. */
0003
0004 #ifndef _ICE_SCHED_H_
0005 #define _ICE_SCHED_H_
0006
0007 #include "ice_common.h"
0008
0009 #define ICE_QGRP_LAYER_OFFSET   2
0010 #define ICE_VSI_LAYER_OFFSET    4
0011 #define ICE_AGG_LAYER_OFFSET    6
0012 #define ICE_SCHED_INVAL_LAYER_NUM   0xFF
0013 /* Burst size is a 12 bits register that is configured while creating the RL
0014  * profile(s). MSB is a granularity bit and tells the granularity type
0015  * 0 - LSB bits are in 64 bytes granularity
0016  * 1 - LSB bits are in 1K bytes granularity
0017  */
0018 #define ICE_64_BYTE_GRANULARITY         0
0019 #define ICE_KBYTE_GRANULARITY           BIT(11)
0020 #define ICE_MIN_BURST_SIZE_ALLOWED      64 /* In Bytes */
0021 #define ICE_MAX_BURST_SIZE_ALLOWED \
0022     ((BIT(11) - 1) * 1024) /* In Bytes */
0023 #define ICE_MAX_BURST_SIZE_64_BYTE_GRANULARITY \
0024     ((BIT(11) - 1) * 64) /* In Bytes */
0025 #define ICE_MAX_BURST_SIZE_KBYTE_GRANULARITY    ICE_MAX_BURST_SIZE_ALLOWED
0026
0027 #define ICE_RL_PROF_ACCURACY_BYTES 128
0028 #define ICE_RL_PROF_MULTIPLIER 10000
0029 #define ICE_RL_PROF_TS_MULTIPLIER 32
0030 #define ICE_RL_PROF_FRACTION 512
0031
0032 #define ICE_PSM_CLK_367MHZ_IN_HZ 367647059
0033 #define ICE_PSM_CLK_416MHZ_IN_HZ 416666667
0034 #define ICE_PSM_CLK_446MHZ_IN_HZ 446428571
0035 #define ICE_PSM_CLK_390MHZ_IN_HZ 390625000
0036
0037 /* BW rate limit profile parameters list entry along
0038  * with bandwidth maintained per layer in port info
0039  */
0040 struct ice_aqc_rl_profile_info {
0041     struct ice_aqc_rl_profile_elem profile;
0042     struct list_head list_entry;
0043     u32 bw;         /* requested */
0044     u16 prof_id_ref;    /* profile ID to node association ref count */
0045 };
0046
0047 struct ice_sched_agg_vsi_info {
0048     struct list_head list_entry;
0049     DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
0050     u16 vsi_handle;
0051     /* save aggregator VSI TC bitmap */
0052     DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
0053 };
0054
0055 struct ice_sched_agg_info {
0056     struct list_head agg_vsi_list;
0057     struct list_head list_entry;
0058     DECLARE_BITMAP(tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
0059     u32 agg_id;
0060     enum ice_agg_type agg_type;
0061     /* bw_t_info saves aggregator BW information */
0062     struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
0063     /* save aggregator TC bitmap */
0064     DECLARE_BITMAP(replay_tc_bitmap, ICE_MAX_TRAFFIC_CLASS);
0065 };
0066
0067 /* FW AQ command calls */
0068 int
0069 ice_aq_query_sched_elems(struct ice_hw *hw, u16 elems_req,
0070              struct ice_aqc_txsched_elem_data *buf, u16 buf_size,
0071              u16 *elems_ret, struct ice_sq_cd *cd);
0072 int ice_sched_init_port(struct ice_port_info *pi);
0073 int ice_sched_query_res_alloc(struct ice_hw *hw);
0074 void ice_sched_get_psm_clk_freq(struct ice_hw *hw);
0075
0076 void ice_sched_clear_port(struct ice_port_info *pi);
0077 void ice_sched_cleanup_all(struct ice_hw *hw);
0078 void ice_sched_clear_agg(struct ice_hw *hw);
0079
0080 struct ice_sched_node *
0081 ice_sched_find_node_by_teid(struct ice_sched_node *start_node, u32 teid);
0082 int
0083 ice_sched_add_node(struct ice_port_info *pi, u8 layer,
0084            struct ice_aqc_txsched_elem_data *info);
0085 void ice_free_sched_node(struct ice_port_info *pi, struct ice_sched_node *node);
0086 struct ice_sched_node *ice_sched_get_tc_node(struct ice_port_info *pi, u8 tc);
0087 struct ice_sched_node *
0088 ice_sched_get_free_qparent(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
0089                u8 owner);
0090 int
0091 ice_sched_cfg_vsi(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u16 maxqs,
0092           u8 owner, bool enable);
0093 int ice_rm_vsi_lan_cfg(struct ice_port_info *pi, u16 vsi_handle);
0094 int ice_rm_vsi_rdma_cfg(struct ice_port_info *pi, u16 vsi_handle);
0095
0096 /* Tx scheduler rate limiter functions */
0097 int
0098 ice_cfg_agg(struct ice_port_info *pi, u32 agg_id,
0099         enum ice_agg_type agg_type, u8 tc_bitmap);
0100 int
0101 ice_move_vsi_to_agg(struct ice_port_info *pi, u32 agg_id, u16 vsi_handle,
0102             u8 tc_bitmap);
0103 int
0104 ice_cfg_q_bw_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
0105          u16 q_handle, enum ice_rl_type rl_type, u32 bw);
0106 int
0107 ice_cfg_q_bw_dflt_lmt(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
0108               u16 q_handle, enum ice_rl_type rl_type);
0109 int
0110 ice_cfg_vsi_bw_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
0111               enum ice_rl_type rl_type, u32 bw);
0112 int
0113 ice_cfg_vsi_bw_dflt_lmt_per_tc(struct ice_port_info *pi, u16 vsi_handle, u8 tc,
0114                    enum ice_rl_type rl_type);
0115 int
0116 ice_sched_set_node_bw_lmt_per_tc(struct ice_port_info *pi, u32 id,
0117                  enum ice_agg_type agg_type, u8 tc,
0118                  enum ice_rl_type rl_type, u32 bw);
0119 int ice_cfg_rl_burst_size(struct ice_hw *hw, u32 bytes);
0120 void ice_sched_replay_agg_vsi_preinit(struct ice_hw *hw);
0121 void ice_sched_replay_agg(struct ice_hw *hw);
0122 int ice_replay_vsi_agg(struct ice_hw *hw, u16 vsi_handle);
0123 int ice_sched_replay_q_bw(struct ice_port_info *pi, struct ice_q_ctx *q_ctx);
0124 #endif /* _ICE_SCHED_H_ */