intel/ice/ice_ptp_hw.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2021, Intel Corporation. */
0003
0004 #ifndef _ICE_PTP_HW_H_
0005 #define _ICE_PTP_HW_H_
0006
0007 enum ice_ptp_tmr_cmd {
0008     INIT_TIME,
0009     INIT_INCVAL,
0010     ADJ_TIME,
0011     ADJ_TIME_AT_TIME,
0012     READ_TIME
0013 };
0014
0015 enum ice_ptp_serdes {
0016     ICE_PTP_SERDES_1G,
0017     ICE_PTP_SERDES_10G,
0018     ICE_PTP_SERDES_25G,
0019     ICE_PTP_SERDES_40G,
0020     ICE_PTP_SERDES_50G,
0021     ICE_PTP_SERDES_100G
0022 };
0023
0024 enum ice_ptp_link_spd {
0025     ICE_PTP_LNK_SPD_1G,
0026     ICE_PTP_LNK_SPD_10G,
0027     ICE_PTP_LNK_SPD_25G,
0028     ICE_PTP_LNK_SPD_25G_RS,
0029     ICE_PTP_LNK_SPD_40G,
0030     ICE_PTP_LNK_SPD_50G,
0031     ICE_PTP_LNK_SPD_50G_RS,
0032     ICE_PTP_LNK_SPD_100G_RS,
0033     NUM_ICE_PTP_LNK_SPD /* Must be last */
0034 };
0035
0036 enum ice_ptp_fec_mode {
0037     ICE_PTP_FEC_MODE_NONE,
0038     ICE_PTP_FEC_MODE_CLAUSE74,
0039     ICE_PTP_FEC_MODE_RS_FEC
0040 };
0041
0042 /**
0043  * struct ice_time_ref_info_e822
0044  * @pll_freq: Frequency of PLL that drives timer ticks in Hz
0045  * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
0046  * @pps_delay: propagation delay of the PPS output signal
0047  *
0048  * Characteristic information for the various TIME_REF sources possible in the
0049  * E822 devices
0050  */
0051 struct ice_time_ref_info_e822 {
0052     u64 pll_freq;
0053     u64 nominal_incval;
0054     u8 pps_delay;
0055 };
0056
0057 /**
0058  * struct ice_vernier_info_e822
0059  * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
0060  * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
0061  * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
0062  * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
0063  * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
0064  * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
0065  * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
0066  * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
0067  * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
0068  * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
0069  * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
0070  *
0071  * Table of constants used during as part of the Vernier calibration of the Tx
0072  * and Rx timestamps. This includes frequency values used to compute TUs per
0073  * PAR/PCS clock cycle, and static delay values measured during hardware
0074  * design.
0075  *
0076  * Note that some values are not used for all link speeds, and the
0077  * P_REG_DESK_PAR* registers may represent different clock markers at
0078  * different link speeds, either the deskew marker for multi-lane link speeds
0079  * or the Reed Solomon gearbox marker for RS-FEC.
0080  */
0081 struct ice_vernier_info_e822 {
0082     u32 tx_par_clk;
0083     u32 rx_par_clk;
0084     u32 tx_pcs_clk;
0085     u32 rx_pcs_clk;
0086     u32 tx_desk_rsgb_par;
0087     u32 rx_desk_rsgb_par;
0088     u32 tx_desk_rsgb_pcs;
0089     u32 rx_desk_rsgb_pcs;
0090     u32 tx_fixed_delay;
0091     u32 pmd_adj_divisor;
0092     u32 rx_fixed_delay;
0093 };
0094
0095 /**
0096  * struct ice_cgu_pll_params_e822
0097  * @refclk_pre_div: Reference clock pre-divisor
0098  * @feedback_div: Feedback divisor
0099  * @frac_n_div: Fractional divisor
0100  * @post_pll_div: Post PLL divisor
0101  *
0102  * Clock Generation Unit parameters used to program the PLL based on the
0103  * selected TIME_REF frequency.
0104  */
0105 struct ice_cgu_pll_params_e822 {
0106     u32 refclk_pre_div;
0107     u32 feedback_div;
0108     u32 frac_n_div;
0109     u32 post_pll_div;
0110 };
0111
0112 extern const struct
0113 ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
0114
0115 /* Table of constants related to possible TIME_REF sources */
0116 extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
0117
0118 /* Table of constants for Vernier calibration on E822 */
0119 extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
0120
0121 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
0122  * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
0123  */
0124 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
0125
0126 /* Device agnostic functions */
0127 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
0128 bool ice_ptp_lock(struct ice_hw *hw);
0129 void ice_ptp_unlock(struct ice_hw *hw);
0130 int ice_ptp_init_time(struct ice_hw *hw, u64 time);
0131 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
0132 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
0133 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
0134 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
0135 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
0136 int ice_ptp_init_phc(struct ice_hw *hw);
0137
0138 /* E822 family functions */
0139 int ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
0140 int ice_write_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 val);
0141 int ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
0142 int ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
0143 int ice_ptp_prep_port_adj_e822(struct ice_hw *hw, u8 port, s64 time);
0144
0145 /**
0146  * ice_e822_time_ref - Get the current TIME_REF from capabilities
0147  * @hw: pointer to the HW structure
0148  *
0149  * Returns the current TIME_REF from the capabilities structure.
0150  */
0151 static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)
0152 {
0153     return hw->func_caps.ts_func_info.time_ref;
0154 }
0155
0156 /**
0157  * ice_set_e822_time_ref - Set new TIME_REF
0158  * @hw: pointer to the HW structure
0159  * @time_ref: new TIME_REF to set
0160  *
0161  * Update the TIME_REF in the capabilities structure in response to some
0162  * change, such as an update to the CGU registers.
0163  */
0164 static inline void
0165 ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
0166 {
0167     hw->func_caps.ts_func_info.time_ref = time_ref;
0168 }
0169
0170 static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
0171 {
0172     return e822_time_ref[time_ref].pll_freq;
0173 }
0174
0175 static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)
0176 {
0177     return e822_time_ref[time_ref].nominal_incval;
0178 }
0179
0180 static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)
0181 {
0182     return e822_time_ref[time_ref].pps_delay;
0183 }
0184
0185 /* E822 Vernier calibration functions */
0186 int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
0187 int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port, bool bypass);
0188 int ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);
0189
0190 /* E810 family functions */
0191 int ice_ptp_init_phy_e810(struct ice_hw *hw);
0192 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
0193 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
0194 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
0195 bool ice_is_pca9575_present(struct ice_hw *hw);
0196
0197 #define PFTSYN_SEM_BYTES    4
0198
0199 #define ICE_PTP_CLOCK_INDEX_0   0x00
0200 #define ICE_PTP_CLOCK_INDEX_1   0x01
0201
0202 /* PHY timer commands */
0203 #define SEL_CPK_SRC 8
0204 #define SEL_PHY_SRC 3
0205
0206 /* Time Sync command Definitions */
0207 #define GLTSYN_CMD_INIT_TIME        BIT(0)
0208 #define GLTSYN_CMD_INIT_INCVAL      BIT(1)
0209 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
0210 #define GLTSYN_CMD_ADJ_TIME     BIT(2)
0211 #define GLTSYN_CMD_ADJ_INIT_TIME    (BIT(2) | BIT(3))
0212 #define GLTSYN_CMD_READ_TIME        BIT(7)
0213
0214 /* PHY port Time Sync command definitions */
0215 #define PHY_CMD_INIT_TIME       BIT(0)
0216 #define PHY_CMD_INIT_INCVAL     BIT(1)
0217 #define PHY_CMD_ADJ_TIME        (BIT(0) | BIT(1))
0218 #define PHY_CMD_ADJ_TIME_AT_TIME    (BIT(0) | BIT(2))
0219 #define PHY_CMD_READ_TIME       (BIT(0) | BIT(1) | BIT(2))
0220
0221 #define TS_CMD_MASK_E810        0xFF
0222 #define TS_CMD_MASK         0xF
0223 #define SYNC_EXEC_CMD           0x3
0224
0225 /* Macros to derive port low and high addresses on both quads */
0226 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
0227 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
0228 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
0229 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
0230
0231 /* PHY QUAD register base addresses */
0232 #define Q_0_BASE            0x94000
0233 #define Q_1_BASE            0x114000
0234
0235 /* Timestamp memory reset registers */
0236 #define Q_REG_TS_CTRL           0x618
0237 #define Q_REG_TS_CTRL_S         0
0238 #define Q_REG_TS_CTRL_M         BIT(0)
0239
0240 /* Timestamp availability status registers */
0241 #define Q_REG_TX_MEMORY_STATUS_L    0xCF0
0242 #define Q_REG_TX_MEMORY_STATUS_U    0xCF4
0243
0244 /* Tx FIFO status registers */
0245 #define Q_REG_FIFO23_STATUS     0xCF8
0246 #define Q_REG_FIFO01_STATUS     0xCFC
0247 #define Q_REG_FIFO02_S          0
0248 #define Q_REG_FIFO02_M          ICE_M(0x3FF, 0)
0249 #define Q_REG_FIFO13_S          10
0250 #define Q_REG_FIFO13_M          ICE_M(0x3FF, 10)
0251
0252 /* Interrupt control Config registers */
0253 #define Q_REG_TX_MEM_GBL_CFG        0xC08
0254 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S    0
0255 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M    BIT(0)
0256 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S  1
0257 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M  ICE_M(0xFF, 1)
0258 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
0259 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
0260 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
0261 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
0262
0263 /* Tx Timestamp data registers */
0264 #define Q_REG_TX_MEMORY_BANK_START  0xA00
0265
0266 /* PHY port register base addresses */
0267 #define P_0_BASE            0x80000
0268 #define P_4_BASE            0x106000
0269
0270 /* Timestamp init registers */
0271 #define P_REG_RX_TIMER_INC_PRE_L    0x46C
0272 #define P_REG_RX_TIMER_INC_PRE_U    0x470
0273 #define P_REG_TX_TIMER_INC_PRE_L    0x44C
0274 #define P_REG_TX_TIMER_INC_PRE_U    0x450
0275
0276 /* Timestamp match and adjust target registers */
0277 #define P_REG_RX_TIMER_CNT_ADJ_L    0x474
0278 #define P_REG_RX_TIMER_CNT_ADJ_U    0x478
0279 #define P_REG_TX_TIMER_CNT_ADJ_L    0x454
0280 #define P_REG_TX_TIMER_CNT_ADJ_U    0x458
0281
0282 /* Timestamp capture registers */
0283 #define P_REG_RX_CAPTURE_L      0x4D8
0284 #define P_REG_RX_CAPTURE_U      0x4DC
0285 #define P_REG_TX_CAPTURE_L      0x4B4
0286 #define P_REG_TX_CAPTURE_U      0x4B8
0287
0288 /* Timestamp PHY incval registers */
0289 #define P_REG_TIMETUS_L         0x410
0290 #define P_REG_TIMETUS_U         0x414
0291
0292 #define P_REG_40B_LOW_M         0xFF
0293 #define P_REG_40B_HIGH_S        8
0294
0295 /* PHY window length registers */
0296 #define P_REG_WL            0x40C
0297
0298 #define PTP_VERNIER_WL          0x111ed
0299
0300 /* PHY start registers */
0301 #define P_REG_PS            0x408
0302 #define P_REG_PS_START_S        0
0303 #define P_REG_PS_START_M        BIT(0)
0304 #define P_REG_PS_BYPASS_MODE_S      1
0305 #define P_REG_PS_BYPASS_MODE_M      BIT(1)
0306 #define P_REG_PS_ENA_CLK_S      2
0307 #define P_REG_PS_ENA_CLK_M      BIT(2)
0308 #define P_REG_PS_LOAD_OFFSET_S      3
0309 #define P_REG_PS_LOAD_OFFSET_M      BIT(3)
0310 #define P_REG_PS_SFT_RESET_S        11
0311 #define P_REG_PS_SFT_RESET_M        BIT(11)
0312
0313 /* PHY offset valid registers */
0314 #define P_REG_TX_OV_STATUS      0x4D4
0315 #define P_REG_TX_OV_STATUS_OV_S     0
0316 #define P_REG_TX_OV_STATUS_OV_M     BIT(0)
0317 #define P_REG_RX_OV_STATUS      0x4F8
0318 #define P_REG_RX_OV_STATUS_OV_S     0
0319 #define P_REG_RX_OV_STATUS_OV_M     BIT(0)
0320
0321 /* PHY offset ready registers */
0322 #define P_REG_TX_OR         0x45C
0323 #define P_REG_RX_OR         0x47C
0324
0325 /* PHY total offset registers */
0326 #define P_REG_TOTAL_RX_OFFSET_L     0x460
0327 #define P_REG_TOTAL_RX_OFFSET_U     0x464
0328 #define P_REG_TOTAL_TX_OFFSET_L     0x440
0329 #define P_REG_TOTAL_TX_OFFSET_U     0x444
0330
0331 /* Timestamp PAR/PCS registers */
0332 #define P_REG_UIX66_10G_40G_L       0x480
0333 #define P_REG_UIX66_10G_40G_U       0x484
0334 #define P_REG_UIX66_25G_100G_L      0x488
0335 #define P_REG_UIX66_25G_100G_U      0x48C
0336 #define P_REG_DESK_PAR_RX_TUS_L     0x490
0337 #define P_REG_DESK_PAR_RX_TUS_U     0x494
0338 #define P_REG_DESK_PAR_TX_TUS_L     0x498
0339 #define P_REG_DESK_PAR_TX_TUS_U     0x49C
0340 #define P_REG_DESK_PCS_RX_TUS_L     0x4A0
0341 #define P_REG_DESK_PCS_RX_TUS_U     0x4A4
0342 #define P_REG_DESK_PCS_TX_TUS_L     0x4A8
0343 #define P_REG_DESK_PCS_TX_TUS_U     0x4AC
0344 #define P_REG_PAR_RX_TUS_L      0x420
0345 #define P_REG_PAR_RX_TUS_U      0x424
0346 #define P_REG_PAR_TX_TUS_L      0x428
0347 #define P_REG_PAR_TX_TUS_U      0x42C
0348 #define P_REG_PCS_RX_TUS_L      0x430
0349 #define P_REG_PCS_RX_TUS_U      0x434
0350 #define P_REG_PCS_TX_TUS_L      0x438
0351 #define P_REG_PCS_TX_TUS_U      0x43C
0352 #define P_REG_PAR_RX_TIME_L     0x4F0
0353 #define P_REG_PAR_RX_TIME_U     0x4F4
0354 #define P_REG_PAR_TX_TIME_L     0x4CC
0355 #define P_REG_PAR_TX_TIME_U     0x4D0
0356 #define P_REG_PAR_PCS_RX_OFFSET_L   0x4E8
0357 #define P_REG_PAR_PCS_RX_OFFSET_U   0x4EC
0358 #define P_REG_PAR_PCS_TX_OFFSET_L   0x4C4
0359 #define P_REG_PAR_PCS_TX_OFFSET_U   0x4C8
0360 #define P_REG_LINK_SPEED        0x4FC
0361 #define P_REG_LINK_SPEED_SERDES_S   0
0362 #define P_REG_LINK_SPEED_SERDES_M   ICE_M(0x7, 0)
0363 #define P_REG_LINK_SPEED_FEC_MODE_S 3
0364 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
0365 #define P_REG_LINK_SPEED_FEC_MODE(reg)          \
0366     (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >>   \
0367      P_REG_LINK_SPEED_FEC_MODE_S)
0368
0369 /* PHY timestamp related registers */
0370 #define P_REG_PMD_ALIGNMENT     0x0FC
0371 #define P_REG_RX_80_TO_160_CNT      0x6FC
0372 #define P_REG_RX_80_TO_160_CNT_RXCYC_S  0
0373 #define P_REG_RX_80_TO_160_CNT_RXCYC_M  BIT(0)
0374 #define P_REG_RX_40_TO_160_CNT      0x8FC
0375 #define P_REG_RX_40_TO_160_CNT_RXCYC_S  0
0376 #define P_REG_RX_40_TO_160_CNT_RXCYC_M  ICE_M(0x3, 0)
0377
0378 /* Rx FIFO status registers */
0379 #define P_REG_RX_OV_FS          0x4F8
0380 #define P_REG_RX_OV_FS_FIFO_STATUS_S    2
0381 #define P_REG_RX_OV_FS_FIFO_STATUS_M    ICE_M(0x3FF, 2)
0382
0383 /* Timestamp command registers */
0384 #define P_REG_TX_TMR_CMD        0x448
0385 #define P_REG_RX_TMR_CMD        0x468
0386
0387 /* E810 timesync enable register */
0388 #define ETH_GLTSYN_ENA(_i)      (0x03000348 + ((_i) * 4))
0389
0390 /* E810 shadow init time registers */
0391 #define ETH_GLTSYN_SHTIME_0(i)      (0x03000368 + ((i) * 32))
0392 #define ETH_GLTSYN_SHTIME_L(i)      (0x0300036C + ((i) * 32))
0393
0394 /* E810 shadow time adjust registers */
0395 #define ETH_GLTSYN_SHADJ_L(_i)      (0x03000378 + ((_i) * 32))
0396 #define ETH_GLTSYN_SHADJ_H(_i)      (0x0300037C + ((_i) * 32))
0397
0398 /* E810 timer command register */
0399 #define ETH_GLTSYN_CMD          0x03000344
0400
0401 /* Source timer incval macros */
0402 #define INCVAL_HIGH_M           0xFF
0403
0404 /* Timestamp block macros */
0405 #define TS_LOW_M            0xFFFFFFFF
0406 #define TS_HIGH_M           0xFF
0407 #define TS_HIGH_S           32
0408
0409 #define TS_PHY_LOW_M            0xFF
0410 #define TS_PHY_HIGH_M           0xFFFFFFFF
0411 #define TS_PHY_HIGH_S           8
0412
0413 #define BYTES_PER_IDX_ADDR_L_U      8
0414 #define BYTES_PER_IDX_ADDR_L        4
0415
0416 /* Internal PHY timestamp address */
0417 #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
0418 #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U +       \
0419                  BYTES_PER_IDX_ADDR_L))
0420
0421 /* External PHY timestamp address */
0422 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) +         \
0423                  ((idx) * BYTES_PER_IDX_ADDR_L_U))
0424
0425 #define LOW_TX_MEMORY_BANK_START    0x03090000
0426 #define HIGH_TX_MEMORY_BANK_START   0x03090004
0427
0428 /* E810T SMA controller pin control */
0429 #define ICE_SMA1_DIR_EN_E810T       BIT(4)
0430 #define ICE_SMA1_TX_EN_E810T        BIT(5)
0431 #define ICE_SMA2_UFL2_RX_DIS_E810T  BIT(3)
0432 #define ICE_SMA2_DIR_EN_E810T       BIT(6)
0433 #define ICE_SMA2_TX_EN_E810T        BIT(7)
0434
0435 #define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
0436                  ICE_SMA1_TX_EN_E810T)
0437 #define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
0438                  ICE_SMA2_DIR_EN_E810T | \
0439                  ICE_SMA2_TX_EN_E810T)
0440 #define ICE_ALL_SMA_MASK_E810T  (ICE_SMA1_MASK_E810T | \
0441                  ICE_SMA2_MASK_E810T)
0442
0443 #define ICE_SMA_MIN_BIT_E810T   3
0444 #define ICE_SMA_MAX_BIT_E810T   7
0445 #define ICE_PCA9575_P1_OFFSET   8
0446
0447 /* E810T PCA9575 IO controller registers */
0448 #define ICE_PCA9575_P0_IN   0x0
0449
0450 /* E810T PCA9575 IO controller pin control */
0451 #define ICE_E810T_P0_GNSS_PRSNT_N   BIT(4)
0452
0453 #endif /* _ICE_PTP_HW_H_ */