intel/ice/ice_ptp_consts.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (C) 2018-2021, Intel Corporation. */
0003
0004 #ifndef _ICE_PTP_CONSTS_H_
0005 #define _ICE_PTP_CONSTS_H_
0006
0007 /* Constant definitions related to the hardware clock used for PTP 1588
0008  * features and functionality.
0009  */
0010 /* Constants defined for the PTP 1588 clock hardware. */
0011
0012 /* struct ice_time_ref_info_e822
0013  *
0014  * E822 hardware can use different sources as the reference for the PTP
0015  * hardware clock. Each clock has different characteristics such as a slightly
0016  * different frequency, etc.
0017  *
0018  * This lookup table defines several constants that depend on the current time
0019  * reference. See the struct ice_time_ref_info_e822 for information about the
0020  * meaning of each constant.
0021  */
0022 const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ] = {
0023     /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
0024     {
0025         /* pll_freq */
0026         823437500, /* 823.4375 MHz PLL */
0027         /* nominal_incval */
0028         0x136e44fabULL,
0029         /* pps_delay */
0030         11,
0031     },
0032
0033     /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
0034     {
0035         /* pll_freq */
0036         783360000, /* 783.36 MHz */
0037         /* nominal_incval */
0038         0x146cc2177ULL,
0039         /* pps_delay */
0040         12,
0041     },
0042
0043     /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
0044     {
0045         /* pll_freq */
0046         796875000, /* 796.875 MHz */
0047         /* nominal_incval */
0048         0x141414141ULL,
0049         /* pps_delay */
0050         12,
0051     },
0052
0053     /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
0054     {
0055         /* pll_freq */
0056         816000000, /* 816 MHz */
0057         /* nominal_incval */
0058         0x139b9b9baULL,
0059         /* pps_delay */
0060         12,
0061     },
0062
0063     /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
0064     {
0065         /* pll_freq */
0066         830078125, /* 830.78125 MHz */
0067         /* nominal_incval */
0068         0x134679aceULL,
0069         /* pps_delay */
0070         11,
0071     },
0072
0073     /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
0074     {
0075         /* pll_freq */
0076         783360000, /* 783.36 MHz */
0077         /* nominal_incval */
0078         0x146cc2177ULL,
0079         /* pps_delay */
0080         12,
0081     },
0082 };
0083
0084 const struct ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ] = {
0085     /* ICE_TIME_REF_FREQ_25_000 -> 25 MHz */
0086     {
0087         /* refclk_pre_div */
0088         1,
0089         /* feedback_div */
0090         197,
0091         /* frac_n_div */
0092         2621440,
0093         /* post_pll_div */
0094         6,
0095     },
0096
0097     /* ICE_TIME_REF_FREQ_122_880 -> 122.88 MHz */
0098     {
0099         /* refclk_pre_div */
0100         5,
0101         /* feedback_div */
0102         223,
0103         /* frac_n_div */
0104         524288,
0105         /* post_pll_div */
0106         7,
0107     },
0108
0109     /* ICE_TIME_REF_FREQ_125_000 -> 125 MHz */
0110     {
0111         /* refclk_pre_div */
0112         5,
0113         /* feedback_div */
0114         223,
0115         /* frac_n_div */
0116         524288,
0117         /* post_pll_div */
0118         7,
0119     },
0120
0121     /* ICE_TIME_REF_FREQ_153_600 -> 153.6 MHz */
0122     {
0123         /* refclk_pre_div */
0124         5,
0125         /* feedback_div */
0126         159,
0127         /* frac_n_div */
0128         1572864,
0129         /* post_pll_div */
0130         6,
0131     },
0132
0133     /* ICE_TIME_REF_FREQ_156_250 -> 156.25 MHz */
0134     {
0135         /* refclk_pre_div */
0136         5,
0137         /* feedback_div */
0138         159,
0139         /* frac_n_div */
0140         1572864,
0141         /* post_pll_div */
0142         6,
0143     },
0144
0145     /* ICE_TIME_REF_FREQ_245_760 -> 245.76 MHz */
0146     {
0147         /* refclk_pre_div */
0148         10,
0149         /* feedback_div */
0150         223,
0151         /* frac_n_div */
0152         524288,
0153         /* post_pll_div */
0154         7,
0155     },
0156 };
0157
0158 /* struct ice_vernier_info_e822
0159  *
0160  * E822 hardware calibrates the delay of the timestamp indication from the
0161  * actual packet transmission or reception during the initialization of the
0162  * PHY. To do this, the hardware mechanism uses some conversions between the
0163  * various clocks within the PHY block. This table defines constants used to
0164  * calculate the correct conversion ratios in the PHY registers.
0165  *
0166  * Many of the values relate to the PAR/PCS clock conversion registers. For
0167  * these registers, a value of 0 means that the associated register is not
0168  * used by this link speed, and that the register should be cleared by writing
0169  * 0. Other values specify the clock frequency in Hz.
0170  */
0171 const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD] = {
0172     /* ICE_PTP_LNK_SPD_1G */
0173     {
0174         /* tx_par_clk */
0175         31250000, /* 31.25 MHz */
0176         /* rx_par_clk */
0177         31250000, /* 31.25 MHz */
0178         /* tx_pcs_clk */
0179         125000000, /* 125 MHz */
0180         /* rx_pcs_clk */
0181         125000000, /* 125 MHz */
0182         /* tx_desk_rsgb_par */
0183         0, /* unused */
0184         /* rx_desk_rsgb_par */
0185         0, /* unused */
0186         /* tx_desk_rsgb_pcs */
0187         0, /* unused */
0188         /* rx_desk_rsgb_pcs */
0189         0, /* unused */
0190         /* tx_fixed_delay */
0191         25140,
0192         /* pmd_adj_divisor */
0193         10000000,
0194         /* rx_fixed_delay */
0195         17372,
0196     },
0197     /* ICE_PTP_LNK_SPD_10G */
0198     {
0199         /* tx_par_clk */
0200         257812500, /* 257.8125 MHz */
0201         /* rx_par_clk */
0202         257812500, /* 257.8125 MHz */
0203         /* tx_pcs_clk */
0204         156250000, /* 156.25 MHz */
0205         /* rx_pcs_clk */
0206         156250000, /* 156.25 MHz */
0207         /* tx_desk_rsgb_par */
0208         0, /* unused */
0209         /* rx_desk_rsgb_par */
0210         0, /* unused */
0211         /* tx_desk_rsgb_pcs */
0212         0, /* unused */
0213         /* rx_desk_rsgb_pcs */
0214         0, /* unused */
0215         /* tx_fixed_delay */
0216         6938,
0217         /* pmd_adj_divisor */
0218         82500000,
0219         /* rx_fixed_delay */
0220         6212,
0221     },
0222     /* ICE_PTP_LNK_SPD_25G */
0223     {
0224         /* tx_par_clk */
0225         644531250, /* 644.53125 MHZ */
0226         /* rx_par_clk */
0227         644531250, /* 644.53125 MHz */
0228         /* tx_pcs_clk */
0229         390625000, /* 390.625 MHz */
0230         /* rx_pcs_clk */
0231         390625000, /* 390.625 MHz */
0232         /* tx_desk_rsgb_par */
0233         0, /* unused */
0234         /* rx_desk_rsgb_par */
0235         0, /* unused */
0236         /* tx_desk_rsgb_pcs */
0237         0, /* unused */
0238         /* rx_desk_rsgb_pcs */
0239         0, /* unused */
0240         /* tx_fixed_delay */
0241         2778,
0242         /* pmd_adj_divisor */
0243         206250000,
0244         /* rx_fixed_delay */
0245         2491,
0246     },
0247     /* ICE_PTP_LNK_SPD_25G_RS */
0248     {
0249         /* tx_par_clk */
0250         0, /* unused */
0251         /* rx_par_clk */
0252         0, /* unused */
0253         /* tx_pcs_clk */
0254         0, /* unused */
0255         /* rx_pcs_clk */
0256         0, /* unused */
0257         /* tx_desk_rsgb_par */
0258         161132812, /* 162.1328125 MHz Reed Solomon gearbox */
0259         /* rx_desk_rsgb_par */
0260         161132812, /* 162.1328125 MHz Reed Solomon gearbox */
0261         /* tx_desk_rsgb_pcs */
0262         97656250, /* 97.62625 MHz Reed Solomon gearbox */
0263         /* rx_desk_rsgb_pcs */
0264         97656250, /* 97.62625 MHz Reed Solomon gearbox */
0265         /* tx_fixed_delay */
0266         3928,
0267         /* pmd_adj_divisor */
0268         206250000,
0269         /* rx_fixed_delay */
0270         29535,
0271     },
0272     /* ICE_PTP_LNK_SPD_40G */
0273     {
0274         /* tx_par_clk */
0275         257812500,
0276         /* rx_par_clk */
0277         257812500,
0278         /* tx_pcs_clk */
0279         156250000, /* 156.25 MHz */
0280         /* rx_pcs_clk */
0281         156250000, /* 156.25 MHz */
0282         /* tx_desk_rsgb_par */
0283         0, /* unused */
0284         /* rx_desk_rsgb_par */
0285         156250000, /* 156.25 MHz deskew clock */
0286         /* tx_desk_rsgb_pcs */
0287         0, /* unused */
0288         /* rx_desk_rsgb_pcs */
0289         156250000, /* 156.25 MHz deskew clock */
0290         /* tx_fixed_delay */
0291         5666,
0292         /* pmd_adj_divisor */
0293         82500000,
0294         /* rx_fixed_delay */
0295         4244,
0296     },
0297     /* ICE_PTP_LNK_SPD_50G */
0298     {
0299         /* tx_par_clk */
0300         644531250, /* 644.53125 MHZ */
0301         /* rx_par_clk */
0302         644531250, /* 644.53125 MHZ */
0303         /* tx_pcs_clk */
0304         390625000, /* 390.625 MHz */
0305         /* rx_pcs_clk */
0306         390625000, /* 390.625 MHz */
0307         /* tx_desk_rsgb_par */
0308         0, /* unused */
0309         /* rx_desk_rsgb_par */
0310         195312500, /* 193.3125 MHz deskew clock */
0311         /* tx_desk_rsgb_pcs */
0312         0, /* unused */
0313         /* rx_desk_rsgb_pcs */
0314         195312500, /* 193.3125 MHz deskew clock */
0315         /* tx_fixed_delay */
0316         2778,
0317         /* pmd_adj_divisor */
0318         206250000,
0319         /* rx_fixed_delay */
0320         2868,
0321     },
0322     /* ICE_PTP_LNK_SPD_50G_RS */
0323     {
0324         /* tx_par_clk */
0325         0, /* unused */
0326         /* rx_par_clk */
0327         644531250, /* 644.53125 MHz */
0328         /* tx_pcs_clk */
0329         0, /* unused */
0330         /* rx_pcs_clk */
0331         644531250, /* 644.53125 MHz */
0332         /* tx_desk_rsgb_par */
0333         322265625, /* 322.265625 MHz Reed Solomon gearbox */
0334         /* rx_desk_rsgb_par */
0335         322265625, /* 322.265625 MHz Reed Solomon gearbox */
0336         /* tx_desk_rsgb_pcs */
0337         644531250, /* 644.53125 MHz Reed Solomon gearbox */
0338         /* rx_desk_rsgb_pcs */
0339         644531250, /* 644.53125 MHz Reed Solomon gearbox */
0340         /* tx_fixed_delay */
0341         2095,
0342         /* pmd_adj_divisor */
0343         206250000,
0344         /* rx_fixed_delay */
0345         14524,
0346     },
0347     /* ICE_PTP_LNK_SPD_100G_RS */
0348     {
0349         /* tx_par_clk */
0350         0, /* unused */
0351         /* rx_par_clk */
0352         644531250, /* 644.53125 MHz */
0353         /* tx_pcs_clk */
0354         0, /* unused */
0355         /* rx_pcs_clk */
0356         644531250, /* 644.53125 MHz */
0357         /* tx_desk_rsgb_par */
0358         644531250, /* 644.53125 MHz Reed Solomon gearbox */
0359         /* rx_desk_rsgb_par */
0360         644531250, /* 644.53125 MHz Reed Solomon gearbox */
0361         /* tx_desk_rsgb_pcs */
0362         644531250, /* 644.53125 MHz Reed Solomon gearbox */
0363         /* rx_desk_rsgb_pcs */
0364         644531250, /* 644.53125 MHz Reed Solomon gearbox */
0365         /* tx_fixed_delay */
0366         1620,
0367         /* pmd_adj_divisor */
0368         206250000,
0369         /* rx_fixed_delay */
0370         7775,
0371     },
0372 };
0373
0374 #endif /* _ICE_PTP_CONSTS_H_ */