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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2018, Intel Corporation. */
0003 
0004 #ifndef _ICE_LAN_TX_RX_H_
0005 #define _ICE_LAN_TX_RX_H_
0006 
0007 union ice_32byte_rx_desc {
0008     struct {
0009         __le64 pkt_addr; /* Packet buffer address */
0010         __le64 hdr_addr; /* Header buffer address */
0011             /* bit 0 of hdr_addr is DD bit */
0012         __le64 rsvd1;
0013         __le64 rsvd2;
0014     } read;
0015     struct {
0016         struct {
0017             struct {
0018                 __le16 mirroring_status;
0019                 __le16 l2tag1;
0020             } lo_dword;
0021             union {
0022                 __le32 rss; /* RSS Hash */
0023                 __le32 fd_id; /* Flow Director filter ID */
0024             } hi_dword;
0025         } qword0;
0026         struct {
0027             /* status/error/PTYPE/length */
0028             __le64 status_error_len;
0029         } qword1;
0030         struct {
0031             __le16 ext_status; /* extended status */
0032             __le16 rsvd;
0033             __le16 l2tag2_1;
0034             __le16 l2tag2_2;
0035         } qword2;
0036         struct {
0037             __le32 reserved;
0038             __le32 fd_id;
0039         } qword3;
0040     } wb; /* writeback */
0041 };
0042 
0043 struct ice_fltr_desc {
0044     __le64 qidx_compq_space_stat;
0045     __le64 dtype_cmd_vsi_fdid;
0046 };
0047 
0048 #define ICE_FXD_FLTR_QW0_QINDEX_S   0
0049 #define ICE_FXD_FLTR_QW0_QINDEX_M   (0x7FFULL << ICE_FXD_FLTR_QW0_QINDEX_S)
0050 #define ICE_FXD_FLTR_QW0_COMP_Q_S   11
0051 #define ICE_FXD_FLTR_QW0_COMP_Q_M   BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)
0052 #define ICE_FXD_FLTR_QW0_COMP_Q_ZERO    0x0ULL
0053 
0054 #define ICE_FXD_FLTR_QW0_COMP_REPORT_S  12
0055 #define ICE_FXD_FLTR_QW0_COMP_REPORT_M  \
0056                 (0x3ULL << ICE_FXD_FLTR_QW0_COMP_REPORT_S)
0057 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW_FAIL    0x1ULL
0058 #define ICE_FXD_FLTR_QW0_COMP_REPORT_SW     0x2ULL
0059 
0060 #define ICE_FXD_FLTR_QW0_FD_SPACE_S 14
0061 #define ICE_FXD_FLTR_QW0_FD_SPACE_M (0x3ULL << ICE_FXD_FLTR_QW0_FD_SPACE_S)
0062 #define ICE_FXD_FLTR_QW0_FD_SPACE_GUAR_BEST     0x2ULL
0063 
0064 #define ICE_FXD_FLTR_QW0_STAT_CNT_S 16
0065 #define ICE_FXD_FLTR_QW0_STAT_CNT_M \
0066                 (0x1FFFULL << ICE_FXD_FLTR_QW0_STAT_CNT_S)
0067 #define ICE_FXD_FLTR_QW0_STAT_ENA_S 29
0068 #define ICE_FXD_FLTR_QW0_STAT_ENA_M (0x3ULL << ICE_FXD_FLTR_QW0_STAT_ENA_S)
0069 #define ICE_FXD_FLTR_QW0_STAT_ENA_PKTS      0x1ULL
0070 
0071 #define ICE_FXD_FLTR_QW0_EVICT_ENA_S    31
0072 #define ICE_FXD_FLTR_QW0_EVICT_ENA_M    BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)
0073 #define ICE_FXD_FLTR_QW0_EVICT_ENA_FALSE    0x0ULL
0074 #define ICE_FXD_FLTR_QW0_EVICT_ENA_TRUE     0x1ULL
0075 
0076 #define ICE_FXD_FLTR_QW0_TO_Q_S     32
0077 #define ICE_FXD_FLTR_QW0_TO_Q_M     (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_S)
0078 #define ICE_FXD_FLTR_QW0_TO_Q_EQUALS_QINDEX 0x0ULL
0079 
0080 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_S 35
0081 #define ICE_FXD_FLTR_QW0_TO_Q_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_TO_Q_PRI_S)
0082 #define ICE_FXD_FLTR_QW0_TO_Q_PRIO1 0x1ULL
0083 
0084 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_S   38
0085 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_M   \
0086             (0x3ULL << ICE_FXD_FLTR_QW0_DPU_RECIPE_S)
0087 #define ICE_FXD_FLTR_QW0_DPU_RECIPE_DFLT    0x0ULL
0088 
0089 #define ICE_FXD_FLTR_QW0_DROP_S     40
0090 #define ICE_FXD_FLTR_QW0_DROP_M     BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)
0091 #define ICE_FXD_FLTR_QW0_DROP_NO    0x0ULL
0092 #define ICE_FXD_FLTR_QW0_DROP_YES   0x1ULL
0093 
0094 #define ICE_FXD_FLTR_QW0_FLEX_PRI_S 41
0095 #define ICE_FXD_FLTR_QW0_FLEX_PRI_M (0x7ULL << ICE_FXD_FLTR_QW0_FLEX_PRI_S)
0096 #define ICE_FXD_FLTR_QW0_FLEX_PRI_NONE  0x0ULL
0097 
0098 #define ICE_FXD_FLTR_QW0_FLEX_MDID_S    44
0099 #define ICE_FXD_FLTR_QW0_FLEX_MDID_M    (0xFULL << ICE_FXD_FLTR_QW0_FLEX_MDID_S)
0100 #define ICE_FXD_FLTR_QW0_FLEX_MDID0 0x0ULL
0101 
0102 #define ICE_FXD_FLTR_QW0_FLEX_VAL_S 48
0103 #define ICE_FXD_FLTR_QW0_FLEX_VAL_M \
0104                 (0xFFFFULL << ICE_FXD_FLTR_QW0_FLEX_VAL_S)
0105 #define ICE_FXD_FLTR_QW0_FLEX_VAL0  0x0ULL
0106 
0107 #define ICE_FXD_FLTR_QW1_DTYPE_S    0
0108 #define ICE_FXD_FLTR_QW1_DTYPE_M    (0xFULL << ICE_FXD_FLTR_QW1_DTYPE_S)
0109 #define ICE_FXD_FLTR_QW1_PCMD_S     4
0110 #define ICE_FXD_FLTR_QW1_PCMD_M     BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)
0111 #define ICE_FXD_FLTR_QW1_PCMD_ADD   0x0ULL
0112 #define ICE_FXD_FLTR_QW1_PCMD_REMOVE    0x1ULL
0113 
0114 #define ICE_FXD_FLTR_QW1_PROF_PRI_S 5
0115 #define ICE_FXD_FLTR_QW1_PROF_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_PROF_PRI_S)
0116 #define ICE_FXD_FLTR_QW1_PROF_PRIO_ZERO 0x0ULL
0117 
0118 #define ICE_FXD_FLTR_QW1_PROF_S     8
0119 #define ICE_FXD_FLTR_QW1_PROF_M     (0x3FULL << ICE_FXD_FLTR_QW1_PROF_S)
0120 #define ICE_FXD_FLTR_QW1_PROF_ZERO  0x0ULL
0121 
0122 #define ICE_FXD_FLTR_QW1_FD_VSI_S   14
0123 #define ICE_FXD_FLTR_QW1_FD_VSI_M   (0x3FFULL << ICE_FXD_FLTR_QW1_FD_VSI_S)
0124 #define ICE_FXD_FLTR_QW1_SWAP_S     24
0125 #define ICE_FXD_FLTR_QW1_SWAP_M     BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)
0126 #define ICE_FXD_FLTR_QW1_SWAP_NOT_SET   0x0ULL
0127 #define ICE_FXD_FLTR_QW1_SWAP_SET   0x1ULL
0128 
0129 #define ICE_FXD_FLTR_QW1_FDID_PRI_S 25
0130 #define ICE_FXD_FLTR_QW1_FDID_PRI_M (0x7ULL << ICE_FXD_FLTR_QW1_FDID_PRI_S)
0131 #define ICE_FXD_FLTR_QW1_FDID_PRI_ONE   0x1ULL
0132 #define ICE_FXD_FLTR_QW1_FDID_PRI_THREE 0x3ULL
0133 
0134 #define ICE_FXD_FLTR_QW1_FDID_MDID_S    28
0135 #define ICE_FXD_FLTR_QW1_FDID_MDID_M    (0xFULL << ICE_FXD_FLTR_QW1_FDID_MDID_S)
0136 #define ICE_FXD_FLTR_QW1_FDID_MDID_FD   0x05ULL
0137 
0138 #define ICE_FXD_FLTR_QW1_FDID_S     32
0139 #define ICE_FXD_FLTR_QW1_FDID_M     \
0140             (0xFFFFFFFFULL << ICE_FXD_FLTR_QW1_FDID_S)
0141 #define ICE_FXD_FLTR_QW1_FDID_ZERO  0x0ULL
0142 
0143 /* definition for FD filter programming status descriptor WB format */
0144 #define ICE_FXD_FLTR_WB_QW1_DD_S    0
0145 #define ICE_FXD_FLTR_WB_QW1_DD_M    (0x1ULL << ICE_FXD_FLTR_WB_QW1_DD_S)
0146 #define ICE_FXD_FLTR_WB_QW1_DD_YES  0x1ULL
0147 
0148 #define ICE_FXD_FLTR_WB_QW1_PROG_ID_S   1
0149 #define ICE_FXD_FLTR_WB_QW1_PROG_ID_M   \
0150                 (0x3ULL << ICE_FXD_FLTR_WB_QW1_PROG_ID_S)
0151 #define ICE_FXD_FLTR_WB_QW1_PROG_ADD    0x0ULL
0152 #define ICE_FXD_FLTR_WB_QW1_PROG_DEL    0x1ULL
0153 
0154 #define ICE_FXD_FLTR_WB_QW1_FAIL_S  4
0155 #define ICE_FXD_FLTR_WB_QW1_FAIL_M  (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_S)
0156 #define ICE_FXD_FLTR_WB_QW1_FAIL_YES    0x1ULL
0157 
0158 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S 5
0159 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_M \
0160                 (0x1ULL << ICE_FXD_FLTR_WB_QW1_FAIL_PROF_S)
0161 #define ICE_FXD_FLTR_WB_QW1_FAIL_PROF_YES   0x1ULL
0162 
0163 struct ice_rx_ptype_decoded {
0164     u32 known:1;
0165     u32 outer_ip:1;
0166     u32 outer_ip_ver:2;
0167     u32 outer_frag:1;
0168     u32 tunnel_type:3;
0169     u32 tunnel_end_prot:2;
0170     u32 tunnel_end_frag:1;
0171     u32 inner_prot:4;
0172     u32 payload_layer:3;
0173 };
0174 
0175 enum ice_rx_ptype_outer_ip {
0176     ICE_RX_PTYPE_OUTER_L2   = 0,
0177     ICE_RX_PTYPE_OUTER_IP   = 1,
0178 };
0179 
0180 enum ice_rx_ptype_outer_ip_ver {
0181     ICE_RX_PTYPE_OUTER_NONE = 0,
0182     ICE_RX_PTYPE_OUTER_IPV4 = 1,
0183     ICE_RX_PTYPE_OUTER_IPV6 = 2,
0184 };
0185 
0186 enum ice_rx_ptype_outer_fragmented {
0187     ICE_RX_PTYPE_NOT_FRAG   = 0,
0188     ICE_RX_PTYPE_FRAG   = 1,
0189 };
0190 
0191 enum ice_rx_ptype_tunnel_type {
0192     ICE_RX_PTYPE_TUNNEL_NONE        = 0,
0193     ICE_RX_PTYPE_TUNNEL_IP_IP       = 1,
0194     ICE_RX_PTYPE_TUNNEL_IP_GRENAT       = 2,
0195     ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC   = 3,
0196     ICE_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN  = 4,
0197 };
0198 
0199 enum ice_rx_ptype_tunnel_end_prot {
0200     ICE_RX_PTYPE_TUNNEL_END_NONE    = 0,
0201     ICE_RX_PTYPE_TUNNEL_END_IPV4    = 1,
0202     ICE_RX_PTYPE_TUNNEL_END_IPV6    = 2,
0203 };
0204 
0205 enum ice_rx_ptype_inner_prot {
0206     ICE_RX_PTYPE_INNER_PROT_NONE        = 0,
0207     ICE_RX_PTYPE_INNER_PROT_UDP     = 1,
0208     ICE_RX_PTYPE_INNER_PROT_TCP     = 2,
0209     ICE_RX_PTYPE_INNER_PROT_SCTP        = 3,
0210     ICE_RX_PTYPE_INNER_PROT_ICMP        = 4,
0211     ICE_RX_PTYPE_INNER_PROT_TIMESYNC    = 5,
0212 };
0213 
0214 enum ice_rx_ptype_payload_layer {
0215     ICE_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
0216     ICE_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
0217     ICE_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
0218     ICE_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
0219 };
0220 
0221 /* Rx Flex Descriptor
0222  * This descriptor is used instead of the legacy version descriptor when
0223  * ice_rlan_ctx.adv_desc is set
0224  */
0225 union ice_32b_rx_flex_desc {
0226     struct {
0227         __le64 pkt_addr; /* Packet buffer address */
0228         __le64 hdr_addr; /* Header buffer address */
0229                  /* bit 0 of hdr_addr is DD bit */
0230         __le64 rsvd1;
0231         __le64 rsvd2;
0232     } read;
0233     struct {
0234         /* Qword 0 */
0235         u8 rxdid; /* descriptor builder profile ID */
0236         u8 mir_id_umb_cast; /* mirror=[5:0], umb=[7:6] */
0237         __le16 ptype_flex_flags0; /* ptype=[9:0], ff0=[15:10] */
0238         __le16 pkt_len; /* [15:14] are reserved */
0239         __le16 hdr_len_sph_flex_flags1; /* header=[10:0] */
0240                         /* sph=[11:11] */
0241                         /* ff1/ext=[15:12] */
0242 
0243         /* Qword 1 */
0244         __le16 status_error0;
0245         __le16 l2tag1;
0246         __le16 flex_meta0;
0247         __le16 flex_meta1;
0248 
0249         /* Qword 2 */
0250         __le16 status_error1;
0251         u8 flex_flags2;
0252         u8 time_stamp_low;
0253         __le16 l2tag2_1st;
0254         __le16 l2tag2_2nd;
0255 
0256         /* Qword 3 */
0257         __le16 flex_meta2;
0258         __le16 flex_meta3;
0259         union {
0260             struct {
0261                 __le16 flex_meta4;
0262                 __le16 flex_meta5;
0263             } flex;
0264             __le32 ts_high;
0265         } flex_ts;
0266     } wb; /* writeback */
0267 };
0268 
0269 /* Rx Flex Descriptor NIC Profile
0270  * This descriptor corresponds to RxDID 2 which contains
0271  * metadata fields for RSS, flow ID and timestamp info
0272  */
0273 struct ice_32b_rx_flex_desc_nic {
0274     /* Qword 0 */
0275     u8 rxdid;
0276     u8 mir_id_umb_cast;
0277     __le16 ptype_flexi_flags0;
0278     __le16 pkt_len;
0279     __le16 hdr_len_sph_flex_flags1;
0280 
0281     /* Qword 1 */
0282     __le16 status_error0;
0283     __le16 l2tag1;
0284     __le32 rss_hash;
0285 
0286     /* Qword 2 */
0287     __le16 status_error1;
0288     u8 flexi_flags2;
0289     u8 ts_low;
0290     __le16 l2tag2_1st;
0291     __le16 l2tag2_2nd;
0292 
0293     /* Qword 3 */
0294     __le32 flow_id;
0295     union {
0296         struct {
0297             __le16 vlan_id;
0298             __le16 flow_id_ipv6;
0299         } flex;
0300         __le32 ts_high;
0301     } flex_ts;
0302 };
0303 
0304 /* Rx Flex Descriptor NIC Profile
0305  * RxDID Profile ID 6
0306  * Flex-field 0: RSS hash lower 16-bits
0307  * Flex-field 1: RSS hash upper 16-bits
0308  * Flex-field 2: Flow ID lower 16-bits
0309  * Flex-field 3: Source VSI
0310  * Flex-field 4: reserved, VLAN ID taken from L2Tag
0311  */
0312 struct ice_32b_rx_flex_desc_nic_2 {
0313     /* Qword 0 */
0314     u8 rxdid;
0315     u8 mir_id_umb_cast;
0316     __le16 ptype_flexi_flags0;
0317     __le16 pkt_len;
0318     __le16 hdr_len_sph_flex_flags1;
0319 
0320     /* Qword 1 */
0321     __le16 status_error0;
0322     __le16 l2tag1;
0323     __le32 rss_hash;
0324 
0325     /* Qword 2 */
0326     __le16 status_error1;
0327     u8 flexi_flags2;
0328     u8 ts_low;
0329     __le16 l2tag2_1st;
0330     __le16 l2tag2_2nd;
0331 
0332     /* Qword 3 */
0333     __le16 flow_id;
0334     __le16 src_vsi;
0335     union {
0336         struct {
0337             __le16 rsvd;
0338             __le16 flow_id_ipv6;
0339         } flex;
0340         __le32 ts_high;
0341     } flex_ts;
0342 };
0343 
0344 /* Receive Flex Descriptor profile IDs: There are a total
0345  * of 64 profiles where profile IDs 0/1 are for legacy; and
0346  * profiles 2-63 are flex profiles that can be programmed
0347  * with a specific metadata (profile 7 reserved for HW)
0348  */
0349 enum ice_rxdid {
0350     ICE_RXDID_LEGACY_0      = 0,
0351     ICE_RXDID_LEGACY_1      = 1,
0352     ICE_RXDID_FLEX_NIC      = 2,
0353     ICE_RXDID_FLEX_NIC_2        = 6,
0354     ICE_RXDID_HW            = 7,
0355     ICE_RXDID_LAST          = 63,
0356 };
0357 
0358 /* Receive Flex Descriptor Rx opcode values */
0359 #define ICE_RX_OPC_MDID     0x01
0360 
0361 /* Receive Descriptor MDID values that access packet flags */
0362 enum ice_flex_mdid_pkt_flags {
0363     ICE_RX_MDID_PKT_FLAGS_15_0  = 20,
0364     ICE_RX_MDID_PKT_FLAGS_31_16,
0365     ICE_RX_MDID_PKT_FLAGS_47_32,
0366     ICE_RX_MDID_PKT_FLAGS_63_48,
0367 };
0368 
0369 /* Receive Descriptor MDID values */
0370 enum ice_flex_rx_mdid {
0371     ICE_RX_MDID_FLOW_ID_LOWER   = 5,
0372     ICE_RX_MDID_FLOW_ID_HIGH,
0373     ICE_RX_MDID_SRC_VSI     = 19,
0374     ICE_RX_MDID_HASH_LOW        = 56,
0375     ICE_RX_MDID_HASH_HIGH,
0376 };
0377 
0378 /* Rx/Tx Flag64 packet flag bits */
0379 enum ice_flg64_bits {
0380     ICE_FLG_PKT_DSI     = 0,
0381     ICE_FLG_EVLAN_x8100 = 14,
0382     ICE_FLG_EVLAN_x9100,
0383     ICE_FLG_VLAN_x8100,
0384     ICE_FLG_TNL_MAC     = 22,
0385     ICE_FLG_TNL_VLAN,
0386     ICE_FLG_PKT_FRG,
0387     ICE_FLG_FIN     = 32,
0388     ICE_FLG_SYN,
0389     ICE_FLG_RST,
0390     ICE_FLG_TNL0        = 38,
0391     ICE_FLG_TNL1,
0392     ICE_FLG_TNL2,
0393     ICE_FLG_UDP_GRE,
0394     ICE_FLG_RSVD        = 63
0395 };
0396 
0397 /* for ice_32byte_rx_flex_desc.ptype_flexi_flags0 member */
0398 #define ICE_RX_FLEX_DESC_PTYPE_M    (0x3FF) /* 10-bits */
0399 
0400 /* for ice_32byte_rx_flex_desc.pkt_length member */
0401 #define ICE_RX_FLX_DESC_PKT_LEN_M   (0x3FFF) /* 14-bits */
0402 
0403 enum ice_rx_flex_desc_status_error_0_bits {
0404     /* Note: These are predefined bit offsets */
0405     ICE_RX_FLEX_DESC_STATUS0_DD_S = 0,
0406     ICE_RX_FLEX_DESC_STATUS0_EOF_S,
0407     ICE_RX_FLEX_DESC_STATUS0_HBO_S,
0408     ICE_RX_FLEX_DESC_STATUS0_L3L4P_S,
0409     ICE_RX_FLEX_DESC_STATUS0_XSUM_IPE_S,
0410     ICE_RX_FLEX_DESC_STATUS0_XSUM_L4E_S,
0411     ICE_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S,
0412     ICE_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S,
0413     ICE_RX_FLEX_DESC_STATUS0_LPBK_S,
0414     ICE_RX_FLEX_DESC_STATUS0_IPV6EXADD_S,
0415     ICE_RX_FLEX_DESC_STATUS0_RXE_S,
0416     ICE_RX_FLEX_DESC_STATUS0_CRCP_S,
0417     ICE_RX_FLEX_DESC_STATUS0_RSS_VALID_S,
0418     ICE_RX_FLEX_DESC_STATUS0_L2TAG1P_S,
0419     ICE_RX_FLEX_DESC_STATUS0_XTRMD0_VALID_S,
0420     ICE_RX_FLEX_DESC_STATUS0_XTRMD1_VALID_S,
0421     ICE_RX_FLEX_DESC_STATUS0_LAST /* this entry must be last!!! */
0422 };
0423 
0424 enum ice_rx_flex_desc_status_error_1_bits {
0425     /* Note: These are predefined bit offsets */
0426     ICE_RX_FLEX_DESC_STATUS1_NAT_S = 4,
0427      /* [10:5] reserved */
0428     ICE_RX_FLEX_DESC_STATUS1_L2TAG2P_S = 11,
0429     ICE_RX_FLEX_DESC_STATUS1_LAST /* this entry must be last!!! */
0430 };
0431 
0432 #define ICE_RXQ_CTX_SIZE_DWORDS     8
0433 #define ICE_RXQ_CTX_SZ          (ICE_RXQ_CTX_SIZE_DWORDS * sizeof(u32))
0434 #define ICE_TX_CMPLTNQ_CTX_SIZE_DWORDS  22
0435 #define ICE_TX_DRBELL_Q_CTX_SIZE_DWORDS 5
0436 #define GLTCLAN_CQ_CNTX(i, CQ)      (GLTCLAN_CQ_CNTX0(CQ) + ((i) * 0x0800))
0437 
0438 /* RLAN Rx queue context data
0439  *
0440  * The sizes of the variables may be larger than needed due to crossing byte
0441  * boundaries. If we do not have the width of the variable set to the correct
0442  * size then we could end up shifting bits off the top of the variable when the
0443  * variable is at the top of a byte and crosses over into the next byte.
0444  */
0445 struct ice_rlan_ctx {
0446     u16 head;
0447     u16 cpuid; /* bigger than needed, see above for reason */
0448 #define ICE_RLAN_BASE_S 7
0449     u64 base;
0450     u16 qlen;
0451 #define ICE_RLAN_CTX_DBUF_S 7
0452     u16 dbuf; /* bigger than needed, see above for reason */
0453 #define ICE_RLAN_CTX_HBUF_S 6
0454     u16 hbuf; /* bigger than needed, see above for reason */
0455     u8 dtype;
0456     u8 dsize;
0457     u8 crcstrip;
0458     u8 l2tsel;
0459     u8 hsplit_0;
0460     u8 hsplit_1;
0461     u8 showiv;
0462     u32 rxmax; /* bigger than needed, see above for reason */
0463     u8 tphrdesc_ena;
0464     u8 tphwdesc_ena;
0465     u8 tphdata_ena;
0466     u8 tphhead_ena;
0467     u16 lrxqthresh; /* bigger than needed, see above for reason */
0468     u8 prefena; /* NOTE: normally must be set to 1 at init */
0469 };
0470 
0471 struct ice_ctx_ele {
0472     u16 offset;
0473     u16 size_of;
0474     u16 width;
0475     u16 lsb;
0476 };
0477 
0478 #define ICE_CTX_STORE(_struct, _ele, _width, _lsb) {    \
0479     .offset = offsetof(struct _struct, _ele),   \
0480     .size_of = sizeof_field(struct _struct, _ele),  \
0481     .width = _width,                \
0482     .lsb = _lsb,                    \
0483 }
0484 
0485 /* for hsplit_0 field of Rx RLAN context */
0486 enum ice_rlan_ctx_rx_hsplit_0 {
0487     ICE_RLAN_RX_HSPLIT_0_NO_SPLIT       = 0,
0488     ICE_RLAN_RX_HSPLIT_0_SPLIT_L2       = 1,
0489     ICE_RLAN_RX_HSPLIT_0_SPLIT_IP       = 2,
0490     ICE_RLAN_RX_HSPLIT_0_SPLIT_TCP_UDP  = 4,
0491     ICE_RLAN_RX_HSPLIT_0_SPLIT_SCTP     = 8,
0492 };
0493 
0494 /* for hsplit_1 field of Rx RLAN context */
0495 enum ice_rlan_ctx_rx_hsplit_1 {
0496     ICE_RLAN_RX_HSPLIT_1_NO_SPLIT       = 0,
0497     ICE_RLAN_RX_HSPLIT_1_SPLIT_L2       = 1,
0498     ICE_RLAN_RX_HSPLIT_1_SPLIT_ALWAYS   = 2,
0499 };
0500 
0501 /* Tx Descriptor */
0502 struct ice_tx_desc {
0503     __le64 buf_addr; /* Address of descriptor's data buf */
0504     __le64 cmd_type_offset_bsz;
0505 };
0506 
0507 enum ice_tx_desc_dtype_value {
0508     ICE_TX_DESC_DTYPE_DATA      = 0x0,
0509     ICE_TX_DESC_DTYPE_CTX       = 0x1,
0510     ICE_TX_DESC_DTYPE_FLTR_PROG = 0x8,
0511     /* DESC_DONE - HW has completed write-back of descriptor */
0512     ICE_TX_DESC_DTYPE_DESC_DONE = 0xF,
0513 };
0514 
0515 #define ICE_TXD_QW1_CMD_S   4
0516 #define ICE_TXD_QW1_CMD_M   (0xFFFUL << ICE_TXD_QW1_CMD_S)
0517 
0518 enum ice_tx_desc_cmd_bits {
0519     ICE_TX_DESC_CMD_EOP         = 0x0001,
0520     ICE_TX_DESC_CMD_RS          = 0x0002,
0521     ICE_TX_DESC_CMD_IL2TAG1         = 0x0008,
0522     ICE_TX_DESC_CMD_DUMMY           = 0x0010,
0523     ICE_TX_DESC_CMD_IIPT_IPV6       = 0x0020,
0524     ICE_TX_DESC_CMD_IIPT_IPV4       = 0x0040,
0525     ICE_TX_DESC_CMD_IIPT_IPV4_CSUM      = 0x0060,
0526     ICE_TX_DESC_CMD_L4T_EOFT_TCP        = 0x0100,
0527     ICE_TX_DESC_CMD_L4T_EOFT_SCTP       = 0x0200,
0528     ICE_TX_DESC_CMD_L4T_EOFT_UDP        = 0x0300,
0529     ICE_TX_DESC_CMD_RE          = 0x0400,
0530 };
0531 
0532 #define ICE_TXD_QW1_OFFSET_S    16
0533 #define ICE_TXD_QW1_OFFSET_M    (0x3FFFFULL << ICE_TXD_QW1_OFFSET_S)
0534 
0535 enum ice_tx_desc_len_fields {
0536     /* Note: These are predefined bit offsets */
0537     ICE_TX_DESC_LEN_MACLEN_S    = 0, /* 7 BITS */
0538     ICE_TX_DESC_LEN_IPLEN_S = 7, /* 7 BITS */
0539     ICE_TX_DESC_LEN_L4_LEN_S    = 14 /* 4 BITS */
0540 };
0541 
0542 #define ICE_TXD_QW1_MACLEN_M (0x7FUL << ICE_TX_DESC_LEN_MACLEN_S)
0543 #define ICE_TXD_QW1_IPLEN_M  (0x7FUL << ICE_TX_DESC_LEN_IPLEN_S)
0544 #define ICE_TXD_QW1_L4LEN_M  (0xFUL << ICE_TX_DESC_LEN_L4_LEN_S)
0545 
0546 /* Tx descriptor field limits in bytes */
0547 #define ICE_TXD_MACLEN_MAX ((ICE_TXD_QW1_MACLEN_M >> \
0548                  ICE_TX_DESC_LEN_MACLEN_S) * ICE_BYTES_PER_WORD)
0549 #define ICE_TXD_IPLEN_MAX ((ICE_TXD_QW1_IPLEN_M >> \
0550                 ICE_TX_DESC_LEN_IPLEN_S) * ICE_BYTES_PER_DWORD)
0551 #define ICE_TXD_L4LEN_MAX ((ICE_TXD_QW1_L4LEN_M >> \
0552                 ICE_TX_DESC_LEN_L4_LEN_S) * ICE_BYTES_PER_DWORD)
0553 
0554 #define ICE_TXD_QW1_TX_BUF_SZ_S 34
0555 #define ICE_TXD_QW1_L2TAG1_S    48
0556 
0557 /* Context descriptors */
0558 struct ice_tx_ctx_desc {
0559     __le32 tunneling_params;
0560     __le16 l2tag2;
0561     __le16 rsvd;
0562     __le64 qw1;
0563 };
0564 
0565 #define ICE_TXD_CTX_QW1_CMD_S   4
0566 #define ICE_TXD_CTX_QW1_CMD_M   (0x7FUL << ICE_TXD_CTX_QW1_CMD_S)
0567 
0568 #define ICE_TXD_CTX_QW1_TSO_LEN_S   30
0569 #define ICE_TXD_CTX_QW1_TSO_LEN_M   \
0570             (0x3FFFFULL << ICE_TXD_CTX_QW1_TSO_LEN_S)
0571 
0572 #define ICE_TXD_CTX_QW1_MSS_S   50
0573 #define ICE_TXD_CTX_MIN_MSS 64
0574 
0575 #define ICE_TXD_CTX_QW1_VSI_S   50
0576 #define ICE_TXD_CTX_QW1_VSI_M   (0x3FFULL << ICE_TXD_CTX_QW1_VSI_S)
0577 
0578 enum ice_tx_ctx_desc_cmd_bits {
0579     ICE_TX_CTX_DESC_TSO     = 0x01,
0580     ICE_TX_CTX_DESC_TSYN        = 0x02,
0581     ICE_TX_CTX_DESC_IL2TAG2     = 0x04,
0582     ICE_TX_CTX_DESC_IL2TAG2_IL2H    = 0x08,
0583     ICE_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
0584     ICE_TX_CTX_DESC_SWTCH_UPLINK    = 0x10,
0585     ICE_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
0586     ICE_TX_CTX_DESC_SWTCH_VSI   = 0x30,
0587     ICE_TX_CTX_DESC_RESERVED    = 0x40
0588 };
0589 
0590 enum ice_tx_ctx_desc_eipt_offload {
0591     ICE_TX_CTX_EIPT_NONE        = 0x0,
0592     ICE_TX_CTX_EIPT_IPV6        = 0x1,
0593     ICE_TX_CTX_EIPT_IPV4_NO_CSUM    = 0x2,
0594     ICE_TX_CTX_EIPT_IPV4        = 0x3
0595 };
0596 
0597 #define ICE_TXD_CTX_QW0_EIPLEN_S    2
0598 
0599 #define ICE_TXD_CTX_QW0_L4TUNT_S    9
0600 
0601 #define ICE_TXD_CTX_UDP_TUNNELING   BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S)
0602 #define ICE_TXD_CTX_GRE_TUNNELING   (0x2ULL << ICE_TXD_CTX_QW0_L4TUNT_S)
0603 
0604 #define ICE_TXD_CTX_QW0_NATLEN_S    12
0605 
0606 #define ICE_TXD_CTX_QW0_L4T_CS_S    23
0607 #define ICE_TXD_CTX_QW0_L4T_CS_M    BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
0608 
0609 #define ICE_LAN_TXQ_MAX_QGRPS   127
0610 #define ICE_LAN_TXQ_MAX_QDIS    1023
0611 
0612 /* Tx queue context data
0613  *
0614  * The sizes of the variables may be larger than needed due to crossing byte
0615  * boundaries. If we do not have the width of the variable set to the correct
0616  * size then we could end up shifting bits off the top of the variable when the
0617  * variable is at the top of a byte and crosses over into the next byte.
0618  */
0619 struct ice_tlan_ctx {
0620 #define ICE_TLAN_CTX_BASE_S 7
0621     u64 base;       /* base is defined in 128-byte units */
0622     u8 port_num;
0623     u16 cgd_num;        /* bigger than needed, see above for reason */
0624     u8 pf_num;
0625     u16 vmvf_num;
0626     u8 vmvf_type;
0627 #define ICE_TLAN_CTX_VMVF_TYPE_VF   0
0628 #define ICE_TLAN_CTX_VMVF_TYPE_VMQ  1
0629 #define ICE_TLAN_CTX_VMVF_TYPE_PF   2
0630     u16 src_vsi;
0631     u8 tsyn_ena;
0632     u8 internal_usage_flag;
0633     u8 alt_vlan;
0634     u16 cpuid;      /* bigger than needed, see above for reason */
0635     u8 wb_mode;
0636     u8 tphrd_desc;
0637     u8 tphrd;
0638     u8 tphwr_desc;
0639     u16 cmpq_id;
0640     u16 qnum_in_func;
0641     u8 itr_notification_mode;
0642     u8 adjust_prof_id;
0643     u32 qlen;       /* bigger than needed, see above for reason */
0644     u8 quanta_prof_idx;
0645     u8 tso_ena;
0646     u16 tso_qnum;
0647     u8 legacy_int;
0648     u8 drop_ena;
0649     u8 cache_prof_idx;
0650     u8 pkt_shaper_prof_idx;
0651     u8 int_q_state; /* width not needed - internal - DO NOT WRITE!!! */
0652 };
0653 
0654 /* The ice_ptype_lkup table is used to convert from the 10-bit ptype in the
0655  * hardware to a bit-field that can be used by SW to more easily determine the
0656  * packet type.
0657  *
0658  * Macros are used to shorten the table lines and make this table human
0659  * readable.
0660  *
0661  * We store the PTYPE in the top byte of the bit field - this is just so that
0662  * we can check that the table doesn't have a row missing, as the index into
0663  * the table should be the PTYPE.
0664  *
0665  * Typical work flow:
0666  *
0667  * IF NOT ice_ptype_lkup[ptype].known
0668  * THEN
0669  *      Packet is unknown
0670  * ELSE IF ice_ptype_lkup[ptype].outer_ip == ICE_RX_PTYPE_OUTER_IP
0671  *      Use the rest of the fields to look at the tunnels, inner protocols, etc
0672  * ELSE
0673  *      Use the enum ice_rx_l2_ptype to decode the packet type
0674  * ENDIF
0675  */
0676 
0677 /* macro to make the table lines short, use explicit indexing with [PTYPE] */
0678 #define ICE_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
0679     [PTYPE] = { \
0680         1, \
0681         ICE_RX_PTYPE_OUTER_##OUTER_IP, \
0682         ICE_RX_PTYPE_OUTER_##OUTER_IP_VER, \
0683         ICE_RX_PTYPE_##OUTER_FRAG, \
0684         ICE_RX_PTYPE_TUNNEL_##T, \
0685         ICE_RX_PTYPE_TUNNEL_END_##TE, \
0686         ICE_RX_PTYPE_##TEF, \
0687         ICE_RX_PTYPE_INNER_PROT_##I, \
0688         ICE_RX_PTYPE_PAYLOAD_LAYER_##PL }
0689 
0690 #define ICE_PTT_UNUSED_ENTRY(PTYPE) [PTYPE] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0691 
0692 /* shorter macros makes the table fit but are terse */
0693 #define ICE_RX_PTYPE_NOF        ICE_RX_PTYPE_NOT_FRAG
0694 #define ICE_RX_PTYPE_FRG        ICE_RX_PTYPE_FRAG
0695 
0696 /* Lookup table mapping in the 10-bit HW PTYPE to the bit field for decoding */
0697 static const struct ice_rx_ptype_decoded ice_ptype_lkup[BIT(10)] = {
0698     /* L2 Packet types */
0699     ICE_PTT_UNUSED_ENTRY(0),
0700     ICE_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
0701     ICE_PTT_UNUSED_ENTRY(2),
0702     ICE_PTT_UNUSED_ENTRY(3),
0703     ICE_PTT_UNUSED_ENTRY(4),
0704     ICE_PTT_UNUSED_ENTRY(5),
0705     ICE_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
0706     ICE_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
0707     ICE_PTT_UNUSED_ENTRY(8),
0708     ICE_PTT_UNUSED_ENTRY(9),
0709     ICE_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
0710     ICE_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
0711     ICE_PTT_UNUSED_ENTRY(12),
0712     ICE_PTT_UNUSED_ENTRY(13),
0713     ICE_PTT_UNUSED_ENTRY(14),
0714     ICE_PTT_UNUSED_ENTRY(15),
0715     ICE_PTT_UNUSED_ENTRY(16),
0716     ICE_PTT_UNUSED_ENTRY(17),
0717     ICE_PTT_UNUSED_ENTRY(18),
0718     ICE_PTT_UNUSED_ENTRY(19),
0719     ICE_PTT_UNUSED_ENTRY(20),
0720     ICE_PTT_UNUSED_ENTRY(21),
0721 
0722     /* Non Tunneled IPv4 */
0723     ICE_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
0724     ICE_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
0725     ICE_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP,  PAY4),
0726     ICE_PTT_UNUSED_ENTRY(25),
0727     ICE_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP,  PAY4),
0728     ICE_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
0729     ICE_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
0730 
0731     /* IPv4 --> IPv4 */
0732     ICE_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
0733     ICE_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
0734     ICE_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
0735     ICE_PTT_UNUSED_ENTRY(32),
0736     ICE_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
0737     ICE_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
0738     ICE_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
0739 
0740     /* IPv4 --> IPv6 */
0741     ICE_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
0742     ICE_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
0743     ICE_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
0744     ICE_PTT_UNUSED_ENTRY(39),
0745     ICE_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
0746     ICE_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
0747     ICE_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
0748 
0749     /* IPv4 --> GRE/NAT */
0750     ICE_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
0751 
0752     /* IPv4 --> GRE/NAT --> IPv4 */
0753     ICE_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
0754     ICE_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
0755     ICE_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
0756     ICE_PTT_UNUSED_ENTRY(47),
0757     ICE_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
0758     ICE_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
0759     ICE_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
0760 
0761     /* IPv4 --> GRE/NAT --> IPv6 */
0762     ICE_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
0763     ICE_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
0764     ICE_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
0765     ICE_PTT_UNUSED_ENTRY(54),
0766     ICE_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
0767     ICE_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
0768     ICE_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
0769 
0770     /* IPv4 --> GRE/NAT --> MAC */
0771     ICE_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
0772 
0773     /* IPv4 --> GRE/NAT --> MAC --> IPv4 */
0774     ICE_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
0775     ICE_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
0776     ICE_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
0777     ICE_PTT_UNUSED_ENTRY(62),
0778     ICE_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
0779     ICE_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
0780     ICE_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
0781 
0782     /* IPv4 --> GRE/NAT -> MAC --> IPv6 */
0783     ICE_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
0784     ICE_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
0785     ICE_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
0786     ICE_PTT_UNUSED_ENTRY(69),
0787     ICE_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
0788     ICE_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
0789     ICE_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
0790 
0791     /* IPv4 --> GRE/NAT --> MAC/VLAN */
0792     ICE_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
0793 
0794     /* IPv4 ---> GRE/NAT -> MAC/VLAN --> IPv4 */
0795     ICE_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
0796     ICE_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
0797     ICE_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
0798     ICE_PTT_UNUSED_ENTRY(77),
0799     ICE_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
0800     ICE_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
0801     ICE_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
0802 
0803     /* IPv4 -> GRE/NAT -> MAC/VLAN --> IPv6 */
0804     ICE_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
0805     ICE_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
0806     ICE_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
0807     ICE_PTT_UNUSED_ENTRY(84),
0808     ICE_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
0809     ICE_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
0810     ICE_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
0811 
0812     /* Non Tunneled IPv6 */
0813     ICE_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
0814     ICE_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
0815     ICE_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP,  PAY4),
0816     ICE_PTT_UNUSED_ENTRY(91),
0817     ICE_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP,  PAY4),
0818     ICE_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
0819     ICE_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
0820 
0821     /* IPv6 --> IPv4 */
0822     ICE_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
0823     ICE_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
0824     ICE_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP,  PAY4),
0825     ICE_PTT_UNUSED_ENTRY(98),
0826     ICE_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP,  PAY4),
0827     ICE_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
0828     ICE_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
0829 
0830     /* IPv6 --> IPv6 */
0831     ICE_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
0832     ICE_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
0833     ICE_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP,  PAY4),
0834     ICE_PTT_UNUSED_ENTRY(105),
0835     ICE_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP,  PAY4),
0836     ICE_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
0837     ICE_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
0838 
0839     /* IPv6 --> GRE/NAT */
0840     ICE_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
0841 
0842     /* IPv6 --> GRE/NAT -> IPv4 */
0843     ICE_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
0844     ICE_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
0845     ICE_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP,  PAY4),
0846     ICE_PTT_UNUSED_ENTRY(113),
0847     ICE_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP,  PAY4),
0848     ICE_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
0849     ICE_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
0850 
0851     /* IPv6 --> GRE/NAT -> IPv6 */
0852     ICE_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
0853     ICE_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
0854     ICE_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP,  PAY4),
0855     ICE_PTT_UNUSED_ENTRY(120),
0856     ICE_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP,  PAY4),
0857     ICE_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
0858     ICE_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
0859 
0860     /* IPv6 --> GRE/NAT -> MAC */
0861     ICE_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
0862 
0863     /* IPv6 --> GRE/NAT -> MAC -> IPv4 */
0864     ICE_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
0865     ICE_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
0866     ICE_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP,  PAY4),
0867     ICE_PTT_UNUSED_ENTRY(128),
0868     ICE_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP,  PAY4),
0869     ICE_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
0870     ICE_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
0871 
0872     /* IPv6 --> GRE/NAT -> MAC -> IPv6 */
0873     ICE_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
0874     ICE_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
0875     ICE_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP,  PAY4),
0876     ICE_PTT_UNUSED_ENTRY(135),
0877     ICE_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP,  PAY4),
0878     ICE_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
0879     ICE_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
0880 
0881     /* IPv6 --> GRE/NAT -> MAC/VLAN */
0882     ICE_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
0883 
0884     /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv4 */
0885     ICE_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
0886     ICE_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
0887     ICE_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP,  PAY4),
0888     ICE_PTT_UNUSED_ENTRY(143),
0889     ICE_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP,  PAY4),
0890     ICE_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
0891     ICE_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
0892 
0893     /* IPv6 --> GRE/NAT -> MAC/VLAN --> IPv6 */
0894     ICE_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
0895     ICE_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
0896     ICE_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP,  PAY4),
0897     ICE_PTT_UNUSED_ENTRY(150),
0898     ICE_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP,  PAY4),
0899     ICE_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
0900     ICE_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
0901 
0902     /* unused entries */
0903     [154 ... 1023] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
0904 };
0905 
0906 static inline struct ice_rx_ptype_decoded ice_decode_rx_desc_ptype(u16 ptype)
0907 {
0908     return ice_ptype_lkup[ptype];
0909 }
0910 
0911 #define ICE_LINK_SPEED_UNKNOWN      0
0912 #define ICE_LINK_SPEED_10MBPS       10
0913 #define ICE_LINK_SPEED_100MBPS      100
0914 #define ICE_LINK_SPEED_1000MBPS     1000
0915 #define ICE_LINK_SPEED_2500MBPS     2500
0916 #define ICE_LINK_SPEED_5000MBPS     5000
0917 #define ICE_LINK_SPEED_10000MBPS    10000
0918 #define ICE_LINK_SPEED_20000MBPS    20000
0919 #define ICE_LINK_SPEED_25000MBPS    25000
0920 #define ICE_LINK_SPEED_40000MBPS    40000
0921 #define ICE_LINK_SPEED_50000MBPS    50000
0922 #define ICE_LINK_SPEED_100000MBPS   100000
0923 
0924 #endif /* _ICE_LAN_TX_RX_H_ */
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