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0006 #ifndef _ICE_HW_AUTOGEN_H_
0007 #define _ICE_HW_AUTOGEN_H_
0008
0009 #define QTX_COMM_DBELL(_DBQM) (0x002C0000 + ((_DBQM) * 4))
0010 #define QTX_COMM_HEAD(_DBQM) (0x000E0000 + ((_DBQM) * 4))
0011 #define QTX_COMM_HEAD_HEAD_S 0
0012 #define QTX_COMM_HEAD_HEAD_M ICE_M(0x1FFF, 0)
0013 #define PF_FW_ARQBAH 0x00080180
0014 #define PF_FW_ARQBAL 0x00080080
0015 #define PF_FW_ARQH 0x00080380
0016 #define PF_FW_ARQH_ARQH_M ICE_M(0x3FF, 0)
0017 #define PF_FW_ARQLEN 0x00080280
0018 #define PF_FW_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
0019 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
0020 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
0021 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
0022 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
0023 #define PF_FW_ARQT 0x00080480
0024 #define PF_FW_ATQBAH 0x00080100
0025 #define PF_FW_ATQBAL 0x00080000
0026 #define PF_FW_ATQH 0x00080300
0027 #define PF_FW_ATQH_ATQH_M ICE_M(0x3FF, 0)
0028 #define PF_FW_ATQLEN 0x00080200
0029 #define PF_FW_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
0030 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
0031 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
0032 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
0033 #define VF_MBX_ARQLEN(_VF) (0x0022BC00 + ((_VF) * 4))
0034 #define VF_MBX_ATQLEN(_VF) (0x0022A800 + ((_VF) * 4))
0035 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
0036 #define PF_FW_ATQT 0x00080400
0037 #define PF_MBX_ARQBAH 0x0022E400
0038 #define PF_MBX_ARQBAL 0x0022E380
0039 #define PF_MBX_ARQH 0x0022E500
0040 #define PF_MBX_ARQH_ARQH_M ICE_M(0x3FF, 0)
0041 #define PF_MBX_ARQLEN 0x0022E480
0042 #define PF_MBX_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
0043 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
0044 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
0045 #define PF_MBX_ARQT 0x0022E580
0046 #define PF_MBX_ATQBAH 0x0022E180
0047 #define PF_MBX_ATQBAL 0x0022E100
0048 #define PF_MBX_ATQH 0x0022E280
0049 #define PF_MBX_ATQH_ATQH_M ICE_M(0x3FF, 0)
0050 #define PF_MBX_ATQLEN 0x0022E200
0051 #define PF_MBX_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
0052 #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30)
0053 #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31)
0054 #define PF_MBX_ATQT 0x0022E300
0055 #define PF_SB_ARQBAH 0x0022FF00
0056 #define PF_SB_ARQBAH_ARQBAH_S 0
0057 #define PF_SB_ARQBAH_ARQBAH_M ICE_M(0xFFFFFFFF, 0)
0058 #define PF_SB_ARQBAL 0x0022FE80
0059 #define PF_SB_ARQBAL_ARQBAL_LSB_S 0
0060 #define PF_SB_ARQBAL_ARQBAL_LSB_M ICE_M(0x3F, 0)
0061 #define PF_SB_ARQBAL_ARQBAL_S 6
0062 #define PF_SB_ARQBAL_ARQBAL_M ICE_M(0x3FFFFFF, 6)
0063 #define PF_SB_ARQH 0x00230000
0064 #define PF_SB_ARQH_ARQH_S 0
0065 #define PF_SB_ARQH_ARQH_M ICE_M(0x3FF, 0)
0066 #define PF_SB_ARQLEN 0x0022FF80
0067 #define PF_SB_ARQLEN_ARQLEN_S 0
0068 #define PF_SB_ARQLEN_ARQLEN_M ICE_M(0x3FF, 0)
0069 #define PF_SB_ARQLEN_ARQVFE_S 28
0070 #define PF_SB_ARQLEN_ARQVFE_M BIT(28)
0071 #define PF_SB_ARQLEN_ARQOVFL_S 29
0072 #define PF_SB_ARQLEN_ARQOVFL_M BIT(29)
0073 #define PF_SB_ARQLEN_ARQCRIT_S 30
0074 #define PF_SB_ARQLEN_ARQCRIT_M BIT(30)
0075 #define PF_SB_ARQLEN_ARQENABLE_S 31
0076 #define PF_SB_ARQLEN_ARQENABLE_M BIT(31)
0077 #define PF_SB_ARQT 0x00230080
0078 #define PF_SB_ARQT_ARQT_S 0
0079 #define PF_SB_ARQT_ARQT_M ICE_M(0x3FF, 0)
0080 #define PF_SB_ATQBAH 0x0022FC80
0081 #define PF_SB_ATQBAH_ATQBAH_S 0
0082 #define PF_SB_ATQBAH_ATQBAH_M ICE_M(0xFFFFFFFF, 0)
0083 #define PF_SB_ATQBAL 0x0022FC00
0084 #define PF_SB_ATQBAL_ATQBAL_S 6
0085 #define PF_SB_ATQBAL_ATQBAL_M ICE_M(0x3FFFFFF, 6)
0086 #define PF_SB_ATQH 0x0022FD80
0087 #define PF_SB_ATQH_ATQH_S 0
0088 #define PF_SB_ATQH_ATQH_M ICE_M(0x3FF, 0)
0089 #define PF_SB_ATQLEN 0x0022FD00
0090 #define PF_SB_ATQLEN_ATQLEN_S 0
0091 #define PF_SB_ATQLEN_ATQLEN_M ICE_M(0x3FF, 0)
0092 #define PF_SB_ATQLEN_ATQVFE_S 28
0093 #define PF_SB_ATQLEN_ATQVFE_M BIT(28)
0094 #define PF_SB_ATQLEN_ATQOVFL_S 29
0095 #define PF_SB_ATQLEN_ATQOVFL_M BIT(29)
0096 #define PF_SB_ATQLEN_ATQCRIT_S 30
0097 #define PF_SB_ATQLEN_ATQCRIT_M BIT(30)
0098 #define PF_SB_ATQLEN_ATQENABLE_S 31
0099 #define PF_SB_ATQLEN_ATQENABLE_M BIT(31)
0100 #define PF_SB_ATQT 0x0022FE00
0101 #define PF_SB_ATQT_ATQT_S 0
0102 #define PF_SB_ATQT_ATQT_M ICE_M(0x3FF, 0)
0103 #define PF_SB_REM_DEV_CTL 0x002300F0
0104 #define PRTDCB_GENC 0x00083000
0105 #define PRTDCB_GENC_PFCLDA_S 16
0106 #define PRTDCB_GENC_PFCLDA_M ICE_M(0xFFFF, 16)
0107 #define PRTDCB_GENS 0x00083020
0108 #define PRTDCB_GENS_DCBX_STATUS_S 0
0109 #define PRTDCB_GENS_DCBX_STATUS_M ICE_M(0x7, 0)
0110 #define PRTDCB_TUP2TC 0x001D26C0
0111 #define GL_PREEXT_L2_PMASK0(_i) (0x0020F0FC + ((_i) * 4))
0112 #define GL_PREEXT_L2_PMASK1(_i) (0x0020F108 + ((_i) * 4))
0113 #define GLFLXP_RXDID_FLX_WRD_0(_i) (0x0045c800 + ((_i) * 4))
0114 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_S 0
0115 #define GLFLXP_RXDID_FLX_WRD_0_PROT_MDID_M ICE_M(0xFF, 0)
0116 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
0117 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30)
0118 #define GLFLXP_RXDID_FLX_WRD_1(_i) (0x0045c900 + ((_i) * 4))
0119 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_S 0
0120 #define GLFLXP_RXDID_FLX_WRD_1_PROT_MDID_M ICE_M(0xFF, 0)
0121 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
0122 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30)
0123 #define GLFLXP_RXDID_FLX_WRD_2(_i) (0x0045ca00 + ((_i) * 4))
0124 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_S 0
0125 #define GLFLXP_RXDID_FLX_WRD_2_PROT_MDID_M ICE_M(0xFF, 0)
0126 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
0127 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30)
0128 #define GLFLXP_RXDID_FLX_WRD_3(_i) (0x0045cb00 + ((_i) * 4))
0129 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_S 0
0130 #define GLFLXP_RXDID_FLX_WRD_3_PROT_MDID_M ICE_M(0xFF, 0)
0131 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
0132 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30)
0133 #define QRXFLXP_CNTXT(_QRX) (0x00480000 + ((_QRX) * 4))
0134 #define QRXFLXP_CNTXT_RXDID_IDX_S 0
0135 #define QRXFLXP_CNTXT_RXDID_IDX_M ICE_M(0x3F, 0)
0136 #define QRXFLXP_CNTXT_RXDID_PRIO_S 8
0137 #define QRXFLXP_CNTXT_RXDID_PRIO_M ICE_M(0x7, 8)
0138 #define QRXFLXP_CNTXT_TS_M BIT(11)
0139 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_S 4
0140 #define GLGEN_CLKSTAT_SRC_PSM_CLK_SRC_M ICE_M(0x3, 4)
0141 #define GLGEN_CLKSTAT_SRC 0x000B826C
0142 #define GLGEN_GPIO_CTL(_i) (0x000880C8 + ((_i) * 4))
0143 #define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4)
0144 #define GLGEN_GPIO_CTL_PIN_FUNC_S 8
0145 #define GLGEN_GPIO_CTL_PIN_FUNC_M ICE_M(0xF, 8)
0146 #define GLGEN_RSTAT 0x000B8188
0147 #define GLGEN_RSTAT_DEVSTATE_M ICE_M(0x3, 0)
0148 #define GLGEN_RSTCTL 0x000B8180
0149 #define GLGEN_RSTCTL_GRSTDEL_S 0
0150 #define GLGEN_RSTCTL_GRSTDEL_M ICE_M(0x3F, GLGEN_RSTCTL_GRSTDEL_S)
0151 #define GLGEN_RSTAT_RESET_TYPE_S 2
0152 #define GLGEN_RSTAT_RESET_TYPE_M ICE_M(0x3, 2)
0153 #define GLGEN_RTRIG 0x000B8190
0154 #define GLGEN_RTRIG_CORER_M BIT(0)
0155 #define GLGEN_RTRIG_GLOBR_M BIT(1)
0156 #define GLGEN_STAT 0x000B612C
0157 #define GLGEN_VFLRSTAT(_i) (0x00093A04 + ((_i) * 4))
0158 #define PFGEN_CTRL 0x00091000
0159 #define PFGEN_CTRL_PFSWR_M BIT(0)
0160 #define PFGEN_STATE 0x00088000
0161 #define PRTGEN_STATUS 0x000B8100
0162 #define VFGEN_RSTAT(_VF) (0x00074000 + ((_VF) * 4))
0163 #define VPGEN_VFRSTAT(_VF) (0x00090800 + ((_VF) * 4))
0164 #define VPGEN_VFRSTAT_VFRD_M BIT(0)
0165 #define VPGEN_VFRTRIG(_VF) (0x00090000 + ((_VF) * 4))
0166 #define VPGEN_VFRTRIG_VFSWR_M BIT(0)
0167 #define GLINT_CTL 0x0016CC54
0168 #define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
0169 #define GLINT_CTL_ITR_GRAN_200_S 16
0170 #define GLINT_CTL_ITR_GRAN_200_M ICE_M(0xF, 16)
0171 #define GLINT_CTL_ITR_GRAN_100_S 20
0172 #define GLINT_CTL_ITR_GRAN_100_M ICE_M(0xF, 20)
0173 #define GLINT_CTL_ITR_GRAN_50_S 24
0174 #define GLINT_CTL_ITR_GRAN_50_M ICE_M(0xF, 24)
0175 #define GLINT_CTL_ITR_GRAN_25_S 28
0176 #define GLINT_CTL_ITR_GRAN_25_M ICE_M(0xF, 28)
0177 #define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4))
0178 #define GLINT_DYN_CTL_INTENA_M BIT(0)
0179 #define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
0180 #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2)
0181 #define GLINT_DYN_CTL_ITR_INDX_S 3
0182 #define GLINT_DYN_CTL_ITR_INDX_M ICE_M(0x3, 3)
0183 #define GLINT_DYN_CTL_INTERVAL_S 5
0184 #define GLINT_DYN_CTL_INTERVAL_M ICE_M(0xFFF, 5)
0185 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
0186 #define GLINT_DYN_CTL_SW_ITR_INDX_S 25
0187 #define GLINT_DYN_CTL_SW_ITR_INDX_M ICE_M(0x3, 25)
0188 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
0189 #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31)
0190 #define GLINT_ITR(_i, _INT) (0x00154000 + ((_i) * 8192 + (_INT) * 4))
0191 #define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4))
0192 #define GLINT_RATE_INTRL_ENA_M BIT(6)
0193 #define GLINT_VECT2FUNC(_INT) (0x00162000 + ((_INT) * 4))
0194 #define GLINT_VECT2FUNC_VF_NUM_S 0
0195 #define GLINT_VECT2FUNC_VF_NUM_M ICE_M(0xFF, 0)
0196 #define GLINT_VECT2FUNC_PF_NUM_S 12
0197 #define GLINT_VECT2FUNC_PF_NUM_M ICE_M(0x7, 12)
0198 #define GLINT_VECT2FUNC_IS_PF_S 16
0199 #define GLINT_VECT2FUNC_IS_PF_M BIT(16)
0200 #define PFINT_FW_CTL 0x0016C800
0201 #define PFINT_FW_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
0202 #define PFINT_FW_CTL_ITR_INDX_S 11
0203 #define PFINT_FW_CTL_ITR_INDX_M ICE_M(0x3, 11)
0204 #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
0205 #define PFINT_MBX_CTL 0x0016B280
0206 #define PFINT_MBX_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
0207 #define PFINT_MBX_CTL_ITR_INDX_S 11
0208 #define PFINT_MBX_CTL_ITR_INDX_M ICE_M(0x3, 11)
0209 #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
0210 #define PFINT_OICR 0x0016CA00
0211 #define PFINT_OICR_TSYN_TX_M BIT(11)
0212 #define PFINT_OICR_TSYN_EVNT_M BIT(12)
0213 #define PFINT_OICR_ECC_ERR_M BIT(16)
0214 #define PFINT_OICR_MAL_DETECT_M BIT(19)
0215 #define PFINT_OICR_GRST_M BIT(20)
0216 #define PFINT_OICR_PCI_EXCEPTION_M BIT(21)
0217 #define PFINT_OICR_HMC_ERR_M BIT(26)
0218 #define PFINT_OICR_PE_PUSH_M BIT(27)
0219 #define PFINT_OICR_PE_CRITERR_M BIT(28)
0220 #define PFINT_OICR_VFLR_M BIT(29)
0221 #define PFINT_OICR_SWINT_M BIT(31)
0222 #define PFINT_OICR_CTL 0x0016CA80
0223 #define PFINT_OICR_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
0224 #define PFINT_OICR_CTL_ITR_INDX_S 11
0225 #define PFINT_OICR_CTL_ITR_INDX_M ICE_M(0x3, 11)
0226 #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
0227 #define PFINT_OICR_ENA 0x0016C900
0228 #define PFINT_SB_CTL 0x0016B600
0229 #define PFINT_SB_CTL_MSIX_INDX_M ICE_M(0x7FF, 0)
0230 #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30)
0231 #define QINT_RQCTL(_QRX) (0x00150000 + ((_QRX) * 4))
0232 #define QINT_RQCTL_MSIX_INDX_S 0
0233 #define QINT_RQCTL_MSIX_INDX_M ICE_M(0x7FF, 0)
0234 #define QINT_RQCTL_ITR_INDX_S 11
0235 #define QINT_RQCTL_ITR_INDX_M ICE_M(0x3, 11)
0236 #define QINT_RQCTL_CAUSE_ENA_M BIT(30)
0237 #define QINT_TQCTL(_DBQM) (0x00140000 + ((_DBQM) * 4))
0238 #define QINT_TQCTL_MSIX_INDX_S 0
0239 #define QINT_TQCTL_MSIX_INDX_M ICE_M(0x7FF, 0)
0240 #define QINT_TQCTL_ITR_INDX_S 11
0241 #define QINT_TQCTL_ITR_INDX_M ICE_M(0x3, 11)
0242 #define QINT_TQCTL_CAUSE_ENA_M BIT(30)
0243 #define VPINT_ALLOC(_VF) (0x001D1000 + ((_VF) * 4))
0244 #define VPINT_ALLOC_FIRST_S 0
0245 #define VPINT_ALLOC_FIRST_M ICE_M(0x7FF, 0)
0246 #define VPINT_ALLOC_LAST_S 12
0247 #define VPINT_ALLOC_LAST_M ICE_M(0x7FF, 12)
0248 #define VPINT_ALLOC_VALID_M BIT(31)
0249 #define VPINT_ALLOC_PCI(_VF) (0x0009D000 + ((_VF) * 4))
0250 #define VPINT_ALLOC_PCI_FIRST_S 0
0251 #define VPINT_ALLOC_PCI_FIRST_M ICE_M(0x7FF, 0)
0252 #define VPINT_ALLOC_PCI_LAST_S 12
0253 #define VPINT_ALLOC_PCI_LAST_M ICE_M(0x7FF, 12)
0254 #define VPINT_ALLOC_PCI_VALID_M BIT(31)
0255 #define VPINT_MBX_CTL(_VSI) (0x0016A000 + ((_VSI) * 4))
0256 #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
0257 #define GLLAN_RCTL_0 0x002941F8
0258 #define QRX_CONTEXT(_i, _QRX) (0x00280000 + ((_i) * 8192 + (_QRX) * 4))
0259 #define QRX_CTRL(_QRX) (0x00120000 + ((_QRX) * 4))
0260 #define QRX_CTRL_MAX_INDEX 2047
0261 #define QRX_CTRL_QENA_REQ_S 0
0262 #define QRX_CTRL_QENA_REQ_M BIT(0)
0263 #define QRX_CTRL_QENA_STAT_S 2
0264 #define QRX_CTRL_QENA_STAT_M BIT(2)
0265 #define QRX_ITR(_QRX) (0x00292000 + ((_QRX) * 4))
0266 #define QRX_TAIL(_QRX) (0x00290000 + ((_QRX) * 4))
0267 #define QRX_TAIL_MAX_INDEX 2047
0268 #define QRX_TAIL_TAIL_S 0
0269 #define QRX_TAIL_TAIL_M ICE_M(0x1FFF, 0)
0270 #define VPLAN_RX_QBASE(_VF) (0x00072000 + ((_VF) * 4))
0271 #define VPLAN_RX_QBASE_VFFIRSTQ_S 0
0272 #define VPLAN_RX_QBASE_VFFIRSTQ_M ICE_M(0x7FF, 0)
0273 #define VPLAN_RX_QBASE_VFNUMQ_S 16
0274 #define VPLAN_RX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
0275 #define VPLAN_RXQ_MAPENA(_VF) (0x00073000 + ((_VF) * 4))
0276 #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
0277 #define VPLAN_TX_QBASE(_VF) (0x001D1800 + ((_VF) * 4))
0278 #define VPLAN_TX_QBASE_VFFIRSTQ_S 0
0279 #define VPLAN_TX_QBASE_VFFIRSTQ_M ICE_M(0x3FFF, 0)
0280 #define VPLAN_TX_QBASE_VFNUMQ_S 16
0281 #define VPLAN_TX_QBASE_VFNUMQ_M ICE_M(0xFF, 16)
0282 #define VPLAN_TXQ_MAPENA(_VF) (0x00073800 + ((_VF) * 4))
0283 #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
0284 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(_i) (0x001E36E0 + ((_i) * 32))
0285 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_MAX_INDEX 8
0286 #define PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA_HSEC_CTL_TX_PAUSE_QUANTA_M ICE_M(0xFFFF, 0)
0287 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(_i) (0x001E3800 + ((_i) * 32))
0288 #define PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER_M ICE_M(0xFFFF, 0)
0289 #define GL_MDCK_TX_TDPU 0x00049348
0290 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
0291 #define GL_MDET_RX 0x00294C00
0292 #define GL_MDET_RX_QNUM_S 0
0293 #define GL_MDET_RX_QNUM_M ICE_M(0x7FFF, 0)
0294 #define GL_MDET_RX_VF_NUM_S 15
0295 #define GL_MDET_RX_VF_NUM_M ICE_M(0xFF, 15)
0296 #define GL_MDET_RX_PF_NUM_S 23
0297 #define GL_MDET_RX_PF_NUM_M ICE_M(0x7, 23)
0298 #define GL_MDET_RX_MAL_TYPE_S 26
0299 #define GL_MDET_RX_MAL_TYPE_M ICE_M(0x1F, 26)
0300 #define GL_MDET_RX_VALID_M BIT(31)
0301 #define GL_MDET_TX_PQM 0x002D2E00
0302 #define GL_MDET_TX_PQM_PF_NUM_S 0
0303 #define GL_MDET_TX_PQM_PF_NUM_M ICE_M(0x7, 0)
0304 #define GL_MDET_TX_PQM_VF_NUM_S 4
0305 #define GL_MDET_TX_PQM_VF_NUM_M ICE_M(0xFF, 4)
0306 #define GL_MDET_TX_PQM_QNUM_S 12
0307 #define GL_MDET_TX_PQM_QNUM_M ICE_M(0x3FFF, 12)
0308 #define GL_MDET_TX_PQM_MAL_TYPE_S 26
0309 #define GL_MDET_TX_PQM_MAL_TYPE_M ICE_M(0x1F, 26)
0310 #define GL_MDET_TX_PQM_VALID_M BIT(31)
0311 #define GL_MDET_TX_TCLAN 0x000FC068
0312 #define GL_MDET_TX_TCLAN_QNUM_S 0
0313 #define GL_MDET_TX_TCLAN_QNUM_M ICE_M(0x7FFF, 0)
0314 #define GL_MDET_TX_TCLAN_VF_NUM_S 15
0315 #define GL_MDET_TX_TCLAN_VF_NUM_M ICE_M(0xFF, 15)
0316 #define GL_MDET_TX_TCLAN_PF_NUM_S 23
0317 #define GL_MDET_TX_TCLAN_PF_NUM_M ICE_M(0x7, 23)
0318 #define GL_MDET_TX_TCLAN_MAL_TYPE_S 26
0319 #define GL_MDET_TX_TCLAN_MAL_TYPE_M ICE_M(0x1F, 26)
0320 #define GL_MDET_TX_TCLAN_VALID_M BIT(31)
0321 #define PF_MDET_RX 0x00294280
0322 #define PF_MDET_RX_VALID_M BIT(0)
0323 #define PF_MDET_TX_PQM 0x002D2C80
0324 #define PF_MDET_TX_PQM_VALID_M BIT(0)
0325 #define PF_MDET_TX_TCLAN 0x000FC000
0326 #define PF_MDET_TX_TCLAN_VALID_M BIT(0)
0327 #define VP_MDET_RX(_VF) (0x00294400 + ((_VF) * 4))
0328 #define VP_MDET_RX_VALID_M BIT(0)
0329 #define VP_MDET_TX_PQM(_VF) (0x002D2000 + ((_VF) * 4))
0330 #define VP_MDET_TX_PQM_VALID_M BIT(0)
0331 #define VP_MDET_TX_TCLAN(_VF) (0x000FB800 + ((_VF) * 4))
0332 #define VP_MDET_TX_TCLAN_VALID_M BIT(0)
0333 #define VP_MDET_TX_TDPU(_VF) (0x00040000 + ((_VF) * 4))
0334 #define VP_MDET_TX_TDPU_VALID_M BIT(0)
0335 #define GLNVM_FLA 0x000B6108
0336 #define GLNVM_FLA_LOCKED_M BIT(6)
0337 #define GLNVM_GENS 0x000B6100
0338 #define GLNVM_GENS_SR_SIZE_S 5
0339 #define GLNVM_GENS_SR_SIZE_M ICE_M(0x7, 5)
0340 #define GLNVM_ULD 0x000B6008
0341 #define GLNVM_ULD_PCIER_DONE_M BIT(0)
0342 #define GLNVM_ULD_PCIER_DONE_1_M BIT(1)
0343 #define GLNVM_ULD_CORER_DONE_M BIT(3)
0344 #define GLNVM_ULD_GLOBR_DONE_M BIT(4)
0345 #define GLNVM_ULD_POR_DONE_M BIT(5)
0346 #define GLNVM_ULD_POR_DONE_1_M BIT(8)
0347 #define GLNVM_ULD_PCIER_DONE_2_M BIT(9)
0348 #define GLNVM_ULD_PE_DONE_M BIT(10)
0349 #define GLPCI_CNF2 0x000BE004
0350 #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1)
0351 #define PF_FUNC_RID 0x0009E880
0352 #define PF_FUNC_RID_FUNC_NUM_S 0
0353 #define PF_FUNC_RID_FUNC_NUM_M ICE_M(0x7, 0)
0354 #define PF_PCI_CIAA 0x0009E580
0355 #define PF_PCI_CIAA_VF_NUM_S 12
0356 #define PF_PCI_CIAD 0x0009E500
0357 #define GL_PWR_MODE_CTL 0x000B820C
0358 #define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
0359 #define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30)
0360 #define GLQF_FD_CNT 0x00460018
0361 #define GLQF_FD_CNT_FD_BCNT_S 16
0362 #define GLQF_FD_CNT_FD_BCNT_M ICE_M(0x7FFF, 16)
0363 #define GLQF_FD_SIZE 0x00460010
0364 #define GLQF_FD_SIZE_FD_GSIZE_S 0
0365 #define GLQF_FD_SIZE_FD_GSIZE_M ICE_M(0x7FFF, 0)
0366 #define GLQF_FD_SIZE_FD_BSIZE_S 16
0367 #define GLQF_FD_SIZE_FD_BSIZE_M ICE_M(0x7FFF, 16)
0368 #define GLQF_FDINSET(_i, _j) (0x00412000 + ((_i) * 4 + (_j) * 512))
0369 #define GLQF_FDMASK(_i) (0x00410800 + ((_i) * 4))
0370 #define GLQF_FDMASK_MAX_INDEX 31
0371 #define GLQF_FDMASK_MSK_INDEX_S 0
0372 #define GLQF_FDMASK_MSK_INDEX_M ICE_M(0x1F, 0)
0373 #define GLQF_FDMASK_MASK_S 16
0374 #define GLQF_FDMASK_MASK_M ICE_M(0xFFFF, 16)
0375 #define GLQF_FDMASK_SEL(_i) (0x00410400 + ((_i) * 4))
0376 #define GLQF_FDSWAP(_i, _j) (0x00413000 + ((_i) * 4 + (_j) * 512))
0377 #define GLQF_HMASK(_i) (0x0040FC00 + ((_i) * 4))
0378 #define GLQF_HMASK_MAX_INDEX 31
0379 #define GLQF_HMASK_MSK_INDEX_S 0
0380 #define GLQF_HMASK_MSK_INDEX_M ICE_M(0x1F, 0)
0381 #define GLQF_HMASK_MASK_S 16
0382 #define GLQF_HMASK_MASK_M ICE_M(0xFFFF, 16)
0383 #define GLQF_HMASK_SEL(_i) (0x00410000 + ((_i) * 4))
0384 #define GLQF_HMASK_SEL_MAX_INDEX 127
0385 #define GLQF_HMASK_SEL_MASK_SEL_S 0
0386 #define PFQF_FD_ENA 0x0043A000
0387 #define PFQF_FD_ENA_FD_ENA_M BIT(0)
0388 #define PFQF_FD_SIZE 0x00460100
0389 #define GLDCB_RTCTQ_RXQNUM_S 0
0390 #define GLDCB_RTCTQ_RXQNUM_M ICE_M(0x7FF, 0)
0391 #define GLPRT_BPRCL(_i) (0x00381380 + ((_i) * 8))
0392 #define GLPRT_BPTCL(_i) (0x00381240 + ((_i) * 8))
0393 #define GLPRT_CRCERRS(_i) (0x00380100 + ((_i) * 8))
0394 #define GLPRT_GORCL(_i) (0x00380000 + ((_i) * 8))
0395 #define GLPRT_GOTCL(_i) (0x00380B40 + ((_i) * 8))
0396 #define GLPRT_ILLERRC(_i) (0x003801C0 + ((_i) * 8))
0397 #define GLPRT_LXOFFRXC(_i) (0x003802C0 + ((_i) * 8))
0398 #define GLPRT_LXOFFTXC(_i) (0x00381180 + ((_i) * 8))
0399 #define GLPRT_LXONRXC(_i) (0x00380280 + ((_i) * 8))
0400 #define GLPRT_LXONTXC(_i) (0x00381140 + ((_i) * 8))
0401 #define GLPRT_MLFC(_i) (0x00380040 + ((_i) * 8))
0402 #define GLPRT_MPRCL(_i) (0x00381340 + ((_i) * 8))
0403 #define GLPRT_MPTCL(_i) (0x00381200 + ((_i) * 8))
0404 #define GLPRT_MRFC(_i) (0x00380080 + ((_i) * 8))
0405 #define GLPRT_PRC1023L(_i) (0x00380A00 + ((_i) * 8))
0406 #define GLPRT_PRC127L(_i) (0x00380940 + ((_i) * 8))
0407 #define GLPRT_PRC1522L(_i) (0x00380A40 + ((_i) * 8))
0408 #define GLPRT_PRC255L(_i) (0x00380980 + ((_i) * 8))
0409 #define GLPRT_PRC511L(_i) (0x003809C0 + ((_i) * 8))
0410 #define GLPRT_PRC64L(_i) (0x00380900 + ((_i) * 8))
0411 #define GLPRT_PRC9522L(_i) (0x00380A80 + ((_i) * 8))
0412 #define GLPRT_PTC1023L(_i) (0x00380C80 + ((_i) * 8))
0413 #define GLPRT_PTC127L(_i) (0x00380BC0 + ((_i) * 8))
0414 #define GLPRT_PTC1522L(_i) (0x00380CC0 + ((_i) * 8))
0415 #define GLPRT_PTC255L(_i) (0x00380C00 + ((_i) * 8))
0416 #define GLPRT_PTC511L(_i) (0x00380C40 + ((_i) * 8))
0417 #define GLPRT_PTC64L(_i) (0x00380B80 + ((_i) * 8))
0418 #define GLPRT_PTC9522L(_i) (0x00380D00 + ((_i) * 8))
0419 #define GLPRT_PXOFFRXC(_i, _j) (0x00380500 + ((_i) * 8 + (_j) * 64))
0420 #define GLPRT_PXOFFTXC(_i, _j) (0x00380F40 + ((_i) * 8 + (_j) * 64))
0421 #define GLPRT_PXONRXC(_i, _j) (0x00380300 + ((_i) * 8 + (_j) * 64))
0422 #define GLPRT_PXONTXC(_i, _j) (0x00380D40 + ((_i) * 8 + (_j) * 64))
0423 #define GLPRT_RFC(_i) (0x00380AC0 + ((_i) * 8))
0424 #define GLPRT_RJC(_i) (0x00380B00 + ((_i) * 8))
0425 #define GLPRT_RLEC(_i) (0x00380140 + ((_i) * 8))
0426 #define GLPRT_ROC(_i) (0x00380240 + ((_i) * 8))
0427 #define GLPRT_RUC(_i) (0x00380200 + ((_i) * 8))
0428 #define GLPRT_RXON2OFFCNT(_i, _j) (0x00380700 + ((_i) * 8 + (_j) * 64))
0429 #define GLPRT_TDOLD(_i) (0x00381280 + ((_i) * 8))
0430 #define GLPRT_UPRCL(_i) (0x00381300 + ((_i) * 8))
0431 #define GLPRT_UPTCL(_i) (0x003811C0 + ((_i) * 8))
0432 #define GLSTAT_FD_CNT0L(_i) (0x003A0000 + ((_i) * 8))
0433 #define GLV_BPRCL(_i) (0x003B6000 + ((_i) * 8))
0434 #define GLV_BPTCL(_i) (0x0030E000 + ((_i) * 8))
0435 #define GLV_GORCL(_i) (0x003B0000 + ((_i) * 8))
0436 #define GLV_GOTCL(_i) (0x00300000 + ((_i) * 8))
0437 #define GLV_MPRCL(_i) (0x003B4000 + ((_i) * 8))
0438 #define GLV_MPTCL(_i) (0x0030C000 + ((_i) * 8))
0439 #define GLV_RDPC(_i) (0x00294C04 + ((_i) * 4))
0440 #define GLV_TEPC(_VSI) (0x00312000 + ((_VSI) * 4))
0441 #define GLV_UPRCL(_i) (0x003B2000 + ((_i) * 8))
0442 #define GLV_UPTCL(_i) (0x0030A000 + ((_i) * 8))
0443 #define PRTRPB_RDPC 0x000AC260
0444 #define GLHH_ART_CTL 0x000A41D4
0445 #define GLHH_ART_CTL_ACTIVE_M BIT(0)
0446 #define GLHH_ART_TIME_H 0x000A41D8
0447 #define GLHH_ART_TIME_L 0x000A41DC
0448 #define GLTSYN_AUX_IN_0(_i) (0x000889D8 + ((_i) * 4))
0449 #define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4)
0450 #define GLTSYN_AUX_OUT_0(_i) (0x00088998 + ((_i) * 4))
0451 #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0)
0452 #define GLTSYN_AUX_OUT_0_OUTMOD_M ICE_M(0x3, 1)
0453 #define GLTSYN_CLKO_0(_i) (0x000889B8 + ((_i) * 4))
0454 #define GLTSYN_CMD 0x00088810
0455 #define GLTSYN_CMD_SYNC 0x00088814
0456 #define GLTSYN_ENA(_i) (0x00088808 + ((_i) * 4))
0457 #define GLTSYN_ENA_TSYN_ENA_M BIT(0)
0458 #define GLTSYN_EVNT_H_0(_i) (0x00088970 + ((_i) * 4))
0459 #define GLTSYN_EVNT_L_0(_i) (0x00088968 + ((_i) * 4))
0460 #define GLTSYN_HHTIME_H(_i) (0x00088900 + ((_i) * 4))
0461 #define GLTSYN_HHTIME_L(_i) (0x000888F8 + ((_i) * 4))
0462 #define GLTSYN_INCVAL_H(_i) (0x00088920 + ((_i) * 4))
0463 #define GLTSYN_INCVAL_L(_i) (0x00088918 + ((_i) * 4))
0464 #define GLTSYN_SHADJ_H(_i) (0x00088910 + ((_i) * 4))
0465 #define GLTSYN_SHADJ_L(_i) (0x00088908 + ((_i) * 4))
0466 #define GLTSYN_SHTIME_0(_i) (0x000888E0 + ((_i) * 4))
0467 #define GLTSYN_SHTIME_H(_i) (0x000888F0 + ((_i) * 4))
0468 #define GLTSYN_SHTIME_L(_i) (0x000888E8 + ((_i) * 4))
0469 #define GLTSYN_STAT(_i) (0x000888C0 + ((_i) * 4))
0470 #define GLTSYN_STAT_EVENT0_M BIT(0)
0471 #define GLTSYN_STAT_EVENT1_M BIT(1)
0472 #define GLTSYN_STAT_EVENT2_M BIT(2)
0473 #define GLTSYN_SYNC_DLAY 0x00088818
0474 #define GLTSYN_TGT_H_0(_i) (0x00088930 + ((_i) * 4))
0475 #define GLTSYN_TGT_L_0(_i) (0x00088928 + ((_i) * 4))
0476 #define GLTSYN_TIME_H(_i) (0x000888D8 + ((_i) * 4))
0477 #define GLTSYN_TIME_L(_i) (0x000888D0 + ((_i) * 4))
0478 #define PFHH_SEM 0x000A4200
0479 #define PFHH_SEM_BUSY_M BIT(0)
0480 #define PFTSYN_SEM 0x00088880
0481 #define PFTSYN_SEM_BUSY_M BIT(0)
0482 #define VSIQF_FD_CNT(_VSI) (0x00464000 + ((_VSI) * 4))
0483 #define VSIQF_FD_CNT_FD_GCNT_S 0
0484 #define VSIQF_FD_CNT_FD_GCNT_M ICE_M(0x3FFF, 0)
0485 #define VSIQF_FD_CNT_FD_BCNT_S 16
0486 #define VSIQF_FD_CNT_FD_BCNT_M ICE_M(0x3FFF, 16)
0487 #define VSIQF_FD_SIZE(_VSI) (0x00462000 + ((_VSI) * 4))
0488 #define VSIQF_HKEY_MAX_INDEX 12
0489 #define VSIQF_HLUT_MAX_INDEX 15
0490 #define PFPM_APM 0x000B8080
0491 #define PFPM_APM_APME_M BIT(0)
0492 #define PFPM_WUFC 0x0009DC00
0493 #define PFPM_WUFC_MAG_M BIT(1)
0494 #define PFPM_WUS 0x0009DB80
0495 #define PFPM_WUS_LNKC_M BIT(0)
0496 #define PFPM_WUS_MAG_M BIT(1)
0497 #define PFPM_WUS_MNG_M BIT(3)
0498 #define PFPM_WUS_FW_RST_WK_M BIT(31)
0499 #define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))
0500 #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
0501
0502 #endif
