intel/ice/ice_controlq.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright (c) 2018, Intel Corporation. */
0003
0004 #ifndef _ICE_CONTROLQ_H_
0005 #define _ICE_CONTROLQ_H_
0006
0007 #include "ice_adminq_cmd.h"
0008
0009 /* Maximum buffer lengths for all control queue types */
0010 #define ICE_AQ_MAX_BUF_LEN 4096
0011 #define ICE_MBXQ_MAX_BUF_LEN 4096
0012 #define ICE_SBQ_MAX_BUF_LEN 512
0013
0014 #define ICE_CTL_Q_DESC(R, i) \
0015     (&(((struct ice_aq_desc *)((R).desc_buf.va))[i]))
0016
0017 #define ICE_CTL_Q_DESC_UNUSED(R) \
0018     ((u16)((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
0019            (R)->next_to_clean - (R)->next_to_use - 1))
0020
0021 /* Defines that help manage the driver vs FW API checks.
0022  * Take a look at ice_aq_ver_check in ice_controlq.c for actual usage.
0023  */
0024 #define EXP_FW_API_VER_BRANCH       0x00
0025 #define EXP_FW_API_VER_MAJOR        0x01
0026 #define EXP_FW_API_VER_MINOR        0x05
0027
0028 /* Different control queue types: These are mainly for SW consumption. */
0029 enum ice_ctl_q {
0030     ICE_CTL_Q_UNKNOWN = 0,
0031     ICE_CTL_Q_ADMIN,
0032     ICE_CTL_Q_MAILBOX,
0033     ICE_CTL_Q_SB,
0034 };
0035
0036 /* Control Queue timeout settings - max delay 1s */
0037 #define ICE_CTL_Q_SQ_CMD_TIMEOUT    10000 /* Count 10000 times */
0038 #define ICE_CTL_Q_SQ_CMD_USEC       100   /* Check every 100usec */
0039 #define ICE_CTL_Q_ADMIN_INIT_TIMEOUT    10    /* Count 10 times */
0040 #define ICE_CTL_Q_ADMIN_INIT_MSEC   100   /* Check every 100msec */
0041
0042 struct ice_ctl_q_ring {
0043     void *dma_head;         /* Virtual address to DMA head */
0044     struct ice_dma_mem desc_buf;    /* descriptor ring memory */
0045     void *cmd_buf;          /* command buffer memory */
0046
0047     union {
0048         struct ice_dma_mem *sq_bi;
0049         struct ice_dma_mem *rq_bi;
0050     } r;
0051
0052     u16 count;      /* Number of descriptors */
0053
0054     /* used for interrupt processing */
0055     u16 next_to_use;
0056     u16 next_to_clean;
0057
0058     /* used for queue tracking */
0059     u32 head;
0060     u32 tail;
0061     u32 len;
0062     u32 bah;
0063     u32 bal;
0064     u32 len_mask;
0065     u32 len_ena_mask;
0066     u32 len_crit_mask;
0067     u32 head_mask;
0068 };
0069
0070 /* sq transaction details */
0071 struct ice_sq_cd {
0072     struct ice_aq_desc *wb_desc;
0073 };
0074
0075 #define ICE_CTL_Q_DETAILS(R, i) (&(((struct ice_sq_cd *)((R).cmd_buf))[i]))
0076
0077 /* rq event information */
0078 struct ice_rq_event_info {
0079     struct ice_aq_desc desc;
0080     u16 msg_len;
0081     u16 buf_len;
0082     u8 *msg_buf;
0083 };
0084
0085 /* Control Queue information */
0086 struct ice_ctl_q_info {
0087     enum ice_ctl_q qtype;
0088     struct ice_ctl_q_ring rq;   /* receive queue */
0089     struct ice_ctl_q_ring sq;   /* send queue */
0090     u32 sq_cmd_timeout;     /* send queue cmd write back timeout */
0091     u16 num_rq_entries;     /* receive queue depth */
0092     u16 num_sq_entries;     /* send queue depth */
0093     u16 rq_buf_size;        /* receive queue buffer size */
0094     u16 sq_buf_size;        /* send queue buffer size */
0095     enum ice_aq_err sq_last_status; /* last status on send queue */
0096     struct mutex sq_lock;       /* Send queue lock */
0097     struct mutex rq_lock;       /* Receive queue lock */
0098 };
0099
0100 #endif /* _ICE_CONTROLQ_H_ */