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0001 // SPDX-License-Identifier: GPL-2.0
0002 /* Copyright (c) 2018, Intel Corporation. */
0003 
0004 #include "ice_common.h"
0005 
0006 #define ICE_CQ_INIT_REGS(qinfo, prefix)             \
0007 do {                                \
0008     (qinfo)->sq.head = prefix##_ATQH;           \
0009     (qinfo)->sq.tail = prefix##_ATQT;           \
0010     (qinfo)->sq.len = prefix##_ATQLEN;          \
0011     (qinfo)->sq.bah = prefix##_ATQBAH;          \
0012     (qinfo)->sq.bal = prefix##_ATQBAL;          \
0013     (qinfo)->sq.len_mask = prefix##_ATQLEN_ATQLEN_M;    \
0014     (qinfo)->sq.len_ena_mask = prefix##_ATQLEN_ATQENABLE_M; \
0015     (qinfo)->sq.len_crit_mask = prefix##_ATQLEN_ATQCRIT_M;  \
0016     (qinfo)->sq.head_mask = prefix##_ATQH_ATQH_M;       \
0017     (qinfo)->rq.head = prefix##_ARQH;           \
0018     (qinfo)->rq.tail = prefix##_ARQT;           \
0019     (qinfo)->rq.len = prefix##_ARQLEN;          \
0020     (qinfo)->rq.bah = prefix##_ARQBAH;          \
0021     (qinfo)->rq.bal = prefix##_ARQBAL;          \
0022     (qinfo)->rq.len_mask = prefix##_ARQLEN_ARQLEN_M;    \
0023     (qinfo)->rq.len_ena_mask = prefix##_ARQLEN_ARQENABLE_M; \
0024     (qinfo)->rq.len_crit_mask = prefix##_ARQLEN_ARQCRIT_M;  \
0025     (qinfo)->rq.head_mask = prefix##_ARQH_ARQH_M;       \
0026 } while (0)
0027 
0028 /**
0029  * ice_adminq_init_regs - Initialize AdminQ registers
0030  * @hw: pointer to the hardware structure
0031  *
0032  * This assumes the alloc_sq and alloc_rq functions have already been called
0033  */
0034 static void ice_adminq_init_regs(struct ice_hw *hw)
0035 {
0036     struct ice_ctl_q_info *cq = &hw->adminq;
0037 
0038     ICE_CQ_INIT_REGS(cq, PF_FW);
0039 }
0040 
0041 /**
0042  * ice_mailbox_init_regs - Initialize Mailbox registers
0043  * @hw: pointer to the hardware structure
0044  *
0045  * This assumes the alloc_sq and alloc_rq functions have already been called
0046  */
0047 static void ice_mailbox_init_regs(struct ice_hw *hw)
0048 {
0049     struct ice_ctl_q_info *cq = &hw->mailboxq;
0050 
0051     ICE_CQ_INIT_REGS(cq, PF_MBX);
0052 }
0053 
0054 /**
0055  * ice_sb_init_regs - Initialize Sideband registers
0056  * @hw: pointer to the hardware structure
0057  *
0058  * This assumes the alloc_sq and alloc_rq functions have already been called
0059  */
0060 static void ice_sb_init_regs(struct ice_hw *hw)
0061 {
0062     struct ice_ctl_q_info *cq = &hw->sbq;
0063 
0064     ICE_CQ_INIT_REGS(cq, PF_SB);
0065 }
0066 
0067 /**
0068  * ice_check_sq_alive
0069  * @hw: pointer to the HW struct
0070  * @cq: pointer to the specific Control queue
0071  *
0072  * Returns true if Queue is enabled else false.
0073  */
0074 bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0075 {
0076     /* check both queue-length and queue-enable fields */
0077     if (cq->sq.len && cq->sq.len_mask && cq->sq.len_ena_mask)
0078         return (rd32(hw, cq->sq.len) & (cq->sq.len_mask |
0079                         cq->sq.len_ena_mask)) ==
0080             (cq->num_sq_entries | cq->sq.len_ena_mask);
0081 
0082     return false;
0083 }
0084 
0085 /**
0086  * ice_alloc_ctrlq_sq_ring - Allocate Control Transmit Queue (ATQ) rings
0087  * @hw: pointer to the hardware structure
0088  * @cq: pointer to the specific Control queue
0089  */
0090 static int
0091 ice_alloc_ctrlq_sq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0092 {
0093     size_t size = cq->num_sq_entries * sizeof(struct ice_aq_desc);
0094 
0095     cq->sq.desc_buf.va = dmam_alloc_coherent(ice_hw_to_dev(hw), size,
0096                          &cq->sq.desc_buf.pa,
0097                          GFP_KERNEL | __GFP_ZERO);
0098     if (!cq->sq.desc_buf.va)
0099         return -ENOMEM;
0100     cq->sq.desc_buf.size = size;
0101 
0102     cq->sq.cmd_buf = devm_kcalloc(ice_hw_to_dev(hw), cq->num_sq_entries,
0103                       sizeof(struct ice_sq_cd), GFP_KERNEL);
0104     if (!cq->sq.cmd_buf) {
0105         dmam_free_coherent(ice_hw_to_dev(hw), cq->sq.desc_buf.size,
0106                    cq->sq.desc_buf.va, cq->sq.desc_buf.pa);
0107         cq->sq.desc_buf.va = NULL;
0108         cq->sq.desc_buf.pa = 0;
0109         cq->sq.desc_buf.size = 0;
0110         return -ENOMEM;
0111     }
0112 
0113     return 0;
0114 }
0115 
0116 /**
0117  * ice_alloc_ctrlq_rq_ring - Allocate Control Receive Queue (ARQ) rings
0118  * @hw: pointer to the hardware structure
0119  * @cq: pointer to the specific Control queue
0120  */
0121 static int
0122 ice_alloc_ctrlq_rq_ring(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0123 {
0124     size_t size = cq->num_rq_entries * sizeof(struct ice_aq_desc);
0125 
0126     cq->rq.desc_buf.va = dmam_alloc_coherent(ice_hw_to_dev(hw), size,
0127                          &cq->rq.desc_buf.pa,
0128                          GFP_KERNEL | __GFP_ZERO);
0129     if (!cq->rq.desc_buf.va)
0130         return -ENOMEM;
0131     cq->rq.desc_buf.size = size;
0132     return 0;
0133 }
0134 
0135 /**
0136  * ice_free_cq_ring - Free control queue ring
0137  * @hw: pointer to the hardware structure
0138  * @ring: pointer to the specific control queue ring
0139  *
0140  * This assumes the posted buffers have already been cleaned
0141  * and de-allocated
0142  */
0143 static void ice_free_cq_ring(struct ice_hw *hw, struct ice_ctl_q_ring *ring)
0144 {
0145     dmam_free_coherent(ice_hw_to_dev(hw), ring->desc_buf.size,
0146                ring->desc_buf.va, ring->desc_buf.pa);
0147     ring->desc_buf.va = NULL;
0148     ring->desc_buf.pa = 0;
0149     ring->desc_buf.size = 0;
0150 }
0151 
0152 /**
0153  * ice_alloc_rq_bufs - Allocate pre-posted buffers for the ARQ
0154  * @hw: pointer to the hardware structure
0155  * @cq: pointer to the specific Control queue
0156  */
0157 static int
0158 ice_alloc_rq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0159 {
0160     int i;
0161 
0162     /* We'll be allocating the buffer info memory first, then we can
0163      * allocate the mapped buffers for the event processing
0164      */
0165     cq->rq.dma_head = devm_kcalloc(ice_hw_to_dev(hw), cq->num_rq_entries,
0166                        sizeof(cq->rq.desc_buf), GFP_KERNEL);
0167     if (!cq->rq.dma_head)
0168         return -ENOMEM;
0169     cq->rq.r.rq_bi = (struct ice_dma_mem *)cq->rq.dma_head;
0170 
0171     /* allocate the mapped buffers */
0172     for (i = 0; i < cq->num_rq_entries; i++) {
0173         struct ice_aq_desc *desc;
0174         struct ice_dma_mem *bi;
0175 
0176         bi = &cq->rq.r.rq_bi[i];
0177         bi->va = dmam_alloc_coherent(ice_hw_to_dev(hw),
0178                          cq->rq_buf_size, &bi->pa,
0179                          GFP_KERNEL | __GFP_ZERO);
0180         if (!bi->va)
0181             goto unwind_alloc_rq_bufs;
0182         bi->size = cq->rq_buf_size;
0183 
0184         /* now configure the descriptors for use */
0185         desc = ICE_CTL_Q_DESC(cq->rq, i);
0186 
0187         desc->flags = cpu_to_le16(ICE_AQ_FLAG_BUF);
0188         if (cq->rq_buf_size > ICE_AQ_LG_BUF)
0189             desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB);
0190         desc->opcode = 0;
0191         /* This is in accordance with Admin queue design, there is no
0192          * register for buffer size configuration
0193          */
0194         desc->datalen = cpu_to_le16(bi->size);
0195         desc->retval = 0;
0196         desc->cookie_high = 0;
0197         desc->cookie_low = 0;
0198         desc->params.generic.addr_high =
0199             cpu_to_le32(upper_32_bits(bi->pa));
0200         desc->params.generic.addr_low =
0201             cpu_to_le32(lower_32_bits(bi->pa));
0202         desc->params.generic.param0 = 0;
0203         desc->params.generic.param1 = 0;
0204     }
0205     return 0;
0206 
0207 unwind_alloc_rq_bufs:
0208     /* don't try to free the one that failed... */
0209     i--;
0210     for (; i >= 0; i--) {
0211         dmam_free_coherent(ice_hw_to_dev(hw), cq->rq.r.rq_bi[i].size,
0212                    cq->rq.r.rq_bi[i].va, cq->rq.r.rq_bi[i].pa);
0213         cq->rq.r.rq_bi[i].va = NULL;
0214         cq->rq.r.rq_bi[i].pa = 0;
0215         cq->rq.r.rq_bi[i].size = 0;
0216     }
0217     cq->rq.r.rq_bi = NULL;
0218     devm_kfree(ice_hw_to_dev(hw), cq->rq.dma_head);
0219     cq->rq.dma_head = NULL;
0220 
0221     return -ENOMEM;
0222 }
0223 
0224 /**
0225  * ice_alloc_sq_bufs - Allocate empty buffer structs for the ATQ
0226  * @hw: pointer to the hardware structure
0227  * @cq: pointer to the specific Control queue
0228  */
0229 static int
0230 ice_alloc_sq_bufs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0231 {
0232     int i;
0233 
0234     /* No mapped memory needed yet, just the buffer info structures */
0235     cq->sq.dma_head = devm_kcalloc(ice_hw_to_dev(hw), cq->num_sq_entries,
0236                        sizeof(cq->sq.desc_buf), GFP_KERNEL);
0237     if (!cq->sq.dma_head)
0238         return -ENOMEM;
0239     cq->sq.r.sq_bi = (struct ice_dma_mem *)cq->sq.dma_head;
0240 
0241     /* allocate the mapped buffers */
0242     for (i = 0; i < cq->num_sq_entries; i++) {
0243         struct ice_dma_mem *bi;
0244 
0245         bi = &cq->sq.r.sq_bi[i];
0246         bi->va = dmam_alloc_coherent(ice_hw_to_dev(hw),
0247                          cq->sq_buf_size, &bi->pa,
0248                          GFP_KERNEL | __GFP_ZERO);
0249         if (!bi->va)
0250             goto unwind_alloc_sq_bufs;
0251         bi->size = cq->sq_buf_size;
0252     }
0253     return 0;
0254 
0255 unwind_alloc_sq_bufs:
0256     /* don't try to free the one that failed... */
0257     i--;
0258     for (; i >= 0; i--) {
0259         dmam_free_coherent(ice_hw_to_dev(hw), cq->sq.r.sq_bi[i].size,
0260                    cq->sq.r.sq_bi[i].va, cq->sq.r.sq_bi[i].pa);
0261         cq->sq.r.sq_bi[i].va = NULL;
0262         cq->sq.r.sq_bi[i].pa = 0;
0263         cq->sq.r.sq_bi[i].size = 0;
0264     }
0265     cq->sq.r.sq_bi = NULL;
0266     devm_kfree(ice_hw_to_dev(hw), cq->sq.dma_head);
0267     cq->sq.dma_head = NULL;
0268 
0269     return -ENOMEM;
0270 }
0271 
0272 static int
0273 ice_cfg_cq_regs(struct ice_hw *hw, struct ice_ctl_q_ring *ring, u16 num_entries)
0274 {
0275     /* Clear Head and Tail */
0276     wr32(hw, ring->head, 0);
0277     wr32(hw, ring->tail, 0);
0278 
0279     /* set starting point */
0280     wr32(hw, ring->len, (num_entries | ring->len_ena_mask));
0281     wr32(hw, ring->bal, lower_32_bits(ring->desc_buf.pa));
0282     wr32(hw, ring->bah, upper_32_bits(ring->desc_buf.pa));
0283 
0284     /* Check one register to verify that config was applied */
0285     if (rd32(hw, ring->bal) != lower_32_bits(ring->desc_buf.pa))
0286         return -EIO;
0287 
0288     return 0;
0289 }
0290 
0291 /**
0292  * ice_cfg_sq_regs - configure Control ATQ registers
0293  * @hw: pointer to the hardware structure
0294  * @cq: pointer to the specific Control queue
0295  *
0296  * Configure base address and length registers for the transmit queue
0297  */
0298 static int ice_cfg_sq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0299 {
0300     return ice_cfg_cq_regs(hw, &cq->sq, cq->num_sq_entries);
0301 }
0302 
0303 /**
0304  * ice_cfg_rq_regs - configure Control ARQ register
0305  * @hw: pointer to the hardware structure
0306  * @cq: pointer to the specific Control queue
0307  *
0308  * Configure base address and length registers for the receive (event queue)
0309  */
0310 static int ice_cfg_rq_regs(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0311 {
0312     int status;
0313 
0314     status = ice_cfg_cq_regs(hw, &cq->rq, cq->num_rq_entries);
0315     if (status)
0316         return status;
0317 
0318     /* Update tail in the HW to post pre-allocated buffers */
0319     wr32(hw, cq->rq.tail, (u32)(cq->num_rq_entries - 1));
0320 
0321     return 0;
0322 }
0323 
0324 #define ICE_FREE_CQ_BUFS(hw, qi, ring)                  \
0325 do {                                    \
0326     /* free descriptors */                      \
0327     if ((qi)->ring.r.ring##_bi) {                   \
0328         int i;                          \
0329                                     \
0330         for (i = 0; i < (qi)->num_##ring##_entries; i++)    \
0331             if ((qi)->ring.r.ring##_bi[i].pa) {     \
0332                 dmam_free_coherent(ice_hw_to_dev(hw),   \
0333                     (qi)->ring.r.ring##_bi[i].size, \
0334                     (qi)->ring.r.ring##_bi[i].va,   \
0335                     (qi)->ring.r.ring##_bi[i].pa);  \
0336                     (qi)->ring.r.ring##_bi[i].va = NULL;\
0337                     (qi)->ring.r.ring##_bi[i].pa = 0;\
0338                     (qi)->ring.r.ring##_bi[i].size = 0;\
0339         }                           \
0340     }                               \
0341     /* free the buffer info list */                 \
0342     if ((qi)->ring.cmd_buf)                     \
0343         devm_kfree(ice_hw_to_dev(hw), (qi)->ring.cmd_buf);  \
0344     /* free DMA head */                     \
0345     devm_kfree(ice_hw_to_dev(hw), (qi)->ring.dma_head);     \
0346 } while (0)
0347 
0348 /**
0349  * ice_init_sq - main initialization routine for Control ATQ
0350  * @hw: pointer to the hardware structure
0351  * @cq: pointer to the specific Control queue
0352  *
0353  * This is the main initialization routine for the Control Send Queue
0354  * Prior to calling this function, the driver *MUST* set the following fields
0355  * in the cq->structure:
0356  *     - cq->num_sq_entries
0357  *     - cq->sq_buf_size
0358  *
0359  * Do *NOT* hold the lock when calling this as the memory allocation routines
0360  * called are not going to be atomic context safe
0361  */
0362 static int ice_init_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0363 {
0364     int ret_code;
0365 
0366     if (cq->sq.count > 0) {
0367         /* queue already initialized */
0368         ret_code = -EBUSY;
0369         goto init_ctrlq_exit;
0370     }
0371 
0372     /* verify input for valid configuration */
0373     if (!cq->num_sq_entries || !cq->sq_buf_size) {
0374         ret_code = -EIO;
0375         goto init_ctrlq_exit;
0376     }
0377 
0378     cq->sq.next_to_use = 0;
0379     cq->sq.next_to_clean = 0;
0380 
0381     /* allocate the ring memory */
0382     ret_code = ice_alloc_ctrlq_sq_ring(hw, cq);
0383     if (ret_code)
0384         goto init_ctrlq_exit;
0385 
0386     /* allocate buffers in the rings */
0387     ret_code = ice_alloc_sq_bufs(hw, cq);
0388     if (ret_code)
0389         goto init_ctrlq_free_rings;
0390 
0391     /* initialize base registers */
0392     ret_code = ice_cfg_sq_regs(hw, cq);
0393     if (ret_code)
0394         goto init_ctrlq_free_rings;
0395 
0396     /* success! */
0397     cq->sq.count = cq->num_sq_entries;
0398     goto init_ctrlq_exit;
0399 
0400 init_ctrlq_free_rings:
0401     ICE_FREE_CQ_BUFS(hw, cq, sq);
0402     ice_free_cq_ring(hw, &cq->sq);
0403 
0404 init_ctrlq_exit:
0405     return ret_code;
0406 }
0407 
0408 /**
0409  * ice_init_rq - initialize ARQ
0410  * @hw: pointer to the hardware structure
0411  * @cq: pointer to the specific Control queue
0412  *
0413  * The main initialization routine for the Admin Receive (Event) Queue.
0414  * Prior to calling this function, the driver *MUST* set the following fields
0415  * in the cq->structure:
0416  *     - cq->num_rq_entries
0417  *     - cq->rq_buf_size
0418  *
0419  * Do *NOT* hold the lock when calling this as the memory allocation routines
0420  * called are not going to be atomic context safe
0421  */
0422 static int ice_init_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0423 {
0424     int ret_code;
0425 
0426     if (cq->rq.count > 0) {
0427         /* queue already initialized */
0428         ret_code = -EBUSY;
0429         goto init_ctrlq_exit;
0430     }
0431 
0432     /* verify input for valid configuration */
0433     if (!cq->num_rq_entries || !cq->rq_buf_size) {
0434         ret_code = -EIO;
0435         goto init_ctrlq_exit;
0436     }
0437 
0438     cq->rq.next_to_use = 0;
0439     cq->rq.next_to_clean = 0;
0440 
0441     /* allocate the ring memory */
0442     ret_code = ice_alloc_ctrlq_rq_ring(hw, cq);
0443     if (ret_code)
0444         goto init_ctrlq_exit;
0445 
0446     /* allocate buffers in the rings */
0447     ret_code = ice_alloc_rq_bufs(hw, cq);
0448     if (ret_code)
0449         goto init_ctrlq_free_rings;
0450 
0451     /* initialize base registers */
0452     ret_code = ice_cfg_rq_regs(hw, cq);
0453     if (ret_code)
0454         goto init_ctrlq_free_rings;
0455 
0456     /* success! */
0457     cq->rq.count = cq->num_rq_entries;
0458     goto init_ctrlq_exit;
0459 
0460 init_ctrlq_free_rings:
0461     ICE_FREE_CQ_BUFS(hw, cq, rq);
0462     ice_free_cq_ring(hw, &cq->rq);
0463 
0464 init_ctrlq_exit:
0465     return ret_code;
0466 }
0467 
0468 /**
0469  * ice_shutdown_sq - shutdown the Control ATQ
0470  * @hw: pointer to the hardware structure
0471  * @cq: pointer to the specific Control queue
0472  *
0473  * The main shutdown routine for the Control Transmit Queue
0474  */
0475 static int ice_shutdown_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0476 {
0477     int ret_code = 0;
0478 
0479     mutex_lock(&cq->sq_lock);
0480 
0481     if (!cq->sq.count) {
0482         ret_code = -EBUSY;
0483         goto shutdown_sq_out;
0484     }
0485 
0486     /* Stop firmware AdminQ processing */
0487     wr32(hw, cq->sq.head, 0);
0488     wr32(hw, cq->sq.tail, 0);
0489     wr32(hw, cq->sq.len, 0);
0490     wr32(hw, cq->sq.bal, 0);
0491     wr32(hw, cq->sq.bah, 0);
0492 
0493     cq->sq.count = 0;   /* to indicate uninitialized queue */
0494 
0495     /* free ring buffers and the ring itself */
0496     ICE_FREE_CQ_BUFS(hw, cq, sq);
0497     ice_free_cq_ring(hw, &cq->sq);
0498 
0499 shutdown_sq_out:
0500     mutex_unlock(&cq->sq_lock);
0501     return ret_code;
0502 }
0503 
0504 /**
0505  * ice_aq_ver_check - Check the reported AQ API version.
0506  * @hw: pointer to the hardware structure
0507  *
0508  * Checks if the driver should load on a given AQ API version.
0509  *
0510  * Return: 'true' iff the driver should attempt to load. 'false' otherwise.
0511  */
0512 static bool ice_aq_ver_check(struct ice_hw *hw)
0513 {
0514     if (hw->api_maj_ver > EXP_FW_API_VER_MAJOR) {
0515         /* Major API version is newer than expected, don't load */
0516         dev_warn(ice_hw_to_dev(hw),
0517              "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
0518         return false;
0519     } else if (hw->api_maj_ver == EXP_FW_API_VER_MAJOR) {
0520         if (hw->api_min_ver > (EXP_FW_API_VER_MINOR + 2))
0521             dev_info(ice_hw_to_dev(hw),
0522                  "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
0523         else if ((hw->api_min_ver + 2) < EXP_FW_API_VER_MINOR)
0524             dev_info(ice_hw_to_dev(hw),
0525                  "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
0526     } else {
0527         /* Major API version is older than expected, log a warning */
0528         dev_info(ice_hw_to_dev(hw),
0529              "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
0530     }
0531     return true;
0532 }
0533 
0534 /**
0535  * ice_shutdown_rq - shutdown Control ARQ
0536  * @hw: pointer to the hardware structure
0537  * @cq: pointer to the specific Control queue
0538  *
0539  * The main shutdown routine for the Control Receive Queue
0540  */
0541 static int ice_shutdown_rq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0542 {
0543     int ret_code = 0;
0544 
0545     mutex_lock(&cq->rq_lock);
0546 
0547     if (!cq->rq.count) {
0548         ret_code = -EBUSY;
0549         goto shutdown_rq_out;
0550     }
0551 
0552     /* Stop Control Queue processing */
0553     wr32(hw, cq->rq.head, 0);
0554     wr32(hw, cq->rq.tail, 0);
0555     wr32(hw, cq->rq.len, 0);
0556     wr32(hw, cq->rq.bal, 0);
0557     wr32(hw, cq->rq.bah, 0);
0558 
0559     /* set rq.count to 0 to indicate uninitialized queue */
0560     cq->rq.count = 0;
0561 
0562     /* free ring buffers and the ring itself */
0563     ICE_FREE_CQ_BUFS(hw, cq, rq);
0564     ice_free_cq_ring(hw, &cq->rq);
0565 
0566 shutdown_rq_out:
0567     mutex_unlock(&cq->rq_lock);
0568     return ret_code;
0569 }
0570 
0571 /**
0572  * ice_init_check_adminq - Check version for Admin Queue to know if its alive
0573  * @hw: pointer to the hardware structure
0574  */
0575 static int ice_init_check_adminq(struct ice_hw *hw)
0576 {
0577     struct ice_ctl_q_info *cq = &hw->adminq;
0578     int status;
0579 
0580     status = ice_aq_get_fw_ver(hw, NULL);
0581     if (status)
0582         goto init_ctrlq_free_rq;
0583 
0584     if (!ice_aq_ver_check(hw)) {
0585         status = -EIO;
0586         goto init_ctrlq_free_rq;
0587     }
0588 
0589     return 0;
0590 
0591 init_ctrlq_free_rq:
0592     ice_shutdown_rq(hw, cq);
0593     ice_shutdown_sq(hw, cq);
0594     return status;
0595 }
0596 
0597 /**
0598  * ice_init_ctrlq - main initialization routine for any control Queue
0599  * @hw: pointer to the hardware structure
0600  * @q_type: specific Control queue type
0601  *
0602  * Prior to calling this function, the driver *MUST* set the following fields
0603  * in the cq->structure:
0604  *     - cq->num_sq_entries
0605  *     - cq->num_rq_entries
0606  *     - cq->rq_buf_size
0607  *     - cq->sq_buf_size
0608  *
0609  * NOTE: this function does not initialize the controlq locks
0610  */
0611 static int ice_init_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
0612 {
0613     struct ice_ctl_q_info *cq;
0614     int ret_code;
0615 
0616     switch (q_type) {
0617     case ICE_CTL_Q_ADMIN:
0618         ice_adminq_init_regs(hw);
0619         cq = &hw->adminq;
0620         break;
0621     case ICE_CTL_Q_SB:
0622         ice_sb_init_regs(hw);
0623         cq = &hw->sbq;
0624         break;
0625     case ICE_CTL_Q_MAILBOX:
0626         ice_mailbox_init_regs(hw);
0627         cq = &hw->mailboxq;
0628         break;
0629     default:
0630         return -EINVAL;
0631     }
0632     cq->qtype = q_type;
0633 
0634     /* verify input for valid configuration */
0635     if (!cq->num_rq_entries || !cq->num_sq_entries ||
0636         !cq->rq_buf_size || !cq->sq_buf_size) {
0637         return -EIO;
0638     }
0639 
0640     /* setup SQ command write back timeout */
0641     cq->sq_cmd_timeout = ICE_CTL_Q_SQ_CMD_TIMEOUT;
0642 
0643     /* allocate the ATQ */
0644     ret_code = ice_init_sq(hw, cq);
0645     if (ret_code)
0646         return ret_code;
0647 
0648     /* allocate the ARQ */
0649     ret_code = ice_init_rq(hw, cq);
0650     if (ret_code)
0651         goto init_ctrlq_free_sq;
0652 
0653     /* success! */
0654     return 0;
0655 
0656 init_ctrlq_free_sq:
0657     ice_shutdown_sq(hw, cq);
0658     return ret_code;
0659 }
0660 
0661 /**
0662  * ice_is_sbq_supported - is the sideband queue supported
0663  * @hw: pointer to the hardware structure
0664  *
0665  * Returns true if the sideband control queue interface is
0666  * supported for the device, false otherwise
0667  */
0668 bool ice_is_sbq_supported(struct ice_hw *hw)
0669 {
0670     /* The device sideband queue is only supported on devices with the
0671      * generic MAC type.
0672      */
0673     return hw->mac_type == ICE_MAC_GENERIC;
0674 }
0675 
0676 /**
0677  * ice_get_sbq - returns the right control queue to use for sideband
0678  * @hw: pointer to the hardware structure
0679  */
0680 struct ice_ctl_q_info *ice_get_sbq(struct ice_hw *hw)
0681 {
0682     if (ice_is_sbq_supported(hw))
0683         return &hw->sbq;
0684     return &hw->adminq;
0685 }
0686 
0687 /**
0688  * ice_shutdown_ctrlq - shutdown routine for any control queue
0689  * @hw: pointer to the hardware structure
0690  * @q_type: specific Control queue type
0691  *
0692  * NOTE: this function does not destroy the control queue locks.
0693  */
0694 static void ice_shutdown_ctrlq(struct ice_hw *hw, enum ice_ctl_q q_type)
0695 {
0696     struct ice_ctl_q_info *cq;
0697 
0698     switch (q_type) {
0699     case ICE_CTL_Q_ADMIN:
0700         cq = &hw->adminq;
0701         if (ice_check_sq_alive(hw, cq))
0702             ice_aq_q_shutdown(hw, true);
0703         break;
0704     case ICE_CTL_Q_SB:
0705         cq = &hw->sbq;
0706         break;
0707     case ICE_CTL_Q_MAILBOX:
0708         cq = &hw->mailboxq;
0709         break;
0710     default:
0711         return;
0712     }
0713 
0714     ice_shutdown_sq(hw, cq);
0715     ice_shutdown_rq(hw, cq);
0716 }
0717 
0718 /**
0719  * ice_shutdown_all_ctrlq - shutdown routine for all control queues
0720  * @hw: pointer to the hardware structure
0721  *
0722  * NOTE: this function does not destroy the control queue locks. The driver
0723  * may call this at runtime to shutdown and later restart control queues, such
0724  * as in response to a reset event.
0725  */
0726 void ice_shutdown_all_ctrlq(struct ice_hw *hw)
0727 {
0728     /* Shutdown FW admin queue */
0729     ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);
0730     /* Shutdown PHY Sideband */
0731     if (ice_is_sbq_supported(hw))
0732         ice_shutdown_ctrlq(hw, ICE_CTL_Q_SB);
0733     /* Shutdown PF-VF Mailbox */
0734     ice_shutdown_ctrlq(hw, ICE_CTL_Q_MAILBOX);
0735 }
0736 
0737 /**
0738  * ice_init_all_ctrlq - main initialization routine for all control queues
0739  * @hw: pointer to the hardware structure
0740  *
0741  * Prior to calling this function, the driver MUST* set the following fields
0742  * in the cq->structure for all control queues:
0743  *     - cq->num_sq_entries
0744  *     - cq->num_rq_entries
0745  *     - cq->rq_buf_size
0746  *     - cq->sq_buf_size
0747  *
0748  * NOTE: this function does not initialize the controlq locks.
0749  */
0750 int ice_init_all_ctrlq(struct ice_hw *hw)
0751 {
0752     u32 retry = 0;
0753     int status;
0754 
0755     /* Init FW admin queue */
0756     do {
0757         status = ice_init_ctrlq(hw, ICE_CTL_Q_ADMIN);
0758         if (status)
0759             return status;
0760 
0761         status = ice_init_check_adminq(hw);
0762         if (status != -EIO)
0763             break;
0764 
0765         ice_debug(hw, ICE_DBG_AQ_MSG, "Retry Admin Queue init due to FW critical error\n");
0766         ice_shutdown_ctrlq(hw, ICE_CTL_Q_ADMIN);
0767         msleep(ICE_CTL_Q_ADMIN_INIT_MSEC);
0768     } while (retry++ < ICE_CTL_Q_ADMIN_INIT_TIMEOUT);
0769 
0770     if (status)
0771         return status;
0772     /* sideband control queue (SBQ) interface is not supported on some
0773      * devices. Initialize if supported, else fallback to the admin queue
0774      * interface
0775      */
0776     if (ice_is_sbq_supported(hw)) {
0777         status = ice_init_ctrlq(hw, ICE_CTL_Q_SB);
0778         if (status)
0779             return status;
0780     }
0781     /* Init Mailbox queue */
0782     return ice_init_ctrlq(hw, ICE_CTL_Q_MAILBOX);
0783 }
0784 
0785 /**
0786  * ice_init_ctrlq_locks - Initialize locks for a control queue
0787  * @cq: pointer to the control queue
0788  *
0789  * Initializes the send and receive queue locks for a given control queue.
0790  */
0791 static void ice_init_ctrlq_locks(struct ice_ctl_q_info *cq)
0792 {
0793     mutex_init(&cq->sq_lock);
0794     mutex_init(&cq->rq_lock);
0795 }
0796 
0797 /**
0798  * ice_create_all_ctrlq - main initialization routine for all control queues
0799  * @hw: pointer to the hardware structure
0800  *
0801  * Prior to calling this function, the driver *MUST* set the following fields
0802  * in the cq->structure for all control queues:
0803  *     - cq->num_sq_entries
0804  *     - cq->num_rq_entries
0805  *     - cq->rq_buf_size
0806  *     - cq->sq_buf_size
0807  *
0808  * This function creates all the control queue locks and then calls
0809  * ice_init_all_ctrlq. It should be called once during driver load. If the
0810  * driver needs to re-initialize control queues at run time it should call
0811  * ice_init_all_ctrlq instead.
0812  */
0813 int ice_create_all_ctrlq(struct ice_hw *hw)
0814 {
0815     ice_init_ctrlq_locks(&hw->adminq);
0816     if (ice_is_sbq_supported(hw))
0817         ice_init_ctrlq_locks(&hw->sbq);
0818     ice_init_ctrlq_locks(&hw->mailboxq);
0819 
0820     return ice_init_all_ctrlq(hw);
0821 }
0822 
0823 /**
0824  * ice_destroy_ctrlq_locks - Destroy locks for a control queue
0825  * @cq: pointer to the control queue
0826  *
0827  * Destroys the send and receive queue locks for a given control queue.
0828  */
0829 static void ice_destroy_ctrlq_locks(struct ice_ctl_q_info *cq)
0830 {
0831     mutex_destroy(&cq->sq_lock);
0832     mutex_destroy(&cq->rq_lock);
0833 }
0834 
0835 /**
0836  * ice_destroy_all_ctrlq - exit routine for all control queues
0837  * @hw: pointer to the hardware structure
0838  *
0839  * This function shuts down all the control queues and then destroys the
0840  * control queue locks. It should be called once during driver unload. The
0841  * driver should call ice_shutdown_all_ctrlq if it needs to shut down and
0842  * reinitialize control queues, such as in response to a reset event.
0843  */
0844 void ice_destroy_all_ctrlq(struct ice_hw *hw)
0845 {
0846     /* shut down all the control queues first */
0847     ice_shutdown_all_ctrlq(hw);
0848 
0849     ice_destroy_ctrlq_locks(&hw->adminq);
0850     if (ice_is_sbq_supported(hw))
0851         ice_destroy_ctrlq_locks(&hw->sbq);
0852     ice_destroy_ctrlq_locks(&hw->mailboxq);
0853 }
0854 
0855 /**
0856  * ice_clean_sq - cleans Admin send queue (ATQ)
0857  * @hw: pointer to the hardware structure
0858  * @cq: pointer to the specific Control queue
0859  *
0860  * returns the number of free desc
0861  */
0862 static u16 ice_clean_sq(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0863 {
0864     struct ice_ctl_q_ring *sq = &cq->sq;
0865     u16 ntc = sq->next_to_clean;
0866     struct ice_sq_cd *details;
0867     struct ice_aq_desc *desc;
0868 
0869     desc = ICE_CTL_Q_DESC(*sq, ntc);
0870     details = ICE_CTL_Q_DETAILS(*sq, ntc);
0871 
0872     while (rd32(hw, cq->sq.head) != ntc) {
0873         ice_debug(hw, ICE_DBG_AQ_MSG, "ntc %d head %d.\n", ntc, rd32(hw, cq->sq.head));
0874         memset(desc, 0, sizeof(*desc));
0875         memset(details, 0, sizeof(*details));
0876         ntc++;
0877         if (ntc == sq->count)
0878             ntc = 0;
0879         desc = ICE_CTL_Q_DESC(*sq, ntc);
0880         details = ICE_CTL_Q_DETAILS(*sq, ntc);
0881     }
0882 
0883     sq->next_to_clean = ntc;
0884 
0885     return ICE_CTL_Q_DESC_UNUSED(sq);
0886 }
0887 
0888 /**
0889  * ice_debug_cq
0890  * @hw: pointer to the hardware structure
0891  * @desc: pointer to control queue descriptor
0892  * @buf: pointer to command buffer
0893  * @buf_len: max length of buf
0894  *
0895  * Dumps debug log about control command with descriptor contents.
0896  */
0897 static void ice_debug_cq(struct ice_hw *hw, void *desc, void *buf, u16 buf_len)
0898 {
0899     struct ice_aq_desc *cq_desc = desc;
0900     u16 len;
0901 
0902     if (!IS_ENABLED(CONFIG_DYNAMIC_DEBUG) &&
0903         !((ICE_DBG_AQ_DESC | ICE_DBG_AQ_DESC_BUF) & hw->debug_mask))
0904         return;
0905 
0906     if (!desc)
0907         return;
0908 
0909     len = le16_to_cpu(cq_desc->datalen);
0910 
0911     ice_debug(hw, ICE_DBG_AQ_DESC, "CQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
0912           le16_to_cpu(cq_desc->opcode),
0913           le16_to_cpu(cq_desc->flags),
0914           le16_to_cpu(cq_desc->datalen), le16_to_cpu(cq_desc->retval));
0915     ice_debug(hw, ICE_DBG_AQ_DESC, "\tcookie (h,l) 0x%08X 0x%08X\n",
0916           le32_to_cpu(cq_desc->cookie_high),
0917           le32_to_cpu(cq_desc->cookie_low));
0918     ice_debug(hw, ICE_DBG_AQ_DESC, "\tparam (0,1)  0x%08X 0x%08X\n",
0919           le32_to_cpu(cq_desc->params.generic.param0),
0920           le32_to_cpu(cq_desc->params.generic.param1));
0921     ice_debug(hw, ICE_DBG_AQ_DESC, "\taddr (h,l)   0x%08X 0x%08X\n",
0922           le32_to_cpu(cq_desc->params.generic.addr_high),
0923           le32_to_cpu(cq_desc->params.generic.addr_low));
0924     if (buf && cq_desc->datalen != 0) {
0925         ice_debug(hw, ICE_DBG_AQ_DESC_BUF, "Buffer:\n");
0926         if (buf_len < len)
0927             len = buf_len;
0928 
0929         ice_debug_array(hw, ICE_DBG_AQ_DESC_BUF, 16, 1, buf, len);
0930     }
0931 }
0932 
0933 /**
0934  * ice_sq_done - check if FW has processed the Admin Send Queue (ATQ)
0935  * @hw: pointer to the HW struct
0936  * @cq: pointer to the specific Control queue
0937  *
0938  * Returns true if the firmware has processed all descriptors on the
0939  * admin send queue. Returns false if there are still requests pending.
0940  */
0941 static bool ice_sq_done(struct ice_hw *hw, struct ice_ctl_q_info *cq)
0942 {
0943     /* AQ designers suggest use of head for better
0944      * timing reliability than DD bit
0945      */
0946     return rd32(hw, cq->sq.head) == cq->sq.next_to_use;
0947 }
0948 
0949 /**
0950  * ice_sq_send_cmd - send command to Control Queue (ATQ)
0951  * @hw: pointer to the HW struct
0952  * @cq: pointer to the specific Control queue
0953  * @desc: prefilled descriptor describing the command
0954  * @buf: buffer to use for indirect commands (or NULL for direct commands)
0955  * @buf_size: size of buffer for indirect commands (or 0 for direct commands)
0956  * @cd: pointer to command details structure
0957  *
0958  * This is the main send command routine for the ATQ. It runs the queue,
0959  * cleans the queue, etc.
0960  */
0961 int
0962 ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
0963         struct ice_aq_desc *desc, void *buf, u16 buf_size,
0964         struct ice_sq_cd *cd)
0965 {
0966     struct ice_dma_mem *dma_buf = NULL;
0967     struct ice_aq_desc *desc_on_ring;
0968     bool cmd_completed = false;
0969     struct ice_sq_cd *details;
0970     u32 total_delay = 0;
0971     int status = 0;
0972     u16 retval = 0;
0973     u32 val = 0;
0974 
0975     /* if reset is in progress return a soft error */
0976     if (hw->reset_ongoing)
0977         return -EBUSY;
0978     mutex_lock(&cq->sq_lock);
0979 
0980     cq->sq_last_status = ICE_AQ_RC_OK;
0981 
0982     if (!cq->sq.count) {
0983         ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send queue not initialized.\n");
0984         status = -EIO;
0985         goto sq_send_command_error;
0986     }
0987 
0988     if ((buf && !buf_size) || (!buf && buf_size)) {
0989         status = -EINVAL;
0990         goto sq_send_command_error;
0991     }
0992 
0993     if (buf) {
0994         if (buf_size > cq->sq_buf_size) {
0995             ice_debug(hw, ICE_DBG_AQ_MSG, "Invalid buffer size for Control Send queue: %d.\n",
0996                   buf_size);
0997             status = -EINVAL;
0998             goto sq_send_command_error;
0999         }
1000 
1001         desc->flags |= cpu_to_le16(ICE_AQ_FLAG_BUF);
1002         if (buf_size > ICE_AQ_LG_BUF)
1003             desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB);
1004     }
1005 
1006     val = rd32(hw, cq->sq.head);
1007     if (val >= cq->num_sq_entries) {
1008         ice_debug(hw, ICE_DBG_AQ_MSG, "head overrun at %d in the Control Send Queue ring\n",
1009               val);
1010         status = -EIO;
1011         goto sq_send_command_error;
1012     }
1013 
1014     details = ICE_CTL_Q_DETAILS(cq->sq, cq->sq.next_to_use);
1015     if (cd)
1016         *details = *cd;
1017     else
1018         memset(details, 0, sizeof(*details));
1019 
1020     /* Call clean and check queue available function to reclaim the
1021      * descriptors that were processed by FW/MBX; the function returns the
1022      * number of desc available. The clean function called here could be
1023      * called in a separate thread in case of asynchronous completions.
1024      */
1025     if (ice_clean_sq(hw, cq) == 0) {
1026         ice_debug(hw, ICE_DBG_AQ_MSG, "Error: Control Send Queue is full.\n");
1027         status = -ENOSPC;
1028         goto sq_send_command_error;
1029     }
1030 
1031     /* initialize the temp desc pointer with the right desc */
1032     desc_on_ring = ICE_CTL_Q_DESC(cq->sq, cq->sq.next_to_use);
1033 
1034     /* if the desc is available copy the temp desc to the right place */
1035     memcpy(desc_on_ring, desc, sizeof(*desc_on_ring));
1036 
1037     /* if buf is not NULL assume indirect command */
1038     if (buf) {
1039         dma_buf = &cq->sq.r.sq_bi[cq->sq.next_to_use];
1040         /* copy the user buf into the respective DMA buf */
1041         memcpy(dma_buf->va, buf, buf_size);
1042         desc_on_ring->datalen = cpu_to_le16(buf_size);
1043 
1044         /* Update the address values in the desc with the pa value
1045          * for respective buffer
1046          */
1047         desc_on_ring->params.generic.addr_high =
1048             cpu_to_le32(upper_32_bits(dma_buf->pa));
1049         desc_on_ring->params.generic.addr_low =
1050             cpu_to_le32(lower_32_bits(dma_buf->pa));
1051     }
1052 
1053     /* Debug desc and buffer */
1054     ice_debug(hw, ICE_DBG_AQ_DESC, "ATQ: Control Send queue desc and buffer:\n");
1055 
1056     ice_debug_cq(hw, (void *)desc_on_ring, buf, buf_size);
1057 
1058     (cq->sq.next_to_use)++;
1059     if (cq->sq.next_to_use == cq->sq.count)
1060         cq->sq.next_to_use = 0;
1061     wr32(hw, cq->sq.tail, cq->sq.next_to_use);
1062 
1063     do {
1064         if (ice_sq_done(hw, cq))
1065             break;
1066 
1067         udelay(ICE_CTL_Q_SQ_CMD_USEC);
1068         total_delay++;
1069     } while (total_delay < cq->sq_cmd_timeout);
1070 
1071     /* if ready, copy the desc back to temp */
1072     if (ice_sq_done(hw, cq)) {
1073         memcpy(desc, desc_on_ring, sizeof(*desc));
1074         if (buf) {
1075             /* get returned length to copy */
1076             u16 copy_size = le16_to_cpu(desc->datalen);
1077 
1078             if (copy_size > buf_size) {
1079                 ice_debug(hw, ICE_DBG_AQ_MSG, "Return len %d > than buf len %d\n",
1080                       copy_size, buf_size);
1081                 status = -EIO;
1082             } else {
1083                 memcpy(buf, dma_buf->va, copy_size);
1084             }
1085         }
1086         retval = le16_to_cpu(desc->retval);
1087         if (retval) {
1088             ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send Queue command 0x%04X completed with error 0x%X\n",
1089                   le16_to_cpu(desc->opcode),
1090                   retval);
1091 
1092             /* strip off FW internal code */
1093             retval &= 0xff;
1094         }
1095         cmd_completed = true;
1096         if (!status && retval != ICE_AQ_RC_OK)
1097             status = -EIO;
1098         cq->sq_last_status = (enum ice_aq_err)retval;
1099     }
1100 
1101     ice_debug(hw, ICE_DBG_AQ_MSG, "ATQ: desc and buffer writeback:\n");
1102 
1103     ice_debug_cq(hw, (void *)desc, buf, buf_size);
1104 
1105     /* save writeback AQ if requested */
1106     if (details->wb_desc)
1107         memcpy(details->wb_desc, desc_on_ring,
1108                sizeof(*details->wb_desc));
1109 
1110     /* update the error if time out occurred */
1111     if (!cmd_completed) {
1112         if (rd32(hw, cq->rq.len) & cq->rq.len_crit_mask ||
1113             rd32(hw, cq->sq.len) & cq->sq.len_crit_mask) {
1114             ice_debug(hw, ICE_DBG_AQ_MSG, "Critical FW error.\n");
1115             status = -EIO;
1116         } else {
1117             ice_debug(hw, ICE_DBG_AQ_MSG, "Control Send Queue Writeback timeout.\n");
1118             status = -EIO;
1119         }
1120     }
1121 
1122 sq_send_command_error:
1123     mutex_unlock(&cq->sq_lock);
1124     return status;
1125 }
1126 
1127 /**
1128  * ice_fill_dflt_direct_cmd_desc - AQ descriptor helper function
1129  * @desc: pointer to the temp descriptor (non DMA mem)
1130  * @opcode: the opcode can be used to decide which flags to turn off or on
1131  *
1132  * Fill the desc with default values
1133  */
1134 void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode)
1135 {
1136     /* zero out the desc */
1137     memset(desc, 0, sizeof(*desc));
1138     desc->opcode = cpu_to_le16(opcode);
1139     desc->flags = cpu_to_le16(ICE_AQ_FLAG_SI);
1140 }
1141 
1142 /**
1143  * ice_clean_rq_elem
1144  * @hw: pointer to the HW struct
1145  * @cq: pointer to the specific Control queue
1146  * @e: event info from the receive descriptor, includes any buffers
1147  * @pending: number of events that could be left to process
1148  *
1149  * This function cleans one Admin Receive Queue element and returns
1150  * the contents through e. It can also return how many events are
1151  * left to process through 'pending'.
1152  */
1153 int
1154 ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
1155           struct ice_rq_event_info *e, u16 *pending)
1156 {
1157     u16 ntc = cq->rq.next_to_clean;
1158     enum ice_aq_err rq_last_status;
1159     struct ice_aq_desc *desc;
1160     struct ice_dma_mem *bi;
1161     int ret_code = 0;
1162     u16 desc_idx;
1163     u16 datalen;
1164     u16 flags;
1165     u16 ntu;
1166 
1167     /* pre-clean the event info */
1168     memset(&e->desc, 0, sizeof(e->desc));
1169 
1170     /* take the lock before we start messing with the ring */
1171     mutex_lock(&cq->rq_lock);
1172 
1173     if (!cq->rq.count) {
1174         ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive queue not initialized.\n");
1175         ret_code = -EIO;
1176         goto clean_rq_elem_err;
1177     }
1178 
1179     /* set next_to_use to head */
1180     ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
1181 
1182     if (ntu == ntc) {
1183         /* nothing to do - shouldn't need to update ring's values */
1184         ret_code = -EALREADY;
1185         goto clean_rq_elem_out;
1186     }
1187 
1188     /* now clean the next descriptor */
1189     desc = ICE_CTL_Q_DESC(cq->rq, ntc);
1190     desc_idx = ntc;
1191 
1192     rq_last_status = (enum ice_aq_err)le16_to_cpu(desc->retval);
1193     flags = le16_to_cpu(desc->flags);
1194     if (flags & ICE_AQ_FLAG_ERR) {
1195         ret_code = -EIO;
1196         ice_debug(hw, ICE_DBG_AQ_MSG, "Control Receive Queue Event 0x%04X received with error 0x%X\n",
1197               le16_to_cpu(desc->opcode), rq_last_status);
1198     }
1199     memcpy(&e->desc, desc, sizeof(e->desc));
1200     datalen = le16_to_cpu(desc->datalen);
1201     e->msg_len = min_t(u16, datalen, e->buf_len);
1202     if (e->msg_buf && e->msg_len)
1203         memcpy(e->msg_buf, cq->rq.r.rq_bi[desc_idx].va, e->msg_len);
1204 
1205     ice_debug(hw, ICE_DBG_AQ_DESC, "ARQ: desc and buffer:\n");
1206 
1207     ice_debug_cq(hw, (void *)desc, e->msg_buf, cq->rq_buf_size);
1208 
1209     /* Restore the original datalen and buffer address in the desc,
1210      * FW updates datalen to indicate the event message size
1211      */
1212     bi = &cq->rq.r.rq_bi[ntc];
1213     memset(desc, 0, sizeof(*desc));
1214 
1215     desc->flags = cpu_to_le16(ICE_AQ_FLAG_BUF);
1216     if (cq->rq_buf_size > ICE_AQ_LG_BUF)
1217         desc->flags |= cpu_to_le16(ICE_AQ_FLAG_LB);
1218     desc->datalen = cpu_to_le16(bi->size);
1219     desc->params.generic.addr_high = cpu_to_le32(upper_32_bits(bi->pa));
1220     desc->params.generic.addr_low = cpu_to_le32(lower_32_bits(bi->pa));
1221 
1222     /* set tail = the last cleaned desc index. */
1223     wr32(hw, cq->rq.tail, ntc);
1224     /* ntc is updated to tail + 1 */
1225     ntc++;
1226     if (ntc == cq->num_rq_entries)
1227         ntc = 0;
1228     cq->rq.next_to_clean = ntc;
1229     cq->rq.next_to_use = ntu;
1230 
1231 clean_rq_elem_out:
1232     /* Set pending if needed, unlock and return */
1233     if (pending) {
1234         /* re-read HW head to calculate actual pending messages */
1235         ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
1236         *pending = (u16)((ntc > ntu ? cq->rq.count : 0) + (ntu - ntc));
1237     }
1238 clean_rq_elem_err:
1239     mutex_unlock(&cq->rq_lock);
1240 
1241     return ret_code;
1242 }
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