intel/iavf/iavf_register.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2013 - 2018 Intel Corporation. */
0003
0004 #ifndef _IAVF_REGISTER_H_
0005 #define _IAVF_REGISTER_H_
0006
0007 #define IAVF_VF_ARQBAH1 0x00006000 /* Reset: EMPR */
0008 #define IAVF_VF_ARQBAL1 0x00006C00 /* Reset: EMPR */
0009 #define IAVF_VF_ARQH1 0x00007400 /* Reset: EMPR */
0010 #define IAVF_VF_ARQH1_ARQH_SHIFT 0
0011 #define IAVF_VF_ARQH1_ARQH_MASK IAVF_MASK(0x3FF, IAVF_VF_ARQH1_ARQH_SHIFT)
0012 #define IAVF_VF_ARQLEN1 0x00008000 /* Reset: EMPR */
0013 #define IAVF_VF_ARQLEN1_ARQVFE_SHIFT 28
0014 #define IAVF_VF_ARQLEN1_ARQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQVFE_SHIFT)
0015 #define IAVF_VF_ARQLEN1_ARQOVFL_SHIFT 29
0016 #define IAVF_VF_ARQLEN1_ARQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQOVFL_SHIFT)
0017 #define IAVF_VF_ARQLEN1_ARQCRIT_SHIFT 30
0018 #define IAVF_VF_ARQLEN1_ARQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQCRIT_SHIFT)
0019 #define IAVF_VF_ARQLEN1_ARQENABLE_SHIFT 31
0020 #define IAVF_VF_ARQLEN1_ARQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ARQLEN1_ARQENABLE_SHIFT)
0021 #define IAVF_VF_ARQT1 0x00007000 /* Reset: EMPR */
0022 #define IAVF_VF_ATQBAH1 0x00007800 /* Reset: EMPR */
0023 #define IAVF_VF_ATQBAL1 0x00007C00 /* Reset: EMPR */
0024 #define IAVF_VF_ATQH1 0x00006400 /* Reset: EMPR */
0025 #define IAVF_VF_ATQLEN1 0x00006800 /* Reset: EMPR */
0026 #define IAVF_VF_ATQLEN1_ATQVFE_SHIFT 28
0027 #define IAVF_VF_ATQLEN1_ATQVFE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQVFE_SHIFT)
0028 #define IAVF_VF_ATQLEN1_ATQOVFL_SHIFT 29
0029 #define IAVF_VF_ATQLEN1_ATQOVFL_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQOVFL_SHIFT)
0030 #define IAVF_VF_ATQLEN1_ATQCRIT_SHIFT 30
0031 #define IAVF_VF_ATQLEN1_ATQCRIT_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQCRIT_SHIFT)
0032 #define IAVF_VF_ATQLEN1_ATQENABLE_SHIFT 31
0033 #define IAVF_VF_ATQLEN1_ATQENABLE_MASK IAVF_MASK(0x1, IAVF_VF_ATQLEN1_ATQENABLE_SHIFT)
0034 #define IAVF_VF_ATQT1 0x00008400 /* Reset: EMPR */
0035 #define IAVF_VFGEN_RSTAT 0x00008800 /* Reset: VFR */
0036 #define IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT 0
0037 #define IAVF_VFGEN_RSTAT_VFR_STATE_MASK IAVF_MASK(0x3, IAVF_VFGEN_RSTAT_VFR_STATE_SHIFT)
0038 #define IAVF_VFINT_DYN_CTL01 0x00005C00 /* Reset: VFR */
0039 #define IAVF_VFINT_DYN_CTL01_INTENA_SHIFT 0
0040 #define IAVF_VFINT_DYN_CTL01_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTL01_INTENA_SHIFT)
0041 #define IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT 3
0042 #define IAVF_VFINT_DYN_CTL01_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTL01_ITR_INDX_SHIFT)
0043 #define IAVF_VFINT_DYN_CTLN1(_INTVF) (0x00003800 + ((_INTVF) * 4)) /* _i=0...15 */ /* Reset: VFR */
0044 #define IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT 0
0045 #define IAVF_VFINT_DYN_CTLN1_INTENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_INTENA_SHIFT)
0046 #define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT 2
0047 #define IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_SWINT_TRIG_SHIFT)
0048 #define IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT 3
0049 #define IAVF_VFINT_DYN_CTLN1_ITR_INDX_MASK IAVF_MASK(0x3, IAVF_VFINT_DYN_CTLN1_ITR_INDX_SHIFT)
0050 #define IAVF_VFINT_DYN_CTLN1_INTERVAL_SHIFT 5
0051 #define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT 24
0052 #define IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_SW_ITR_INDX_ENA_SHIFT)
0053 #define IAVF_VFINT_ICR0_ENA1 0x00005000 /* Reset: CORER */
0054 #define IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT 30
0055 #define IAVF_VFINT_ICR0_ENA1_ADMINQ_MASK IAVF_MASK(0x1, IAVF_VFINT_ICR0_ENA1_ADMINQ_SHIFT)
0056 #define IAVF_VFINT_ICR0_ENA1_RSVD_SHIFT 31
0057 #define IAVF_VFINT_ICR01 0x00004800 /* Reset: CORER */
0058 #define IAVF_VFINT_ITRN1(_i, _INTVF) (0x00002800 + ((_i) * 64 + (_INTVF) * 4)) /* _i=0...2, _INTVF=0...15 */ /* Reset: VFR */
0059 #define IAVF_QRX_TAIL1(_Q) (0x00002000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: CORER */
0060 #define IAVF_QTX_TAIL1(_Q) (0x00000000 + ((_Q) * 4)) /* _i=0...15 */ /* Reset: PFR */
0061 #define IAVF_VFQF_HENA(_i) (0x0000C400 + ((_i) * 4)) /* _i=0...1 */ /* Reset: CORER */
0062 #define IAVF_VFQF_HKEY(_i) (0x0000CC00 + ((_i) * 4)) /* _i=0...12 */ /* Reset: CORER */
0063 #define IAVF_VFQF_HKEY_MAX_INDEX 12
0064 #define IAVF_VFQF_HLUT(_i) (0x0000D000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: CORER */
0065 #define IAVF_VFQF_HLUT_MAX_INDEX 15
0066 #define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT 30
0067 #define IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_MASK IAVF_MASK(0x1, IAVF_VFINT_DYN_CTLN1_WB_ON_ITR_SHIFT)
0068 #endif /* _IAVF_REGISTER_H_ */