intel/iavf/iavf_adminq_cmd.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2013 - 2018 Intel Corporation. */
0003
0004 #ifndef _IAVF_ADMINQ_CMD_H_
0005 #define _IAVF_ADMINQ_CMD_H_
0006
0007 /* This header file defines the iavf Admin Queue commands and is shared between
0008  * iavf Firmware and Software.
0009  *
0010  * This file needs to comply with the Linux Kernel coding style.
0011  */
0012
0013 #define IAVF_FW_API_VERSION_MAJOR   0x0001
0014 #define IAVF_FW_API_VERSION_MINOR_X722  0x0005
0015 #define IAVF_FW_API_VERSION_MINOR_X710  0x0008
0016
0017 #define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \
0018                     IAVF_FW_API_VERSION_MINOR_X710 : \
0019                     IAVF_FW_API_VERSION_MINOR_X722)
0020
0021 /* API version 1.7 implements additional link and PHY-specific APIs  */
0022 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
0023
0024 struct iavf_aq_desc {
0025     __le16 flags;
0026     __le16 opcode;
0027     __le16 datalen;
0028     __le16 retval;
0029     __le32 cookie_high;
0030     __le32 cookie_low;
0031     union {
0032         struct {
0033             __le32 param0;
0034             __le32 param1;
0035             __le32 param2;
0036             __le32 param3;
0037         } internal;
0038         struct {
0039             __le32 param0;
0040             __le32 param1;
0041             __le32 addr_high;
0042             __le32 addr_low;
0043         } external;
0044         u8 raw[16];
0045     } params;
0046 };
0047
0048 /* Flags sub-structure
0049  * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
0050  * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
0051  */
0052
0053 /* command flags and offsets*/
0054 #define IAVF_AQ_FLAG_DD_SHIFT   0
0055 #define IAVF_AQ_FLAG_CMP_SHIFT  1
0056 #define IAVF_AQ_FLAG_ERR_SHIFT  2
0057 #define IAVF_AQ_FLAG_VFE_SHIFT  3
0058 #define IAVF_AQ_FLAG_LB_SHIFT   9
0059 #define IAVF_AQ_FLAG_RD_SHIFT   10
0060 #define IAVF_AQ_FLAG_VFC_SHIFT  11
0061 #define IAVF_AQ_FLAG_BUF_SHIFT  12
0062 #define IAVF_AQ_FLAG_SI_SHIFT   13
0063 #define IAVF_AQ_FLAG_EI_SHIFT   14
0064 #define IAVF_AQ_FLAG_FE_SHIFT   15
0065
0066 #define IAVF_AQ_FLAG_DD     BIT(IAVF_AQ_FLAG_DD_SHIFT)  /* 0x1    */
0067 #define IAVF_AQ_FLAG_CMP    BIT(IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2    */
0068 #define IAVF_AQ_FLAG_ERR    BIT(IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4    */
0069 #define IAVF_AQ_FLAG_VFE    BIT(IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8    */
0070 #define IAVF_AQ_FLAG_LB     BIT(IAVF_AQ_FLAG_LB_SHIFT)  /* 0x200  */
0071 #define IAVF_AQ_FLAG_RD     BIT(IAVF_AQ_FLAG_RD_SHIFT)  /* 0x400  */
0072 #define IAVF_AQ_FLAG_VFC    BIT(IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800  */
0073 #define IAVF_AQ_FLAG_BUF    BIT(IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
0074 #define IAVF_AQ_FLAG_SI     BIT(IAVF_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
0075 #define IAVF_AQ_FLAG_EI     BIT(IAVF_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
0076 #define IAVF_AQ_FLAG_FE     BIT(IAVF_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
0077
0078 /* error codes */
0079 enum iavf_admin_queue_err {
0080     IAVF_AQ_RC_OK       = 0,  /* success */
0081     IAVF_AQ_RC_EPERM    = 1,  /* Operation not permitted */
0082     IAVF_AQ_RC_ENOENT   = 2,  /* No such element */
0083     IAVF_AQ_RC_ESRCH    = 3,  /* Bad opcode */
0084     IAVF_AQ_RC_EINTR    = 4,  /* operation interrupted */
0085     IAVF_AQ_RC_EIO      = 5,  /* I/O error */
0086     IAVF_AQ_RC_ENXIO    = 6,  /* No such resource */
0087     IAVF_AQ_RC_E2BIG    = 7,  /* Arg too long */
0088     IAVF_AQ_RC_EAGAIN   = 8,  /* Try again */
0089     IAVF_AQ_RC_ENOMEM   = 9,  /* Out of memory */
0090     IAVF_AQ_RC_EACCES   = 10, /* Permission denied */
0091     IAVF_AQ_RC_EFAULT   = 11, /* Bad address */
0092     IAVF_AQ_RC_EBUSY    = 12, /* Device or resource busy */
0093     IAVF_AQ_RC_EEXIST   = 13, /* object already exists */
0094     IAVF_AQ_RC_EINVAL   = 14, /* Invalid argument */
0095     IAVF_AQ_RC_ENOTTY   = 15, /* Not a typewriter */
0096     IAVF_AQ_RC_ENOSPC   = 16, /* No space left or alloc failure */
0097     IAVF_AQ_RC_ENOSYS   = 17, /* Function not implemented */
0098     IAVF_AQ_RC_ERANGE   = 18, /* Parameter out of range */
0099     IAVF_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
0100     IAVF_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
0101     IAVF_AQ_RC_EMODE    = 21, /* Op not allowed in current dev mode */
0102     IAVF_AQ_RC_EFBIG    = 22, /* File too large */
0103 };
0104
0105 /* Admin Queue command opcodes */
0106 enum iavf_admin_queue_opc {
0107     /* aq commands */
0108     iavf_aqc_opc_get_version    = 0x0001,
0109     iavf_aqc_opc_driver_version = 0x0002,
0110     iavf_aqc_opc_queue_shutdown = 0x0003,
0111     iavf_aqc_opc_set_pf_context = 0x0004,
0112
0113     /* resource ownership */
0114     iavf_aqc_opc_request_resource   = 0x0008,
0115     iavf_aqc_opc_release_resource   = 0x0009,
0116
0117     iavf_aqc_opc_list_func_capabilities = 0x000A,
0118     iavf_aqc_opc_list_dev_capabilities  = 0x000B,
0119
0120     /* Proxy commands */
0121     iavf_aqc_opc_set_proxy_config       = 0x0104,
0122     iavf_aqc_opc_set_ns_proxy_table_entry   = 0x0105,
0123
0124     /* LAA */
0125     iavf_aqc_opc_mac_address_read   = 0x0107,
0126     iavf_aqc_opc_mac_address_write  = 0x0108,
0127
0128     /* PXE */
0129     iavf_aqc_opc_clear_pxe_mode = 0x0110,
0130
0131     /* WoL commands */
0132     iavf_aqc_opc_set_wol_filter = 0x0120,
0133     iavf_aqc_opc_get_wake_reason    = 0x0121,
0134
0135     /* internal switch commands */
0136     iavf_aqc_opc_get_switch_config      = 0x0200,
0137     iavf_aqc_opc_add_statistics     = 0x0201,
0138     iavf_aqc_opc_remove_statistics      = 0x0202,
0139     iavf_aqc_opc_set_port_parameters    = 0x0203,
0140     iavf_aqc_opc_get_switch_resource_alloc  = 0x0204,
0141     iavf_aqc_opc_set_switch_config      = 0x0205,
0142     iavf_aqc_opc_rx_ctl_reg_read        = 0x0206,
0143     iavf_aqc_opc_rx_ctl_reg_write       = 0x0207,
0144
0145     iavf_aqc_opc_add_vsi            = 0x0210,
0146     iavf_aqc_opc_update_vsi_parameters  = 0x0211,
0147     iavf_aqc_opc_get_vsi_parameters     = 0x0212,
0148
0149     iavf_aqc_opc_add_pv         = 0x0220,
0150     iavf_aqc_opc_update_pv_parameters   = 0x0221,
0151     iavf_aqc_opc_get_pv_parameters      = 0x0222,
0152
0153     iavf_aqc_opc_add_veb            = 0x0230,
0154     iavf_aqc_opc_update_veb_parameters  = 0x0231,
0155     iavf_aqc_opc_get_veb_parameters     = 0x0232,
0156
0157     iavf_aqc_opc_delete_element     = 0x0243,
0158
0159     iavf_aqc_opc_add_macvlan        = 0x0250,
0160     iavf_aqc_opc_remove_macvlan     = 0x0251,
0161     iavf_aqc_opc_add_vlan           = 0x0252,
0162     iavf_aqc_opc_remove_vlan        = 0x0253,
0163     iavf_aqc_opc_set_vsi_promiscuous_modes  = 0x0254,
0164     iavf_aqc_opc_add_tag            = 0x0255,
0165     iavf_aqc_opc_remove_tag         = 0x0256,
0166     iavf_aqc_opc_add_multicast_etag     = 0x0257,
0167     iavf_aqc_opc_remove_multicast_etag  = 0x0258,
0168     iavf_aqc_opc_update_tag         = 0x0259,
0169     iavf_aqc_opc_add_control_packet_filter  = 0x025A,
0170     iavf_aqc_opc_remove_control_packet_filter   = 0x025B,
0171     iavf_aqc_opc_add_cloud_filters      = 0x025C,
0172     iavf_aqc_opc_remove_cloud_filters   = 0x025D,
0173     iavf_aqc_opc_clear_wol_switch_filters   = 0x025E,
0174
0175     iavf_aqc_opc_add_mirror_rule    = 0x0260,
0176     iavf_aqc_opc_delete_mirror_rule = 0x0261,
0177
0178     /* Dynamic Device Personalization */
0179     iavf_aqc_opc_write_personalization_profile  = 0x0270,
0180     iavf_aqc_opc_get_personalization_profile_list   = 0x0271,
0181
0182     /* DCB commands */
0183     iavf_aqc_opc_dcb_ignore_pfc = 0x0301,
0184     iavf_aqc_opc_dcb_updated    = 0x0302,
0185     iavf_aqc_opc_set_dcb_parameters = 0x0303,
0186
0187     /* TX scheduler */
0188     iavf_aqc_opc_configure_vsi_bw_limit     = 0x0400,
0189     iavf_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
0190     iavf_aqc_opc_configure_vsi_tc_bw        = 0x0407,
0191     iavf_aqc_opc_query_vsi_bw_config        = 0x0408,
0192     iavf_aqc_opc_query_vsi_ets_sla_config       = 0x040A,
0193     iavf_aqc_opc_configure_switching_comp_bw_limit  = 0x0410,
0194
0195     iavf_aqc_opc_enable_switching_comp_ets          = 0x0413,
0196     iavf_aqc_opc_modify_switching_comp_ets          = 0x0414,
0197     iavf_aqc_opc_disable_switching_comp_ets         = 0x0415,
0198     iavf_aqc_opc_configure_switching_comp_ets_bw_limit  = 0x0416,
0199     iavf_aqc_opc_configure_switching_comp_bw_config     = 0x0417,
0200     iavf_aqc_opc_query_switching_comp_ets_config        = 0x0418,
0201     iavf_aqc_opc_query_port_ets_config          = 0x0419,
0202     iavf_aqc_opc_query_switching_comp_bw_config     = 0x041A,
0203     iavf_aqc_opc_suspend_port_tx                = 0x041B,
0204     iavf_aqc_opc_resume_port_tx             = 0x041C,
0205     iavf_aqc_opc_configure_partition_bw         = 0x041D,
0206     /* hmc */
0207     iavf_aqc_opc_query_hmc_resource_profile = 0x0500,
0208     iavf_aqc_opc_set_hmc_resource_profile   = 0x0501,
0209
0210     /* phy commands*/
0211     iavf_aqc_opc_get_phy_abilities      = 0x0600,
0212     iavf_aqc_opc_set_phy_config     = 0x0601,
0213     iavf_aqc_opc_set_mac_config     = 0x0603,
0214     iavf_aqc_opc_set_link_restart_an    = 0x0605,
0215     iavf_aqc_opc_get_link_status        = 0x0607,
0216     iavf_aqc_opc_set_phy_int_mask       = 0x0613,
0217     iavf_aqc_opc_get_local_advt_reg     = 0x0614,
0218     iavf_aqc_opc_set_local_advt_reg     = 0x0615,
0219     iavf_aqc_opc_get_partner_advt       = 0x0616,
0220     iavf_aqc_opc_set_lb_modes       = 0x0618,
0221     iavf_aqc_opc_get_phy_wol_caps       = 0x0621,
0222     iavf_aqc_opc_set_phy_debug      = 0x0622,
0223     iavf_aqc_opc_upload_ext_phy_fm      = 0x0625,
0224     iavf_aqc_opc_run_phy_activity       = 0x0626,
0225     iavf_aqc_opc_set_phy_register       = 0x0628,
0226     iavf_aqc_opc_get_phy_register       = 0x0629,
0227
0228     /* NVM commands */
0229     iavf_aqc_opc_nvm_read           = 0x0701,
0230     iavf_aqc_opc_nvm_erase          = 0x0702,
0231     iavf_aqc_opc_nvm_update         = 0x0703,
0232     iavf_aqc_opc_nvm_config_read        = 0x0704,
0233     iavf_aqc_opc_nvm_config_write       = 0x0705,
0234     iavf_aqc_opc_oem_post_update        = 0x0720,
0235     iavf_aqc_opc_thermal_sensor     = 0x0721,
0236
0237     /* virtualization commands */
0238     iavf_aqc_opc_send_msg_to_pf     = 0x0801,
0239     iavf_aqc_opc_send_msg_to_vf     = 0x0802,
0240     iavf_aqc_opc_send_msg_to_peer       = 0x0803,
0241
0242     /* alternate structure */
0243     iavf_aqc_opc_alternate_write        = 0x0900,
0244     iavf_aqc_opc_alternate_write_indirect   = 0x0901,
0245     iavf_aqc_opc_alternate_read     = 0x0902,
0246     iavf_aqc_opc_alternate_read_indirect    = 0x0903,
0247     iavf_aqc_opc_alternate_write_done   = 0x0904,
0248     iavf_aqc_opc_alternate_set_mode     = 0x0905,
0249     iavf_aqc_opc_alternate_clear_port   = 0x0906,
0250
0251     /* LLDP commands */
0252     iavf_aqc_opc_lldp_get_mib   = 0x0A00,
0253     iavf_aqc_opc_lldp_update_mib    = 0x0A01,
0254     iavf_aqc_opc_lldp_add_tlv   = 0x0A02,
0255     iavf_aqc_opc_lldp_update_tlv    = 0x0A03,
0256     iavf_aqc_opc_lldp_delete_tlv    = 0x0A04,
0257     iavf_aqc_opc_lldp_stop      = 0x0A05,
0258     iavf_aqc_opc_lldp_start     = 0x0A06,
0259
0260     /* Tunnel commands */
0261     iavf_aqc_opc_add_udp_tunnel = 0x0B00,
0262     iavf_aqc_opc_del_udp_tunnel = 0x0B01,
0263     iavf_aqc_opc_set_rss_key    = 0x0B02,
0264     iavf_aqc_opc_set_rss_lut    = 0x0B03,
0265     iavf_aqc_opc_get_rss_key    = 0x0B04,
0266     iavf_aqc_opc_get_rss_lut    = 0x0B05,
0267
0268     /* Async Events */
0269     iavf_aqc_opc_event_lan_overflow     = 0x1001,
0270
0271     /* OEM commands */
0272     iavf_aqc_opc_oem_parameter_change   = 0xFE00,
0273     iavf_aqc_opc_oem_device_status_change   = 0xFE01,
0274     iavf_aqc_opc_oem_ocsd_initialize    = 0xFE02,
0275     iavf_aqc_opc_oem_ocbb_initialize    = 0xFE03,
0276
0277     /* debug commands */
0278     iavf_aqc_opc_debug_read_reg     = 0xFF03,
0279     iavf_aqc_opc_debug_write_reg        = 0xFF04,
0280     iavf_aqc_opc_debug_modify_reg       = 0xFF07,
0281     iavf_aqc_opc_debug_dump_internals   = 0xFF08,
0282 };
0283
0284 /* command structures and indirect data structures */
0285
0286 /* Structure naming conventions:
0287  * - no suffix for direct command descriptor structures
0288  * - _data for indirect sent data
0289  * - _resp for indirect return data (data which is both will use _data)
0290  * - _completion for direct return data
0291  * - _element_ for repeated elements (may also be _data or _resp)
0292  *
0293  * Command structures are expected to overlay the params.raw member of the basic
0294  * descriptor, and as such cannot exceed 16 bytes in length.
0295  */
0296
0297 /* This macro is used to generate a compilation error if a structure
0298  * is not exactly the correct length. It gives a divide by zero error if the
0299  * structure is not of the correct size, otherwise it creates an enum that is
0300  * never used.
0301  */
0302 #define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \
0303     { iavf_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) }
0304
0305 /* This macro is used extensively to ensure that command structures are 16
0306  * bytes in length as they have to map to the raw array of that size.
0307  */
0308 #define IAVF_CHECK_CMD_LENGTH(X)    IAVF_CHECK_STRUCT_LEN(16, X)
0309
0310 /* Queue Shutdown (direct 0x0003) */
0311 struct iavf_aqc_queue_shutdown {
0312     __le32  driver_unloading;
0313 #define IAVF_AQ_DRIVER_UNLOADING    0x1
0314     u8  reserved[12];
0315 };
0316
0317 IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);
0318
0319 struct iavf_aqc_vsi_properties_data {
0320     /* first 96 byte are written by SW */
0321     __le16  valid_sections;
0322 #define IAVF_AQ_VSI_PROP_SWITCH_VALID       0x0001
0323 #define IAVF_AQ_VSI_PROP_SECURITY_VALID     0x0002
0324 #define IAVF_AQ_VSI_PROP_VLAN_VALID     0x0004
0325 #define IAVF_AQ_VSI_PROP_CAS_PV_VALID       0x0008
0326 #define IAVF_AQ_VSI_PROP_INGRESS_UP_VALID   0x0010
0327 #define IAVF_AQ_VSI_PROP_EGRESS_UP_VALID    0x0020
0328 #define IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID    0x0040
0329 #define IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID    0x0080
0330 #define IAVF_AQ_VSI_PROP_OUTER_UP_VALID     0x0100
0331 #define IAVF_AQ_VSI_PROP_SCHED_VALID        0x0200
0332     /* switch section */
0333     __le16  switch_id; /* 12bit id combined with flags below */
0334 #define IAVF_AQ_VSI_SW_ID_SHIFT     0x0000
0335 #define IAVF_AQ_VSI_SW_ID_MASK      (0xFFF << IAVF_AQ_VSI_SW_ID_SHIFT)
0336 #define IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
0337 #define IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
0338 #define IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
0339     u8  sw_reserved[2];
0340     /* security section */
0341     u8  sec_flags;
0342 #define IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD    0x01
0343 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK    0x02
0344 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
0345     u8  sec_reserved;
0346     /* VLAN section */
0347     __le16  pvid; /* VLANS include priority bits */
0348     __le16  fcoe_pvid;
0349     u8  port_vlan_flags;
0350 #define IAVF_AQ_VSI_PVLAN_MODE_SHIFT    0x00
0351 #define IAVF_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
0352                      IAVF_AQ_VSI_PVLAN_MODE_SHIFT)
0353 #define IAVF_AQ_VSI_PVLAN_MODE_TAGGED   0x01
0354 #define IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
0355 #define IAVF_AQ_VSI_PVLAN_MODE_ALL  0x03
0356 #define IAVF_AQ_VSI_PVLAN_INSERT_PVID   0x04
0357 #define IAVF_AQ_VSI_PVLAN_EMOD_SHIFT    0x03
0358 #define IAVF_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
0359                      IAVF_AQ_VSI_PVLAN_EMOD_SHIFT)
0360 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
0361 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_UP   0x08
0362 #define IAVF_AQ_VSI_PVLAN_EMOD_STR  0x10
0363 #define IAVF_AQ_VSI_PVLAN_EMOD_NOTHING  0x18
0364     u8  pvlan_reserved[3];
0365     /* ingress egress up sections */
0366     __le32  ingress_table; /* bitmap, 3 bits per up */
0367 #define IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT  0
0368 #define IAVF_AQ_VSI_UP_TABLE_UP0_MASK   (0x7 << \
0369                      IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT)
0370 #define IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT  3
0371 #define IAVF_AQ_VSI_UP_TABLE_UP1_MASK   (0x7 << \
0372                      IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT)
0373 #define IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT  6
0374 #define IAVF_AQ_VSI_UP_TABLE_UP2_MASK   (0x7 << \
0375                      IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT)
0376 #define IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT  9
0377 #define IAVF_AQ_VSI_UP_TABLE_UP3_MASK   (0x7 << \
0378                      IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT)
0379 #define IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT  12
0380 #define IAVF_AQ_VSI_UP_TABLE_UP4_MASK   (0x7 << \
0381                      IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT)
0382 #define IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT  15
0383 #define IAVF_AQ_VSI_UP_TABLE_UP5_MASK   (0x7 << \
0384                      IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT)
0385 #define IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT  18
0386 #define IAVF_AQ_VSI_UP_TABLE_UP6_MASK   (0x7 << \
0387                      IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT)
0388 #define IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT  21
0389 #define IAVF_AQ_VSI_UP_TABLE_UP7_MASK   (0x7 << \
0390                      IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT)
0391     __le32  egress_table;   /* same defines as for ingress table */
0392     /* cascaded PV section */
0393     __le16  cas_pv_tag;
0394     u8  cas_pv_flags;
0395 #define IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT       0x00
0396 #define IAVF_AQ_VSI_CAS_PV_TAGX_MASK        (0x03 << \
0397                          IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT)
0398 #define IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE       0x00
0399 #define IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE      0x01
0400 #define IAVF_AQ_VSI_CAS_PV_TAGX_COPY        0x02
0401 #define IAVF_AQ_VSI_CAS_PV_INSERT_TAG       0x10
0402 #define IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE       0x20
0403 #define IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG  0x40
0404     u8  cas_pv_reserved;
0405     /* queue mapping section */
0406     __le16  mapping_flags;
0407 #define IAVF_AQ_VSI_QUE_MAP_CONTIG  0x0
0408 #define IAVF_AQ_VSI_QUE_MAP_NONCONTIG   0x1
0409     __le16  queue_mapping[16];
0410 #define IAVF_AQ_VSI_QUEUE_SHIFT     0x0
0411 #define IAVF_AQ_VSI_QUEUE_MASK      (0x7FF << IAVF_AQ_VSI_QUEUE_SHIFT)
0412     __le16  tc_mapping[8];
0413 #define IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
0414 #define IAVF_AQ_VSI_TC_QUE_OFFSET_MASK  (0x1FF << \
0415                      IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT)
0416 #define IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
0417 #define IAVF_AQ_VSI_TC_QUE_NUMBER_MASK  (0x7 << \
0418                      IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT)
0419     /* queueing option section */
0420     u8  queueing_opt_flags;
0421 #define IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA   0x04
0422 #define IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
0423 #define IAVF_AQ_VSI_QUE_OPT_TCP_ENA 0x10
0424 #define IAVF_AQ_VSI_QUE_OPT_FCOE_ENA    0x20
0425 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_PF  0x00
0426 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
0427     u8  queueing_opt_reserved[3];
0428     /* scheduler section */
0429     u8  up_enable_bits;
0430     u8  sched_reserved;
0431     /* outer up section */
0432     __le32  outer_up_table; /* same structure and defines as ingress tbl */
0433     u8  cmd_reserved[8];
0434     /* last 32 bytes are written by FW */
0435     __le16  qs_handle[8];
0436 #define IAVF_AQ_VSI_QS_HANDLE_INVALID   0xFFFF
0437     __le16  stat_counter_idx;
0438     __le16  sched_id;
0439     u8  resp_reserved[12];
0440 };
0441
0442 IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);
0443
0444 /* Get VEB Parameters (direct 0x0232)
0445  * uses iavf_aqc_switch_seid for the descriptor
0446  */
0447 struct iavf_aqc_get_veb_parameters_completion {
0448     __le16  seid;
0449     __le16  switch_id;
0450     __le16  veb_flags; /* only the first/last flags from 0x0230 is valid */
0451     __le16  statistic_index;
0452     __le16  vebs_used;
0453     __le16  vebs_free;
0454     u8  reserved[4];
0455 };
0456
0457 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);
0458
0459 #define IAVF_LINK_SPEED_100MB_SHIFT 0x1
0460 #define IAVF_LINK_SPEED_1000MB_SHIFT    0x2
0461 #define IAVF_LINK_SPEED_10GB_SHIFT  0x3
0462 #define IAVF_LINK_SPEED_40GB_SHIFT  0x4
0463 #define IAVF_LINK_SPEED_20GB_SHIFT  0x5
0464 #define IAVF_LINK_SPEED_25GB_SHIFT  0x6
0465
0466 enum iavf_aq_link_speed {
0467     IAVF_LINK_SPEED_UNKNOWN = 0,
0468     IAVF_LINK_SPEED_100MB   = BIT(IAVF_LINK_SPEED_100MB_SHIFT),
0469     IAVF_LINK_SPEED_1GB = BIT(IAVF_LINK_SPEED_1000MB_SHIFT),
0470     IAVF_LINK_SPEED_10GB    = BIT(IAVF_LINK_SPEED_10GB_SHIFT),
0471     IAVF_LINK_SPEED_40GB    = BIT(IAVF_LINK_SPEED_40GB_SHIFT),
0472     IAVF_LINK_SPEED_20GB    = BIT(IAVF_LINK_SPEED_20GB_SHIFT),
0473     IAVF_LINK_SPEED_25GB    = BIT(IAVF_LINK_SPEED_25GB_SHIFT),
0474 };
0475
0476 /* Send to PF command (indirect 0x0801) id is only used by PF
0477  * Send to VF command (indirect 0x0802) id is only used by PF
0478  * Send to Peer PF command (indirect 0x0803)
0479  */
0480 struct iavf_aqc_pf_vf_message {
0481     __le32  id;
0482     u8  reserved[4];
0483     __le32  addr_high;
0484     __le32  addr_low;
0485 };
0486
0487 IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
0488
0489 struct iavf_aqc_get_set_rss_key {
0490 #define IAVF_AQC_SET_RSS_KEY_VSI_VALID      BIT(15)
0491 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT   0
0492 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK    (0x3FF << \
0493                     IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
0494     __le16  vsi_id;
0495     u8  reserved[6];
0496     __le32  addr_high;
0497     __le32  addr_low;
0498 };
0499
0500 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_key);
0501
0502 struct iavf_aqc_get_set_rss_key_data {
0503     u8 standard_rss_key[0x28];
0504     u8 extended_hash_key[0xc];
0505 };
0506
0507 IAVF_CHECK_STRUCT_LEN(0x34, iavf_aqc_get_set_rss_key_data);
0508
0509 struct  iavf_aqc_get_set_rss_lut {
0510 #define IAVF_AQC_SET_RSS_LUT_VSI_VALID      BIT(15)
0511 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT   0
0512 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK    (0x3FF << \
0513                     IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
0514     __le16  vsi_id;
0515 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT   0
0516 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK \
0517                 BIT(IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
0518
0519 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
0520 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF  1
0521     __le16  flags;
0522     u8  reserved[4];
0523     __le32  addr_high;
0524     __le32  addr_low;
0525 };
0526
0527 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);
0528 #endif /* _IAVF_ADMINQ_CMD_H_ */