intel/i40e/i40e_xsk.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Copyright(c) 2018 Intel Corporation. */
0003
0004 #ifndef _I40E_XSK_H_
0005 #define _I40E_XSK_H_
0006
0007 /* This value should match the pragma in the loop_unrolled_for
0008  * macro. Why 4? It is strictly empirical. It seems to be a good
0009  * compromise between the advantage of having simultaneous outstanding
0010  * reads to the DMA array that can hide each others latency and the
0011  * disadvantage of having a larger code path.
0012  */
0013 #define PKTS_PER_BATCH 4
0014
0015 #ifdef __clang__
0016 #define loop_unrolled_for _Pragma("clang loop unroll_count(4)") for
0017 #elif __GNUC__ >= 8
0018 #define loop_unrolled_for _Pragma("GCC unroll 4") for
0019 #else
0020 #define loop_unrolled_for for
0021 #endif
0022
0023 struct i40e_vsi;
0024 struct xsk_buff_pool;
0025
0026 int i40e_queue_pair_disable(struct i40e_vsi *vsi, int queue_pair);
0027 int i40e_queue_pair_enable(struct i40e_vsi *vsi, int queue_pair);
0028 int i40e_xsk_pool_setup(struct i40e_vsi *vsi, struct xsk_buff_pool *pool,
0029             u16 qid);
0030 bool i40e_alloc_rx_buffers_zc(struct i40e_ring *rx_ring, u16 cleaned_count);
0031 int i40e_clean_rx_irq_zc(struct i40e_ring *rx_ring, int budget);
0032
0033 bool i40e_clean_xdp_tx_irq(struct i40e_vsi *vsi, struct i40e_ring *tx_ring);
0034 int i40e_xsk_wakeup(struct net_device *dev, u32 queue_id, u32 flags);
0035 int i40e_alloc_rx_bi_zc(struct i40e_ring *rx_ring);
0036 void i40e_clear_rx_bi_zc(struct i40e_ring *rx_ring);
0037
0038 #endif /* _I40E_XSK_H_ */